WO2009092624A1 - A method of fabricating epitaxially grown layers on a composite structure - Google Patents
A method of fabricating epitaxially grown layers on a composite structure Download PDFInfo
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- WO2009092624A1 WO2009092624A1 PCT/EP2009/050086 EP2009050086W WO2009092624A1 WO 2009092624 A1 WO2009092624 A1 WO 2009092624A1 EP 2009050086 W EP2009050086 W EP 2009050086W WO 2009092624 A1 WO2009092624 A1 WO 2009092624A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/01—Manufacture or treatment
- H10H20/011—Manufacture or treatment of bodies, e.g. forming semiconductor layers
- H10H20/018—Bonding of wafers
Definitions
- the present invention relates to the fabrication of layers grown epitaxially on a composite structure and to the detachment of such a layer from the structure. More precisely, the invention relates to the detachment of the support from the remainder of the composite structure after epitaxy, thereby enabling the support to be recycled, and the epitaxially grown layer to be released or to be transferred onto a final support if it is not self-supporting.
- Group III/N materials are endowed with particular electronic properties, such as a wide band-gap, which renders them highly advantageous for use in optics, optoelectronics, and electronics.
- such materials are not available in bulk form, in quantities, in diameters, or at prices that mean that they can be used on a large industrial scale. They are fabricated by heteroepitaxy on substrates or structures that are adapted to produce crystalline growth with a minimal defect density. Possible structures for heteroepitaxial growth are composites provided with a thin seed film that has a lattice parameter that is adapted to the parameter of the material to be grown epitaxially in order to minimize the formation of crystal defects.
- the support substrate for such structures is selected so that its thermal expansion coefficient is close to that of the material to be grown epitaxially, thereby avoiding cracking of the epitaxially grown material during cooling thereof .
- Such growth structures do not have the properties required for optimal use in devices for use in optoelectronics, optics, or electronics. It is thus necessary to transfer the layer of epitaxially grown material to a target support with more appropriate properties (thermal and electrical conductivity, optical properties, etc) or to detach the epitaxially grown layer from the support when it is sufficiently thick to be self-supporting.
- the support must always be detached from the remainder of the growth structure, in a manner that is non-destructive for the support in order to allow it to be recycled.
- European patent EP-A-O 898 307 describes how to unbond a thin wafer covered with integrated circuits bonded to a support substrate that provides the rigidity necessary to the wafer for easier manipulation during the treatments that have to be carried out on the integrated circuits.
- the document describes unbonding at the bonding interface between the wafer and the support by use of an oxide bonding layer formed by PECVD. That oxide has the peculiarity of having OH species that diffuse to the bonding interface under the action of a heat treatment (600 0 C to 1350 0 C) carried out after bonding stabilization annealing and the desired treatments carried out on the integrated circuits. Said species develop until a gas is formed and constitutes bubbles that diffuse and that are concentrated locally at the bonding interface, i.e.
- That phenomenon encourages weakening of the bonding interface until the support substrate unbonds completely at its interface with the bonding layer, thereby liberating the wafer that is integral with the bonding layer from the support so that the integrated circuits can be used.
- International patent document WO-A-02/084722 describes the fabrication of a substrate that can be released via a specific interface, or intermediate layer, having mechanical strength that is kept to a controlled level, compatible with subsequent release. Said release may take place after forming the components on the substrate or an epitaxy step. That interface is created by treating one of the surfaces to be bonded to control its roughness or its hydrophilic characteristics and to allow assembly of the substrates with a force that is sufficient to carry out the subsequent steps but that is compatible with subsequent release. Said release may be accomplished by an external mechanical, chemical, and/or photonic action. The mechanical strength of the interface may be reinforced if necessary by heat treatments while remaining compatible with subsequent detachment .
- WO-A-2005/034218 describes bonding a substrate and a superstrate of silicon, each of which has a thermal oxide layer formed thereon. An intermediate layer of oxide of silicon is formed on one of them. It is doped with phosphorus and/or boron to form a PSG (phosphor-silicate glass) or PBSG (boro-phospho-silicate glass) type material that can be deformed plastically. Applying a heat treatment to the structure at 900 0 C to 1100 0 C causes the irreversible formation of micro-bubbles or microcavities in the bonding layer. Said micro-bubbles may be used for a variety of applications and in particular to weaken the bonding interface to allow the structure to be dismantled.
- WO-A-2005/074022 describes the fabrication of a "liberatable" structure since the two principal layers may be liberated from each other by an external action, for example a mechanical action.
- Bonding is achieved via a reversible connection obtained by forming a layer of a first material comprising within it a second material such as silicon or germanium that is capable, following a heat treatment, of generating nano-particles that are different from the first material.
- the layer of first material may be formed from deposited or thermally formed SiC ⁇ 2 .
- the bonding force procured by that type of connection is not modified during subsequent heat treatments.
- the connection may then be used to liberate the two substrates by the action of a mechanical force.
- the detachment solutions described in those documents cannot be used with structures that are intended to carry out epitaxial growth and that comprise materials with high thermal expansion coefficients such as sapphire, lithium tantalate, etc.
- the bonding force obtained with the methods described in those documents is too low to be able, during heat treatments, to withstand the thermal expansion stresses induced by the materials used, or, during heteroepitaxy, to withstand the stresses induced by the crystalline lattice parameter differences.
- too low a bonding force means that a good quality structure for epitaxy cannot be formed, nor can the moment of detachment of the support substrate be controlled by applying an appropriate thermal budget.
- the support substrate risks becoming detached from the seed film at any time during the epitaxy process.
- the invention aims to overcome the above-mentioned disadvantages and it proposes a solution allowing epitaxial growth, in particular of materials from group III/N, on composite structures comprising a thin film and a support substrate produced with materials that have high thermal expansion coefficients (7 x 10 ⁇ 6 K "1 or more over the temperature range under consideration (20 0 C to 1200 0 C) ) and wherein bonding between the thin film and the support substrate is capable of withstanding the stresses and the temperatures employed for at least a predetermined period of epitaxy, while allowing detachment of the support substrate by rupture of the bonding layer at a predetermined moment, i.e. before or after the end of epitaxy, or at the same time as the end of epitaxy.
- a method of fabricating materials by epitaxy comprising a step of epitaxial growth of at least one layer of a material on a composite structure comprising at least one thin film bonded to a support substrate, a bonding layer being formed by deposition between the support substrate and the thin film, the method of the invention being characterized in that the bonding layer of oxide is formed by low pressure chemical vapor deposition (LPCVD) of a layer of oxide of silicon on the bonding face of the support substrate and/or on the bonding face of the thin film, in that the thin film has a thickness that is less than or equal to the thickness of said oxide layer, and in that the method includes a heat treatment carried out at a temperature that is higher than the temperature for depositing the layer of oxide of silicon and for a predetermined period.
- LPCVD low pressure chemical vapor deposition
- the thickness of the layer of oxide of silicon is greater than or equal to that of the thin film. This means that the stresses applied at the bonding layer during high temperature epitaxial growth can be reduced, as well as the risk of plastic deformations occurring in this bonding layer.
- the composite structure of the invention comprises a deposited bonding layer of oxide of silicon that is designed not to creep readily at the temperatures and stresses to which it is subjected during epitaxy. Since creep of the oxide results in the formation of microcavities, it is possible to initiate the formation of microcavities at a predetermined moment during epitaxy or thereafter by applying a heat treatment at a temperature that is above the oxide deposition temperature. This heat treatment can obtain creep of the bonding layer of oxide by increasing both the temperature of the oxide and that of the composite structure, causing the generation of stresses due to differences in the thermal expansion coefficients.
- the bonding layer of oxide formed by low pressure chemical vapor deposition has a thickness that is greater than the thickness of the thin film and is preferably in the range from approximately 0.2 ⁇ m [micrometer] to 0.75 ⁇ m, and more preferably in the range approximately 0.2 ⁇ m to 0.45 ⁇ m.
- the epitaxial growth step may partially or completely contribute to the heat treatment to obtain creep of the oxide of silicon and the development of microcavities .
- the temperature during epitaxial growth is then higher than the oxide deposition temperature. Knowing this temperature, it is possible to determine the time after which development of the microcavities is such that it sufficiently weakens the oxide layer to allow it to rupture. Epitaxy may be carried out to provide only a part of the heat treatment necessary for rupture of the oxide layer.
- epitaxy may also be carried out over a period that can produce rupture of the oxide layer; in similar vein, it can be continued after rupture of the layer so as to produce the desired thickness of epitaxially grown material.
- the heat treatment step may also be carried out after the epitaxial growth step. This applies in particular when epitaxy is carried out at a temperature below the oxide deposition temperature.
- the heat treatment is carried out for a period that can of itself provoke detachment of the support substrate.
- the heat treatment that can initiate the formation of microcavities is carried out for a period that can develop the microcavities sufficiently to obtain splitting/fracture at the bonding layer of oxide.
- the detachment method further comprises, after the heat treatment step, a complementary step of applying a mechanical separation stress at the bonding layer of oxide to provoke detachment of the support substrate.
- This complementary step may also consist of a chemical attack of the bonding layer of oxide to provoke detachment of the support substrate. Either way, because of the prior formation of microcavities , the heat treatment can weaken the bonding layer of oxide so that fracture /splitting is then readily obtained by mechanical or chemical action.
- the material of the bonding layer formed by low pressure chemical vapor deposition is an oxide of silicon formed from precursors selected from silane, dichlorosilane and TEOS.
- the method further comprises, prior to bonding, a step of densification heat treatment of the layer of oxide of silicon deposited by low pressure chemical vapor deposition on the bonding face of the support substrate and/or on the bonding face of the thin film.
- This densification heat treatment step can further increase the temperature behavior of the deposited oxide of silicon vis-a-vis the formation of microcavities. This step can, if necessary, reduce the ratio of the thicknesses of the thin film and of the deposited layer of oxide of silicon.
- the densification heat treatment step is carried out at a temperature that is higher than the temperature for deposition of the bonding layer of oxide but over a much shorter period than that which provokes rupture of the layer of oxide of silicon.
- the thin film may be obtained using the Smart Cut® technique.
- the method then further comprises : • a step of implantation, by bombardment of one face of a donor substrate using ions to form, at a predetermined depth in the substrate, a layer of weakness defining the thin film in the upper portion of the substrate; • a step of bonding, by placing the donor substrate in intimate contact with the support substrate; • a step of detachment of the thin film in contact with the support substrate, by splitting at the layer of weakness formed in the donor substrate.
- the thin film may be produced with:
- a step of bonding stabilization annealing may be carried out at a temperature that is higher than that at which the oxide of silicon is deposited without microcavities appearing in the deposited layer of oxide.
- the invention relates to the production of at least one layer of binary, ternary, or quaternary type III/V and III/N material such as GaN, AlGaN, InGaN, or InAlGaN.
- the epitaxial growth is carried out for a predetermined period corresponding to the formation of a thickness of semiconductor material or a cumulative thickness of a layer of semiconductor material and thin film of at least 10 micrometers.
- This thickness is sufficient for the layer of conductive material, alone or with the thin film, to have a sufficient mechanical strength and flatness, if it is not manipulated, to withstand the conditions for epitaxy.
- a new epitaxial growth step of the same material or another III /N material may be carried out in the same epitaxy equipment.
- epitaxial growth is carried out for a predetermined period corresponding to the formation of a thickness of semiconductor material or a cumulative thickness of a layer of semiconductor material and thin film of at least 100 micrometers.
- a thickness means that it is possible to form a layer of semiconductor material or a 11 self-supported" material layer/thin film assembly, i.e. that is sufficiently rigid and strong to be manipulated without the need for a support.
- the free surface of the layer of epitaxially grown semiconductor material may be bonded to a target support before detaching the support substrate.
- Figures IA to IL are diagrammatic sectional views showing the production of a composite structure, epitaxy and detachment of the support substrate in accordance with one implementation of the invention
- Figure 2 is a flowchart of the steps carried out in Figures IA to IL; • Figures 3A to 3G are diagrammatic sectional views showing the production of a composite structure, epitaxy and detachment of the support substrate during epitaxy in accordance with another implementation of the invention; and • Figure 4 is a flowchart of the steps carried out in Figures 3A to 3G.
- the present invention proposes the production of a composite structure allowing both the formation by epitaxy of layers of type III/N materials of good quality and detachment of the support substrate from the composition structure before or after the end of epitaxy, or substantially at the same time as the end of epitaxy.
- the invention proposes a novel concept of a composite structure comprising a bonding layer of oxide located between the support substrate and the thin film and in which the formation of microcavities can be controlled.
- the composite structure of the invention means that microcavities in the bonding layer of oxide can be controlled both as regards preventing their appearance during heat treatments applied to the structure before and during at least a portion of the epitaxy and encouraging their formation or even their development during epitaxy or thereafter with a view to detachment of the support substrate.
- the composite structure comprises at least one thin film of semiconductor material bonded to a support substrate via a bonding layer of oxide of silicon between the support substrate and the thin film, the thin film and the support substrate having a mean thermal expansion coefficient of 7 x 1(T 6 K "1 or more over a temperature range of 20 0 C to 1200 0 C in order to be able to reach a certain level of stress in the structure by application of a heat treatment .
- PECVD low pressure chemical vapor deposition
- LPCVD low pressure chemical vapor deposition
- deposited oxide which, in contrast to a thermal oxide, is not stoichiometric (the oxide deposited has a composition of the type Si x O Y H z ) . Further, this deposited oxide is less dense and does not have the same properties as the thermal oxide. Even after densification annealing, this deposited oxide of silicon is still temperature-unstable, in particular during high temperature treatments (> 800 0 C) .
- microcavities appear exclusively at the bonding layer of deposited oxide of silicon once the oxide deposition temperature is exceeded, . They are visible at the surface of the thin film of sapphire by the formation of irreversible blisters which "buckle" its surface and render it unsuitable for epitaxy because the surface is no longer smooth and the lattice parameter is distorted.
- microcavities are larger when the thermal expansion coefficients of the materials used are high, compared with that of the deposited oxide of silicon, at the temperatures reached during fabrication of the composite structure or during its subsequent use (epitaxy). In general, the formation and development of microcavities within the deposited layer of oxide of silicon has been observed at any temperature exceeding the oxide of silicon deposition temperature.
- the appearance of microcavities in the oxide of silicon may be explained by the transition from an elastic mode of deformation to a plastic mode of deformation, which is thus not reversible.
- Elastic deformation is characterized by a modification of the initial state of the oxide, for example under the action of a mechanical stress, and its return to the initial state once the stress is withdrawn.
- Plastic deformation results in irreversible deformation, after which the oxide cannot regain its initial state once the mechanical stress is withdrawn.
- the transition to plastic deformation occurs when a threshold for the various parameters is reached in the oxide. This transition is linked to the temperature, to the creep characteristics of the oxide of silicon and to the stress applied by the difference in the expansion of the bonded materials and of the oxide.
- the creep temperature of the oxide of silicon is one of the characteristics of the oxide that indicates the temperature beyond which the oxide changes from an elastic deformation mode to a plastic deformation mode when it is not subjected to a stress. Temperature increases the amount of creep of the oxide. Thus, the level of stress to be applied to provoke the formation of microcavities in the deposited layer of oxide is lower when the oxide has an intrinsic capacity to creep easily, especially due to the temperature applied vis-a ⁇ vis its creep temperature.
- the Applicant has studied the temperature behavior of oxides obtained by different deposition techniques and has discovered that an oxide of silicon deposited by low pressure chemical vapor deposition, also termed LPCVD, can reduce its capacity to creep.
- the experiments carried out by the Applicant have shown that the properties of the oxide have a substantial influence on the formation of microcavities in the bonding layer and that these properties can be influenced by the deposition technique employed and by the precursor used.
- oxide of silicon produced from a silane precursor deposited at 800 0 C by LPCVD also termed HTO silane, HTO meaning high temperature oxide
- HTO silane oxide of silicon produced from a silane precursor deposited at 800 0 C by LPCVD
- HTO silane HTO meaning high temperature oxide
- PECVD PECVD
- HTO DCS HTO DCS
- the temperature behavior of the deposited oxide may be improved by using an oxide of silicon obtained by LPCVD deposition that has a density that is as close as possible to that of the thermal oxide.
- a densification anneal may be applied to the oxide of silicon deposited by LPCVD prior to bonding.
- the invention also proposes reducing that stress by forming (by transfer or by mechanical or chemical thinning) a thin film with a thickness that is less than or equal to that of the deposited layer of oxide of silicon.
- mechanical stresses derived from the difference in expansion during heat treatments carried out on the structure before or during part of the epitaxy, may be limited so that they do not exceed the plastic deformation (creep) threshold of the oxide of silicon at the temperature under consideration.
- the Applicant has carried out tests which showed that when a film of sapphire with a thickness of 0.5 ⁇ m was transferred onto a 0.3 ⁇ m thick bonding layer of HTO silane oxide of silicon deposited by LPCVD, delamination of the film occurred after a heat treatment carried out at 1100 0 C for 1 hour. In contrast, when a 0.3 ⁇ m thick film of sapphire was transferred onto a bonding layer that was also 0.3 ⁇ m thick of HTO silane oxide of silicon deposited by LPCVD, no delamination occurred after a heat treatment carried out at 1100 0 C for 3 hours.
- the thickness of the thin film should be significantly reduced relative to that of the deposited layer of oxide of silicon when the thin film is formed from lithium tantalate (LiTaOs) that has a thermal expansion coefficient of 16 xl ⁇ ⁇ 6 K "1 at ambient temperature.
- the thickness of the bonding layer of oxide formed by LPCVD deposition is preferably in the range from approximately 0.2 ⁇ m to 0.75 ⁇ m and more preferably in the range from approximately 0.2 ⁇ m to 0.45 ⁇ m.
- the formation and development of microcavities in the bonding layer of oxide formed by deposition result from applying a thermal budget.
- the temperature/period couple corresponds to the thermal budget of a heat treatment .
- the epitaxial growth is carried out at a temperature that is higher than the temperature at which the layer of oxide of silicon is deposited, it is possible, as a function of the temperature of the epitaxial growth, to determine the period after which the oxide layer is sufficiently weakened to be broken, for example during epitaxy or by extending the heat treatment after epitaxy, or by a complementary mechanical or chemical action.
- Fracture may be obtained by developing the microcavities formed by extending the heat treatment for initiating formation of the microcavities.
- fracture may also be obtained by applying a mechanical stress, for example by introducing a blade between the support substrate and the thin film or by applying tensile forces or shear forces to these two elements . It is then possible to obtain fracture more easily, more precisely and in a more localized manner than with a non-weakened bonding layer of oxide, i.e. not comprising microcavities.
- Detachment of the support substrate may also be obtained by means of a chemical attack of the weakened oxide layer, for example using a dilute hydrofluoric acid (HF) solution or BOE (buffered oxide etch, which includes concentrated HF) .
- HF dilute hydrofluoric acid
- BOE buffered oxide etch, which includes concentrated HF
- the heat treatment When epitaxy is carried out at a temperature that is higher than the temperature at which the oxide of silicon is deposited but with a thermal budget that is insufficient to achieve the necessary development of the microcavities and obtain rupture of the bonding layer of oxide, the heat treatment must be extended beyond the epitaxy with a thermal budget which means that formation of the n ⁇ icrocavities in the deposited oxide layer can be continued until rupture occurs.
- This thermal budget is a budget that is complementary to that of the epitaxy, in particular as regards the temperature that must be higher than that of the epitaxy if the rate of development of the microcavities is to be enhanced. The period of the heat treatment thus depends on the temperature used.
- the temperature/period couple which defines the thermal budget to be applied for microcavity formation, has to be modulated as a function of the stress brought about by the difference in thermal expansion of the materials constituting the composite structure and the deposited layer of oxide of silicon during heat treatment and the ratio of the thickness of the thin film to the layer of oxide of silicon.
- a structure of a SapoS (sapphire on sapphire) type that has a thin layer of 0.4 ⁇ m bonded by a layer of oxide of silicon with a thickness of 0.4 ⁇ m deposited at 800 0 C using the LPCVD technique with silane as the precursor gas and densified at 1100 0 C for 2 hours in nitrogen.
- the structure is used to epitaxially grow 100 ⁇ m of GaN, requiring a thermal budget of 1100 0 C for 2 hours.
- the complementary budget to obtain fracture is thus be 1200 0 C for 2 hours. If the temperature is lower, the period must be increased to accomplish the formation and development of microcavities to fracture.
- a composite structure fabricated in accordance with the invention can withstand temperatures greater than that for deposition of the oxide of silicon for the epitaxy of materials such as materials of type Ill/N including GaN and other ternary or quaternary alloys.
- the composite structure of the present invention is particularly suitable for materials with high thermal expansion coefficients (TEC), i.e. a mean of 7 X 10 ⁇ 6 K ⁇ x or more over the temperature range to which the structure is to be subjected, typically 20 0 C to 1200 0 C.
- TEC thermal expansion coefficients
- the structure may comprise a thin film and/or the support substrate formed from sapphire (AI 2 O 3 ) (TEC of 7.5 x ItT 6 IC 1 ), lithium tantalate (LiTaO 3 ) (TEC of 16 x ICT 6 K “1 ) , LiNbO 3 (TEC of 15 X ICT 6 IC 1 ) and Haynes® 230® Alloy (TEC of 11.8 x ItT 6 IC 1 ), which is a commercial alloy primarily composed of Ni, Cr, Mo, W (Haynes® 230® Alloy Is not used for the thin film when the film is intended for use as a seed layer for epitaxy), or MgO.
- sapphire AI 2 O 3
- LiTaO 3 lithium tantalate
- LiNbO 3 TEC of 15 X ICT 6 IC 1
- Haynes® 230® Alloy TEC of 11.8 x ItT 6 IC 1
- the composite structure for epitaxy of the Invention is intended for the epitaxial growth of GaN, AlN, InGaN, AlGaN, AlGaInN, BGaN, and indium nitride (InN) .
- the epitaxially grown layer may also be composed of a stack of these various materials, in particular to constitute the active layers of an LED.
- a method of fabricating a layer of semiconductor material by epitaxy comprising prior production of a composite structure and detachment from the support substrate after epitaxy in accordance with an implementation of the invention is described with reference to Figures IA to IL and 2.
- a composite structure is produced that can allow both the formation by epitaxy of at least one layer of material and the detachment of the support substrate after epitaxy.
- the bonding layer 12 is a layer of oxide of silicon deposited by LPCVD with silane as the precursor gas (HTO silane) at a deposition temperature of 800 0 C, a pressure of 1 torr and for a period allowing the deposition of a layer of oxide approximately 0.4 ⁇ m thick.
- the deposited oxide of silicon is then densified by applying a densification anneal carried out at 1200 0 C for 30 minutes in a nitrogen atmosphere (step S2 ) .
- a layer of oxide of silicon 13 is also formed on a donor substrate 11 of sapphire.
- the layer 13 is a layer of oxide of silicon deposited by LPCVD with silane as the precursor gas (HTO silane) at a deposition temperature of 800 0 C, at a pressure of 1 torr and for a period allowing the deposition of a thickness of oxide of silicon of approximately 0.5 ⁇ m (step S3, Figure IB).
- the deposited oxide of silicon is then densified by application of a densification anneal carried out at 1200 0 C for 30 minutes in a nitrogen atmosphere at atmospheric pressure (step S4) .
- the donor substrate 11 also comprises a layer of defects or weakness 3 that has been obtained, in known manner, by implanting ionic species such as hydrogen ions or co-implanting hydrogen and helium ions, carried out at an implantation dose in the range 1 X 10 x7 atoms/cm 2 [atoms/square centimeter] to 4 X 10 17 atoms/cm 2 and with an implantation energy in the range 30 keV [kilo-electron volt] to 200 keV. Implantation is carried out at a temperature in the range 20 0 C to 400 0 C, preferably in the range 50 0 C to 15O 0 C, for a period of 1 minute to 10 hours.
- ionic species such as hydrogen ions or co-implanting hydrogen and helium ions
- These implantation conditions can create, at a predetermined depth that is less than the cumulative thickness of the oxide layers 12 and 13 , in the donor substrate 11, the layer of defects or weakness 3 defining firstly a thin film 4 in the upper region of the substrate 11 and secondly a portion 5 in the lower region of the substrate corresponding to the remainder of the substrate 11.
- the surface of the bonding layers of oxide 12 and 13 is planarized by chemical mechanical polishing (CMP) to obtain a surface roughness of less than 5 A [Angstrom] rms [root mean square] over a surface area of 5 x 5 ⁇ m to thereby facilitate the subsequent intimate contact step (steps S5 and S6, Figures 1C and ID) .
- CMP chemical mechanical polishing
- the cumulative thickness of layers 12 and 13 is 0.45 ⁇ m ⁇ 0.05 ⁇ m.
- bonding is carried out by bringing the face of the HTO silane layer 12 into intimate contact with the layer of HTO silane 13 of the donor substrate 11, the combined layers 12 and 13 forming a bonding layer of oxide 25 (step S7 , Figure IE) .
- Bonding is carried out by wafer bonding.
- the principle of bonding by wafer bonding is well known per se and is not described in further detail. It should be recalled that bonding by wafer bonding is based on bringing two surfaces into intimate contact, i.e.
- the temperature and duration of the splitting anneal are defined as a function of the implantation conditions and in particular as a function of the implantation dose.
- a bonding stabilization anneal is carried out at 1050 0 C in nitrogen for 1 hour without deformations appearing on the surface of the thin film 4 (step S9) .
- the surface of the film 4 may then be prepared for epitaxy, for example by polishing to obtain a surface roughness of less than 5 A rms over a surface area of 5 x 5 ⁇ m 2 (step SlO, Figure IG).
- a composite structure 14 is obtained comprising the support substrate 10, an oxide bonding layer 25 of HTO silane deposited by LPCVD and a thin film 4 of sapphire that may act as a crystalline seed layer for growth.
- epitaxial growth of a layer of gallium nitride (GaN) 15 is carried out on the thin film 4 (step SIl, Figure IH) .
- Epitaxial growth is carried out at 1050 0 C for 2 to 3 hours in order to obtain a layer of approximately 10 ⁇ m or more of GaN, for example using hydride vapor phase epitaxy, HVPE. No delamination was observed after said epitaxy. Since the GaN epitaxy is carried out at a temperature that is higher than that for deposition of the oxides of silicon, the thermal budget supplied by the epitaxy contributed to the budget necessary for the development of microcavities .
- the epitaxially grown layer 15 may also have a more complex structure, termed the electroluminescent diode layer, which is constituted by several materials such as GaN, InGaN, or AlGaN formed in succession by epitaxy.
- step S12 Figure II
- step S12 Figure II
- step S12 Figure II
- step S12 Figure II
- step S12 Figure II
- step S12 Figure II
- step S12 Figure II
- step S12 Figure II
- step S12 Figure II
- step S12 Figure II
- step S12 Figure II
- step S12 Figure II
- step S12 Figure II
- step S12 Figure II
- step S12 Figure II
- step S12 Figure II
- step Said detachment is achieved here by applying a mechanical stress to finalize detachment of the structure at the cavities formed in the oxide during the epitaxial growth step but that are insufficient to provoke spontaneous separation of the bonding layer of oxide 25 into two portions 25a, 25b (step S13 , Figure IJ) .
- step S14 Figure IK
- the remainder 25b of the bonding layer of oxide is also removed from the support substrate 10 that can then be recycled, for example to form a new composite structure for epitaxy as described above (step S15, Figure IL) .
- Production of the composite structure for epitaxy commences by bringing a support substrate 20 formed from sapphire (AI 2 O 3 ) into intimate contact with a donor substrate 21 formed from sapphire each covered with a layer of oxide of silicon deposited by LPCVD using a silane precursor gas and wherein the surface has a roughness of 5 A rms over a surface area of 5 x 5 ⁇ m 2 (step S20, Figure 3A).
- steps S20, Figure 3A These layers of oxide of silicon are not densified, their combination forming a bonding layer of oxide 30 with a cumulative thickness of approximately 0.5 ⁇ m.
- the donor substrate 21 also comprises a layer of defects or weakness 23 that is obtained by implanting ionic species under conditions that can readily be determined by the skilled person (implantation dose and energy) in order to obtain a thickness of the film 24 of 0.5 ⁇ m.
- Bonding is carried out by wafer bonding.
- the assembly of the two substrates then undergoes a splitting anneal to provoke fracture of the donor substrate 21 at the plane of weakness 23 and transfer proper of the thin film 24 onto the support substrate 20 (step S21, Figure 3B).
- the splitting anneal is carried out using a temperature ramp-up from ambient to approximately 600 0 C.
- the surface of the film 24 is thus prepared to act as a crystalline seed for growth for epitaxy, for example by polishing to obtain a surface roughness of less than 5 A rms over a surface area of 5 x 5 ⁇ m 2 (step S22, Figure 3C) .
- a composite structure 44 is obtained comprising the support substrate 20, a bonding layer of oxide of silicon 30 (LPCVD, silane, 0.5 micrometer thick) and a thin film 24 of sapphire 0.5 ⁇ m thick that could act as a crystalline seed layer for growth.
- LPCVD oxide of silicon 30
- sapphire thin film 24 of sapphire 0.5 ⁇ m thick that could act as a crystalline seed layer for growth.
- GaN gallium nitride
- step S23 100 ⁇ m and rupture of the layer of oxide of silicon 30 (step S23, Figure 3D) .
- the split structure is left in place (the support is not removed from the remainder of the structure) and epitaxy is continued to obtain a layer of GaN 35 of approximately 1 mm (step S24, Figure IE) .
- the remainder 30a of the bonding layer of oxide and the thin film 24 are removed from the surface of the layer of GaN 35 by chemical etching and/or polishing (step S25, Figure 3F) .
- the remainder 30b of the bonding layer of oxide is also removed from the support substrate 20 that could then be recycled, for example to form a new composite structure for epitaxy as described above (step S26, Figure 3G) .
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Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| AT09704183T ATE522930T1 (de) | 2008-01-21 | 2009-01-06 | Herstellungsverfahren von epitaxial gewachsenen schichten auf einer verbundstruktur |
| EP09704183A EP2232546B1 (en) | 2008-01-21 | 2009-01-06 | A method of fabricating epitaxially grown layers on a composite structure |
| CN2009801025906A CN101925995B (zh) | 2008-01-21 | 2009-01-06 | 在复合结构上制造外延生长层的方法 |
| US12/663,696 US8153500B2 (en) | 2008-01-21 | 2009-01-06 | Method of fabricating an epitaxially grown layer on a composite structure |
| JP2010543450A JP5005097B2 (ja) | 2008-01-21 | 2009-01-06 | 複合構造上でエピタキシーによって成長する層の製造方法 |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR0850362 | 2008-01-21 | ||
| FR0850362A FR2926672B1 (fr) | 2008-01-21 | 2008-01-21 | Procede de fabrication de couches de materiau epitaxie |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2009092624A1 true WO2009092624A1 (en) | 2009-07-30 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/EP2009/050086 Ceased WO2009092624A1 (en) | 2008-01-21 | 2009-01-06 | A method of fabricating epitaxially grown layers on a composite structure |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US8153500B2 (enExample) |
| EP (1) | EP2232546B1 (enExample) |
| JP (1) | JP5005097B2 (enExample) |
| KR (1) | KR101568890B1 (enExample) |
| CN (1) | CN101925995B (enExample) |
| AT (1) | ATE522930T1 (enExample) |
| FR (1) | FR2926672B1 (enExample) |
| WO (1) | WO2009092624A1 (enExample) |
Families Citing this family (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2926674B1 (fr) * | 2008-01-21 | 2010-03-26 | Soitec Silicon On Insulator | Procede de fabrication d'une structure composite avec couche d'oxyde de collage stable |
| KR20120052160A (ko) * | 2010-11-15 | 2012-05-23 | 엔지케이 인슐레이터 엘티디 | 복합 기판 및 복합 기판의 제조 방법 |
| FR2968121B1 (fr) * | 2010-11-30 | 2012-12-21 | Soitec Silicon On Insulator | Procede de transfert d'une couche a haute temperature |
| CN102820393A (zh) * | 2011-06-10 | 2012-12-12 | 光达光电设备科技(嘉兴)有限公司 | 复合衬底结构及其制作方法 |
| US8927318B2 (en) * | 2011-06-14 | 2015-01-06 | International Business Machines Corporation | Spalling methods to form multi-junction photovoltaic structure |
| US8633094B2 (en) | 2011-12-01 | 2014-01-21 | Power Integrations, Inc. | GaN high voltage HFET with passivation plus gate dielectric multilayer structure |
| US8940620B2 (en) * | 2011-12-15 | 2015-01-27 | Power Integrations, Inc. | Composite wafer for fabrication of semiconductor devices |
| US8928037B2 (en) | 2013-02-28 | 2015-01-06 | Power Integrations, Inc. | Heterostructure power transistor with AlSiN passivation layer |
| FR3007892B1 (fr) * | 2013-06-27 | 2015-07-31 | Commissariat Energie Atomique | Procede de transfert d'une couche mince avec apport d'energie thermique a une zone fragilisee via une couche inductive |
| JP6454606B2 (ja) * | 2015-06-02 | 2019-01-16 | 信越化学工業株式会社 | 酸化物単結晶薄膜を備えた複合ウェーハの製造方法 |
| FR3048548B1 (fr) * | 2016-03-02 | 2018-03-02 | Soitec | Procede de determination d'une energie convenable d'implantation dans un substrat donneur et procede de fabrication d'une structure de type semi-conducteur sur isolant |
| JP6563360B2 (ja) * | 2016-04-05 | 2019-08-21 | 信越化学工業株式会社 | 酸化物単結晶薄膜を備えた複合ウェーハの製造方法 |
| FR3068508B1 (fr) * | 2017-06-30 | 2019-07-26 | Soitec | Procede de transfert d'une couche mince sur un substrat support presentant des coefficients de dilatation thermique differents |
| JP7034186B2 (ja) * | 2017-07-14 | 2022-03-11 | サンエディソン・セミコンダクター・リミテッド | 絶縁体上半導体構造の製造方法 |
| JP2019151896A (ja) * | 2018-03-05 | 2019-09-12 | 日本特殊陶業株式会社 | SiC部材及びこれからなる基板保持部材並びにこれらの製造方法 |
| FR3079660B1 (fr) * | 2018-03-29 | 2020-04-17 | Soitec | Procede de transfert d'une couche |
| FR3108774B1 (fr) * | 2020-03-27 | 2022-02-18 | Soitec Silicon On Insulator | Procede de fabrication d’une structure composite comprenant une couche mince en sic monocristallin sur un substrat support en sic |
| FR3108775B1 (fr) * | 2020-03-27 | 2022-02-18 | Soitec Silicon On Insulator | Procede de fabrication d’une structure composite comprenant une couche mince en sic monocristallin sur un substrat support en sic |
| FR3111232B1 (fr) * | 2020-06-09 | 2022-05-06 | Soitec Silicon On Insulator | Substrat temporaire demontable compatible avec de tres hautes temperatures et procede de transfert d’une couche utile a partir dudit substrat |
| CN114448372B (zh) * | 2021-12-10 | 2025-12-12 | 上海新硅聚合半导体有限公司 | 一种异质薄膜衬底的制备方法和滤波器 |
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| EP0898307A1 (fr) * | 1997-08-19 | 1999-02-24 | Commissariat A L'energie Atomique | Procédé de traitement pour le collage moléculaire et le décollage de deux structures |
| FR2857983A1 (fr) * | 2003-07-24 | 2005-01-28 | Soitec Silicon On Insulator | Procede de fabrication d'une couche epitaxiee |
| FR2860249A1 (fr) * | 2003-09-30 | 2005-04-01 | Michel Bruel | Procede de fabrication d'une structure en forme de plaque, en particulier en silicium, application de procede, et structure en forme de plaque, en particulier en silicium |
| US20060234486A1 (en) * | 2005-04-13 | 2006-10-19 | Speck James S | Wafer separation technique for the fabrication of free-standing (Al,In,Ga)N wafers |
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| US6326279B1 (en) * | 1999-03-26 | 2001-12-04 | Canon Kabushiki Kaisha | Process for producing semiconductor article |
| JP2000353797A (ja) * | 1999-06-11 | 2000-12-19 | Mitsubishi Electric Corp | 半導体ウエハおよびその製造方法 |
| FR2817395B1 (fr) * | 2000-11-27 | 2003-10-31 | Soitec Silicon On Insulator | Procede de fabrication d'un substrat notamment pour l'optique, l'electronique ou l'optoelectronique et substrat obtenu par ce procede |
| FR2823599B1 (fr) | 2001-04-13 | 2004-12-17 | Commissariat Energie Atomique | Substrat demomtable a tenue mecanique controlee et procede de realisation |
| FR2823596B1 (fr) * | 2001-04-13 | 2004-08-20 | Commissariat Energie Atomique | Substrat ou structure demontable et procede de realisation |
| FR2835095B1 (fr) * | 2002-01-22 | 2005-03-18 | Procede de preparation d'ensembles a semi-conducteurs separables, notamment pour former des substrats pour l'electronique, l'optoelectrique et l'optique | |
| FR2857982B1 (fr) | 2003-07-24 | 2007-05-18 | Soitec Silicon On Insulator | Procede de fabrication d'une couche epitaxiee |
| FR2858461B1 (fr) * | 2003-07-30 | 2005-11-04 | Soitec Silicon On Insulator | Realisation d'une structure comprenant une couche protegeant contre des traitements chimiques |
| FR2865574B1 (fr) | 2004-01-26 | 2006-04-07 | Soitec Silicon On Insulator | Procede de fabrication d'un substrat demontable |
| JP2005005723A (ja) * | 2004-06-25 | 2005-01-06 | Hitachi Cable Ltd | 窒化物半導体エピタキシャルウェハの製造方法及び窒化物半導体エピタキシャルウェハ |
-
2008
- 2008-01-21 FR FR0850362A patent/FR2926672B1/fr active Active
-
2009
- 2009-01-06 US US12/663,696 patent/US8153500B2/en active Active
- 2009-01-06 WO PCT/EP2009/050086 patent/WO2009092624A1/en not_active Ceased
- 2009-01-06 CN CN2009801025906A patent/CN101925995B/zh active Active
- 2009-01-06 EP EP09704183A patent/EP2232546B1/en active Active
- 2009-01-06 JP JP2010543450A patent/JP5005097B2/ja active Active
- 2009-01-06 KR KR1020107015994A patent/KR101568890B1/ko active Active
- 2009-01-06 AT AT09704183T patent/ATE522930T1/de not_active IP Right Cessation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0898307A1 (fr) * | 1997-08-19 | 1999-02-24 | Commissariat A L'energie Atomique | Procédé de traitement pour le collage moléculaire et le décollage de deux structures |
| FR2857983A1 (fr) * | 2003-07-24 | 2005-01-28 | Soitec Silicon On Insulator | Procede de fabrication d'une couche epitaxiee |
| FR2860249A1 (fr) * | 2003-09-30 | 2005-04-01 | Michel Bruel | Procede de fabrication d'une structure en forme de plaque, en particulier en silicium, application de procede, et structure en forme de plaque, en particulier en silicium |
| US20060234486A1 (en) * | 2005-04-13 | 2006-10-19 | Speck James S | Wafer separation technique for the fabrication of free-standing (Al,In,Ga)N wafers |
Also Published As
| Publication number | Publication date |
|---|---|
| KR101568890B1 (ko) | 2015-11-12 |
| KR20100100980A (ko) | 2010-09-15 |
| EP2232546B1 (en) | 2011-08-31 |
| JP5005097B2 (ja) | 2012-08-22 |
| CN101925995A (zh) | 2010-12-22 |
| CN101925995B (zh) | 2013-06-19 |
| US8153500B2 (en) | 2012-04-10 |
| US20100178749A1 (en) | 2010-07-15 |
| JP2011510507A (ja) | 2011-03-31 |
| EP2232546A1 (en) | 2010-09-29 |
| ATE522930T1 (de) | 2011-09-15 |
| FR2926672B1 (fr) | 2010-03-26 |
| FR2926672A1 (fr) | 2009-07-24 |
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