Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
  • H10F71/00—Manufacture or treatment of devices covered by this subclass
  • H10F71/121—The active layers comprising only Group IV materials
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
  • H10F77/00—Constructional details of devices covered by this subclass
  • H10F77/20—Electrodes
  • H10F77/206—Electrodes for devices having potential barriers
  • H10F77/211—Electrodes for devices having potential barriers for photovoltaic cells
  • H10F77/219—Arrangements for electrodes of back-contact photovoltaic cells
  • H10F77/223—Arrangements for electrodes of back-contact photovoltaic cells for metallisation wrap-through [MWT] photovoltaic cells
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
  • H10F77/00—Constructional details of devices covered by this subclass
  • H10F77/20—Electrodes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
  • H10F77/00—Constructional details of devices covered by this subclass
  • H10F77/20—Electrodes
  • H10F77/206—Electrodes for devices having potential barriers
  • H10F77/211—Electrodes for devices having potential barriers for photovoltaic cells
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
  • H10F77/00—Constructional details of devices covered by this subclass
  • H10F77/20—Electrodes
  • H10F77/206—Electrodes for devices having potential barriers
  • H10F77/211—Electrodes for devices having potential barriers for photovoltaic cells
  • H10F77/219—Arrangements for electrodes of back-contact photovoltaic cells
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
  • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
  • Y02E10/00—Energy generation through renewable energy sources
  • Y02E10/50—Photovoltaic [PV] energy
  • Y02E10/547—Monocrystalline silicon PV cells
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
  • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
  • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
  • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

• the present invention is related to photovoltaic devices such as solar cells.
• One of these categories is the group of the so called back-contacted solar cells, meaning that both ohmic contacts to the two oppositely doped regions of the solar cells are placed on the back or non-illuminated surface of the solar cell. This concept avoids or reduces shadowing losses caused by the front metal contact grid on standard solar cells.
• back contact solar cells The most straightforward way to fabricate back contact solar cells is to place the carrier collecting junction between semiconductor regions of opposite doping close to the back surface of the cell ("back-junction" cell).
• back-junction cell
• the document "1 127.5- Percent Silicon Concentrator Solar Cells” (R.A. Sinton, Y. Kwark, J.Y. Gan, R. M. Swanson, IEEE Electron Device Letters, Vol. ED-7. No. 10, October 1986) describes such a device.
• Another group of solar cells combines the two approaches. Such solar cells have both external contacts to the oppositely doped regions on the back surface and the collecting junction close to the front surface. The collected current from the front surface is lead through openings, which extend through the entire wafer, to the back surface. Using this structure, shading losses normally arising from the front metallization grid are greatly reduced.
• MWT solar cells are still generally efficiency limited due to excessive shunt like recombination happening in the via and under the rear emitter bus bars (as disclosed e.g. in documents: "Processing and comprehensive characterisation of screen-printed MC-Si Metal Wrap Through (MWT) Solar cells", Clement et al.., Proceedings of the 22 nd European Photovoltaic Solar Energy Conference, Milan, Italy (2007), p1400- 1402; "Lifetime studies on laser drilled vias for application in Emitter-Wrap- Through-Solar Cells", Mingirulli et al., Proceedings of the 22 nd European Photovoltaic Solar Energy Conference, Milan, Italy (2007), p1415-1418).
• a photovoltaic device as for instance a solar cell, the photovoltaic device having a semiconductor layer having a front surface for receiving impinging light, e.g. sunlight, and a rear surface opposite to the front surface, a front contact, also called emitter contact, for collecting current on the front surface, a rear bus bar, also called emitter busbar, on the rear of the device, e.g. on a rear surface for extracting front side current, a via through the semiconductor layer, the via having a conductive path for coupling the front contact to the rear bus bar, a dielectric layer on a rear surface of the substrate i.e.
• the dielectric in the via helps reduce the need to have a junction region near the via and on the back surface, so there is less damage from drilling the via present in or next to the junction region. This helps reduce unwanted recombination currents, thus improving efficiency.
• the dielectric can serve multiple purposes, such as surface and bulk passivation, protection against thermal damage caused by firing, back surface reflecting to improve efficiency, and insulating the metal from the semiconductor in the via.
• Another aspect of the invention provides a method of manufacturing a photovoltaic device having a semiconductor layer having a front surface for receiving impinging light, e.g. sunlight, and a rear surface opposite to the front surface, the method having the steps of forming a via through the semiconductor layer, forming a dielectric layer on a rear surface of the substrate, i.e.
• Fig.1. shows an example of stages in a photovoltaic device, as e.g. a solar cell, fabrication process according to an embodiment of the present invention.
• Fig.2. shows an Illustration of stages in other fabrication processes according to other embodiments of the present invention.
• Fig 3 shows a cross section view of a photovoltaic device according to an embodiment of the invention.
• Fig 4 shows a similar cross section view according to another embodiment.
• Fig 5 shows a cross section view of a photovoltaic device according to another embodiment of the invention.
• Fig 6 shows steps in a method of manufacturing according to another embodiment.
• the embodiments described show a new and improved structure which has some of the features of the known MWT structure mentioned above, and of the so called /-perc structure described in the document WO 2006/097303 A1.
• the new structure (called /-perc-BC) benefits from the stable passivating stack of the /-perc deposited not only on the rear side but also in the via.
• An important difference of at least some embodiments compared to the known MWT structure is the absence of diffusion in via and on the rear side. A consequence of this is the reduction or avoidance of defects generated during the via formation being present in the emitter and/or in the depletion region. Such defects cause recombinations which reduces performance.
• the stack will also serve as a barrier between the metal paste electrically connected to the emitter and covering via and a portion of the rear surface and the underneath bare base region.
• the stack extends over the whole base region and is only locally opened for contact formation which provides excellent passivation of the surface on the base side.
• the stack provides passivation in the regions covered by base electrode and also in base like regions located in between the emitter and base electrode on the rear side.
• the new structure presents also an advantage compared to the initial MWT structure to be found in a simplification of the solar processing due to absence of need for junction isolation both on the rear and on the front side as a consequence of the absence of emitter regions on the rear side.
• Figure 3 shows a device according to an embodiment of the present invention. It shows a semiconductor layer in the form of P-type Silicon 29 with a via in the form of a hole 25 through the wafer.
• the front side has a diffused region 20, covered by a passivation layer 27 of SiNx, with contacts 23, also called emitter contacts, extending through this passivation layer. Not shown are how the contacts would be coupled together to the conductive path in the via to pass the front side current to the bus bars, also called emitter bus bars, at the rear side.
• an i-perc type structure is shown, in the form of a dielectric stack formed by an oxide layer 39, covered by a SiNx layer 28. This can be implemented using the examples shown in WO2006 097303.
• Back contacts also called rear contacts or base contacts
• AI-BSF 36 are shown reached by Al (31 ) extending through holes in the dielectric stack to couple the base contacts together.
• the dielectric stack extends into the via.
• the deposited oxide extends all the way through the via, and the SiNx extends at least part way through.
• the conductive path in the via is printed directly on the oxide or the SiNx, partly from the front side and partly from the rear side. It can also be printed in one step, either from the rear side or from the front side, using specific vacuum conditions to suck the paste in the via if needed.
• this embodiment of a photovoltaic device has a semiconductor substrate, having at least a radiation receiving front surface and a rear surface, said substrate comprising a first region of one conductivity type (29), (can be a base region) and a second region with the opposite conductivity type (20) (can be an emitter region) adjacent to the front surface, and covered by an antireflection layer (27).
• the rear surface is covered by a dielectric layer(39) such as a deposited oxide layer or dielectric stack comprising oxide layer and silicon nitride layer (28 ), said dielectric layer or dielectric stack covering also an inside surface of the via.
• the front surface has current collecting conductive contacts (23) to the said second region(20) and a conductive layer extending into the via (25), the rear surface having current collecting conductive contacts (31 ) extending through the said dielectric to the said first region(29) and a rear conductive termination electrode (bus bar) (33).
• Fig 4 shows another embodiment in which corresponding reference numerals are used to those of figure 3.
• the SiNx extends in the via all the way through the wafer to the front surface. In some cases it can be deposited all the way through and yet in later manufacturing steps the SiNx can be removed locally in the via near the front surface, to leave an SiNx layer as shown in Fig 3. This local removal can for example take place by the application of the front metal pastes and the subsequent firing step.
• the Example shown in Fig 4 also shows the rear busbar in the form of the screen printed Ag 33 being printed before the front grid is printed (in the form of Ag screen printed contacts 23).
• Figure 5 shows a similar embodiment, with similar reference numerals, but with the SiNx layer on the rear side not extending into the via.
• Figure 6 shows method steps according to an embodiment.
• via's are cut through the wafer by means of laser or any other silicon machining or etching method.
• an N+ diffusion layer is created on the front side of the P-type Si.
• the SiNx and other front side layers if any, are then formed. In principle this step could be carried out before the vias are cut. Either way it is preferable to avoid creating the diffusion layer near the vias so that it does not extend deeper adjacent the vias.
• the dielectric layer is formed all over the back surface without aligning or patterning, so it will extend into the vias.
• the dielectric stack is locally opened.
• emitter metallization is formed.
• the emitter busbars are formed on the rear to connect multiple vias together and to collect all the front side current, as shown as step 68.
• the emitter contact grid is formed on the front. They are connected to each other through the via.
• the emitter electrode extending into the via, and over the dielectric layer is isolated from the base of the semiconductor by the dielectric layer. Forming such conductive paths in the vias can be implemented in various different ways as would be known to those skilled in the art.
• metal is deposited to fill the back-contact holes through the dielectric layer to reach the semiconductor. These accesses to the base of the semiconductor are connected together.
• the device is fired, to do thermal processing of the back and front contacts. Additional features:
• the embodiments described show a semiconductor layer in the form of a silicon substrate, but the invention is not limited thereto. Other suitable substrates can be used as well.
• the dielectric layer can be implemented by a wide bandgap semiconductor layer acting as a dielectric. There can be many vias closely spaced in a regular pattern so as to minimise losses and minimise the amount of shading by the metal on the front side. A typical spacing might be 2mm, though other values can be used.
• the front side contacts can be arranged in star patterns radiating away from each via, or other patterns can be used following known practice.
• the semiconductor layer can have a diffusion region, formed by diffusion from the front surface and formed so that the diffusion region does not extend deeper into the semiconductor layer in the vicinity of the via.
• a passivation layer comprising hydrogenated SiN can be provided in the dielectric stack on top of said dielectric layer. The passivation layer can extend into the via.
• the busbar of the emitter contact formed on the rear side can be formed after the firing of the front grid and of the rear contact, using for instance a low- temperature paste.
• the emitter busbar can be printed before the front grid so that the material of the busbar is in direct contact with the dielectric isolating layer. This material provides an additional protection against penetration of the paste used for the front grid, which can be more aggressive because it needs to penetrate during firing through the SiNx deposited as ARC layer on the front.
• SiN:H layer can have a thickness larger than 100 nm, preferably larger than 120 nm, still more preferred larger than 150 nm, larger than 180 nm or larger than
• both the front main surface and the rear surface are adapted to receive impinging light.
• the front main surface is that surface adapted for receiving the largest fraction of the impinging light.
• the layer of hydrogenated SiN functions as a passivating layer in that it releases hydrogen (during a subsequent high-temperature step) and induces the charges that allow for a good surface passivation of the dielectric/substrate interface.
• the dielectric layer on the rear surface may comprise depositing a low quality oxide.
• the low quality oxide may comprise low quality amorphous oxide, e.g. amorphous silicon oxide, which can reduce production costs when compared to production of high quality oxide.
• the low-quality amorphous oxide may be any of APCVD pyrolithic oxide, spin-on oxide, spray-on oxide or dip oxide.
• the dielectric layer may be a deposited dielectric layer. Deposited dielectric layers are typically of lower quality than grown dielectric layers.
• a low-quality dielectric layer e.g. amorphous oxide
• the deposition temperature may be lower than 600 0 C, hereby allowing processing without thermal poisoning of substrates.
• the dielectric may be deposited e.g. by PECVD at a temperature below 500 0 C.
• the deposition temperature may be lower than 410°C, which can be achieved by using for instance pyrox (having a typical deposition temperature of 404 0 C).
• the dielectric or wide bandgap semiconductor layer may be deposited by low temperature PEVCD ( ⁇ 300 0 C).
• the deposition may be done at Room Temperature e.g. by spin-on, spray-on, dip or any other deposition from liquid, sol, solgel.
• the resulting dielectric layer or wide bandgap semiconductor layer may need further curing at higher temperatures, which can happen during further cell processing.
• any kind of silicon substrate may be used.
• silicon substrates are Czochralski Si (cz-Si) wafers, Float-Zone Si (fz-Si) wafers, multicrystalline Si (mc-Si) wafers and Ribbon Si wafers.
• layers are polycrystalline silicon layers which can be put on glass or glass-ceramic, or monocrystalline Si layers obtained by a lift-off process
• the thickness of the dielectric layer or wide bandgap semiconductor layer or sub-stack of dielectric layers and/or wide bandgap semiconductor layers may be between 100 nm and 5000 nm, preferably between 100 nm and 4000 nm, more preferred between 100 nm and 3000 nm, still more preferred between 100 nm and 2000 nm, still more preferred between 100 nm and 1500 nm, still more preferred between 150 nm and 1200 nm, more preferably between 200 nm and 1200 nm, still more preferably between 600 nm and 1200 nm or between 800 nm and 1200 nm.
• the thickness of the dielectric layer or wide bandgap semiconductor layer or dielectric layer stack may be between 400 nm and 800 nm.
• the minimal thickness of the dielectric layer or wide bandgap semiconductor layer or dielectric layer stack depends on the material which is employed and is determined by the amount of material which is necessary to act simultaneously as a diffusion mask during emitter diffusion, while still being of use for surface passivation and contact formation. For pyrox Silicon Oxide this is typically about 300 nm, for AI 2 O 3 /TiO 2 pseudobinary alloys (PBAs) deposited by solgel this is about 150 nm. Those thickness values are only indicative and a deviation of 10%, 20% or more from the given values is possible.
• a combination, or a stack of layers, of different materials are possible and would lead to a pre-determined threshold thickness for the combined diffusion mask, surface passivation and contact formation process. It is one of the functions of the dielectric layers or wide bandgap semiconductor layers applied at the rear surface of a photovoltaic device, for instance a solar cell, in accordance with the present invention, to increase the distance between the back contact material and the substrate surface. It has been found, surprisingly, that, for a distance between 100 nm and 5000 nm, the larger the distance between the contacting layer at the rear surface of the photovoltaic device, for instance solar cell, and the rear surface of the substrate, the better the achieved passivation results, even with low quality dielectric materials or wide bandgap semiconductor layers being applied.
• forming back contacts may comprise forming holes in said dielectric layer or wide bandgap semiconductor layer and said passivation layer or in said dielectric layer stack possibly provided with a passivation layer, and depositing a layer of contacting material onto said passivation layer or onto said dielectric layer stack, hereby filing said holes.
• Forming holes may be performed by applying an etching paste, by mechanical scribing or by laser ablation for example.
• depositing a layer of contacting material may be performed by evaporation, sputtering or screen printing, inkjet printing, stencil printing.
• Metals can be used as contacting materials, although advantageously Aluminum can be used. Some embodiments involve using Aluminum paste, allowing the formation of local BSF (Back Surface Field) contacts.
• a metal instead of a metal, a p+ (or n+ on n-type substrates) semiconductor (like a-Si) by e.g. PECVD and then deposit a metal on top of it.
• the layer of contacting material may be discontinuous. During the step of depositing the layer of contacting material, said contacting material may be deposited essentially in said holes. Different ways of depositing such a discontinuous layer of contact material exist, and are known by a person of ordinary skill.
• the layer of contacting material may be initially discontinuous. This means that different areas can be covered with contacting material, whereby those different areas are not electrically connected to each other. These areas can be electrically connected later on in order to allow an optimal current flow through the device and/or an external load.
• the layer of contacting material may be deposited in such way that light can also enter the device from the rear side, thereby allowing the production of bifacial solar cells.
• a high temperature step may be applied to the layer of contacting material, i.e. a step at a temperature between 600 and 1000 degrees Celsius, such as for example firing of the front and rear contacts in a rapid thermal process (tens of seconds).
• a temperature between 600 and 1000 degrees Celsius such as for example firing of the front and rear contacts in a rapid thermal process (tens of seconds).
• the method according to the present invention be used with the high temperature step, but the dielectric layer or wide bandgap semiconductor layer or dielectric layer stack can be resistant to such a high temperature step, which is typical in all industrial solar cells.
• the surface passivation of the dielectric/silicon interface can be improved.
• This high temperature step may e.g.
• the firing step can be "co-firing" when the front and rear side contact are created at the same time.
• the rear side can be fired above 800 degrees Celsius, and subsequently the front contact can be fired around 750 degrees Celsius (and possibly followed by a forming gas anneal -FGA-)
• the numbers in the last paragraph are indicative and certain variations are possible (e.g. of about 25%).
• forming back contacts may be performed by applying a continuous layer of contacting material, e.g. metal, and applying local firing of the layer of contacting material, i.e. local heating e.g. by means of a laser.
• the continuous layer of contacting material can also serve as a back mirror.
• forming back contacts may be performed by applying a patterned metal layer at the passivated rear surface of the photovoltaic device, for instance solar cell, and applying a general heating step.
• Some embodiments of methods may further comprise a step of diffusion and emitter removal on the surface to be passivated (i.e. rear surface) before depositing said dielectric layer or wide bandgap semiconductor layer or said dielectric layer stack.
• a step of diffusion and emitter removal on the surface to be passivated i.e. rear surface
• these layers may be applied before the formation of the emitter takes place. In this case, no dopants will enter into the substrate at the rear surface of the device, and thus it is advantageous that according to some embodiments of the present invention emitter removal on the surface to be passivated may be avoided.
• a step of diffusion may be applied after the step of depositing a dielectric layer or wide bandgap semiconductor layer and before the step of depositing a passivation layer.
• the dielectric layer or wide bandgap semiconductor layer may be used as a diffusion mask.
• the dielectric layer or wide bandgap semiconductor layer can be used simultaneously as a diffusion mask and for the purpose of surface passivation, thereby simplifying the cell process sequence.
• the dielectric layer or a wide bandgap semiconductor layer can be used as a diffusion mask, whether it is patterned or not. Normally it will not be patterned, and it is just a mask on the full rear surface. It may, however, be patterned e.g. for interdigitated or back contacted solar cells.
• the dielectric layer or wide bandgap semiconductor layer may be locally removed, ablated, etched or patterned in order to create openings for local contacts to the substrate surface.
• a further step can be comprised of diffusion with another mask to be etched off, or maskless diffusion with subsequent rear side parasitic emitter removal before depositing the dielectric layer or wide bandgap semiconductor layer.
• said front surface may have undergone a typical solar cell front surface processing.
• a typical solar cell front surface process may comprise texturing of the front surface, diffusion of phosphorus atoms at the front side, etching of the phosphorus glass and the deposition of a silicon nitride layer on the front side.
• the method steps as recited hereinabove for the rear surface may also be applied to the front main surface of the solar cell.
• the substrate e.g. silicon substrate
• the substrate may be an ultra-thin substrate, which is typically thinner than 250 micron, preferably thinner than 200 micron, or more preferably thinner than 150 micron. Reducing the thickness of the substrate allows a more efficient use of prime material, hence a lower cost.
• ultra-thin substrates may bow under or after certain treatments. Some embodiments of the present invention can improve the resistance against bowing of such ultra-thin substrates, therefore reducing at least some of the difficulties of the use of ultra-thin substrates for photovoltaic device, for instance solar cell, fabrication.
• a thick SiN layer is deposited on a rear surface of a silicon substrate.
• the SiN layer has a thickness larger than 100 nm, preferably a thickness of at least 180 nm.
• a thickness of at least 180 nm When formed into a solar cell, such structure shows increased cell efficiencies for higher dielectric thicknesses. Furthermore, the cell efficiencies for dielectric layers thicker than 100 nm have been found to be better than prior art cell efficiencies with lower dielectric thicknesses.
• Figs 1 , 2 Fig.1 shows stages in a manufacturing process according to an embodiment, without showing the via.
• dielectric 1 e.g. oxide
• substrate surface 4 e.g. silicon surface.
• SiNx:H 3 optimized for hydrogen release is deposited on top of the dielectric 1 .
• the substrate surface passivation is improved by means of hydrogenation.
• the dielectric layer stack 1 , 3 thus formed is then opened up by forming holes 6 in the stack, to form local contact areas.
• a layer of contacting material 5 is applied onto said dielectric layer stack 1 , 3, hereby filling the holes. This may be done by screen printing, for example by simultaneously or consecutively front and rear side screen printing.
• a high temperature step such as co-firing is then applied in order to make contact with the substrate 2.
• the contacting material 5 may be applied as a continuous layer, or as a discontinuous layer as in Fig. 2. This means that different areas can be covered with contacting material 5, whereby those different areas are not electrically connected to each other. These areas can be electrically connected later on by electrical connection means 8 in order to allow an optimal current flow through the device and/or an external load.
• a rear side passivation layer has thus been developed that (a) retains or improves its surface passivation qualities during the firing step, that (b) cannot be fired through by commercial Aluminum screen printed paste, while there exists a least-damage, fast technique to locally remove such layer prior to metallisation, and that (c) does not interact with the capping metal layer during the firing process or when local contacts are otherwise formed through it. Due to its characteristics this process
• the process eliminates the bowing problems when using ultra-thin wafers or substrates (e.g. problems when combined with Al screen printed paste on ultra- thin wafers).
• a generic low quality amorphous oxide was deposited (e.g. SiO 2 , SiOx, SOG, TiO 2 , AI 2 O 3 ... or their pseudo-alloys, SiONx,) on the solar cell's rear side silicon surface (e.g. by APCVD, or spin coating).
• the surface passivation properties of the dielectric layer were improved by depositing an optimized hydrogenated dielectric layer (namely: SiNx:H).
• SiNx:H optimized hydrogenated dielectric layer
• this invention enables for an easy way to create Local Back Surface Field (LBSF) contacts by selective alloying, during the firing process itself.
• the alloying process partially recovers any surface damage that may have incurred during the opening of the layer, thereby further simplifying the process.
• part of the Si surface and subsurface forms an alloy with the metal.
• the surface termination is therefore not crucial, as it would be e.g. when depositing another semiconductor, or a dielectric. A back surface field is formed and the effect of residual subsurface damage will be reduced, to a certain extent.
• silicon oxide 1 was deposited by atmospheric pressure chemical vapor deposition (APCVD) onto a silicon substrate 2.
• APCVD oxide has poor passivation properties and finds its application in microelectronics as an inexpensive and convenient diffusion mask, or dopant source. In fact, it can be deposited at about 400 0 C, which means that even low quality silicon material can withstand the deposition process without risk of thermal poisoning.
• Thermal annealing can, to some extent, improve the surface passivation quality of APCVD oxide.
• prolonged treatments lead to a degradation of the sample.
• Hydrogenated silicon nitride (SiNx:H) 3 can be used to stably improve the quality of the oxide/silicon interface 4. It is known that silicon nitride can lead to excellent surface and bulk passivation properties on silicon, reason for which it is widely used in solar cell technology. However, its application for rear side passivation of an industrial solar cell is not straightforward. There exists an interaction between silicon nitride and metal capping layer (i.e. the rear surface contact of the solar cell), that leads to decreased surface passivation and cell efficiency (it is believed that this interaction is more than a "shunt" effect as described e.g.
• the silicon nitride is used as a hydrogen source for the low quality oxide underneath, thereby significantly improving its surface passivation properties.
• the oxide layer in one experiment was 800 nm thick, excluding any field-induced passivation effect from the overlying silicon nitride, which is in the prior art believed to be the reason for the good passivation quality.
• a further advantage of the technique is that since it can be applied to low quality oxides, it can be applied directly on diffusion mask oxides too, greatly simplifying the solar cell process.
• Dielectric layer stacks with a dielectric layer with thickness between 100 nm and 1500 nm have been deposited.
• the open circuit voltage has been measured as a function of the low quality dielectric thickness.
• Dielectric thicknesses between 100 nm and 800 nm provide improved open circuit voltages with respect to the open circuit voltage of a cell obtained by a standard prior art process of full coverage aluminium BSF.
• stacks than the above-mentioned silicon (substrate)/low quality oxide (dielectric layer)/silicon nitride (passivation layer) stack can for example be
• silicon (substrate)/dielectric or wide bandgap (>2eV, preferably >3eV) semiconductor such as e.g. silicon carbide (SiC), aluminum nitride (AIN), gallium nitride (GaN) or boron nitride (BN) /silicon nitride
• SiC silicon carbide
• AIN aluminum nitride
• GaN gallium nitride
• BN boron nitride
• the dielectric layer stack has a thickness above 100 nm.
• a typical process sequence for surface passivation including inside the vias can comprise the steps of
• This method for surface passivation can be integrated in the process sequence of a solar cell, in different situations: A) deposition after diffusion
• doped e.g. n-type doped regions all around the substrate, i.e. both at the front surface and the rear surface
• base contacts ⁇ e.g. by Metal deposition for local contacts on back surface (e.g. by evaporation, sputtering, screen printing)).
• back surface e.g. by evaporation, sputtering, screen printing
• -Silicon nitride deposition (rear and possibly front side) -Opening of the local contacts (e.g. by etching paste, scribing or laser ablation) -Forming the rear-contact bus bar (terminal electrode of the front contact grid connected to the front contact grid through the vias). -Forming the front contact grid. - Forming of base contacts (e.g. by Metal deposition for local contacts on back surface (e.g. by evaporation, sputtering, screen printing)). -Firing in a commercial belt furnace
• the AI-BSF layer and Al electrode is replaced by i-PERC dielectric stack and local back contact, - a passivating stack is deposited over the whole rear and inside the vias, and there is no n+ diffusion layer in the vias
• MWT cell Another problem with the known MWT cell arises from metallization in the vias and on the rear side being printed directly on the "non-covered" n+ layer, rather than on top of the silicon nitride antireflection coating layer as happens on the front side. It is very difficult to find the right contact firing process so that the front metallization has low contact resistance and the metallization in the vias does not create shunts. If the firing temperature is too high, metal spiking creates significant shunts. This again reduces performance.
• the n+layer on the rear is in direct contact with the AI-BSF layer which results in shunting.
• Laser junction isolation is applied to separate n+ and p+ regions. Any imperfection in this step of junction isolation contributes to shunts.
• there is no n+ layer on the rear surface and both polarity electrodes are printed on dielectric so there is no need for any additional isolation.
• the constraints of alignment of the two polarity contacts are also relaxed since the metal printing by itself defines the contact isolation, and not an additional laser step, which has to be aligned to the gap between the 2 contacts in the MWT structure.
• a possible difficulty or source of weakness occurs where the front-contact metal paste is very close to the base region of the substrate and separated from it by the oxide layer deposited in the vias (particularly at the intersection of the via and the front surface).
• the dielectric being a lot thinner than on the rear surface.
• the front side Ag paste did get through the SiNx layer during firing, and thus damage the Si. So there were grounds for predicting that it might get through the SiNx layer + a rather thin (but thickness extremely difficult to quantify) oxide layer at the front side edge of the via.
• the iPERC stack optimized for base passivation proved to provide an unexpectedly efficient protection layer against the penetration of the Ag paste.
• the new structure also proves to be better in terms of avoiding a loss in fill factor (FF) which occurs when the diffusion extends along the vias. Also, it is notable that the thick dielectric needed to protect the busbar region if you do not diffuse the vias, can also be used as the thick dielectric needed for the i-PERC process for the back side.
• FF loss in fill factor

Landscapes

• Photovoltaic Devices (AREA)
• Life Sciences & Earth Sciences (AREA)
• Engineering & Computer Science (AREA)
• Sustainable Development (AREA)
• Sustainable Energy (AREA)

Priority Applications (6)

Applications Claiming Priority (4)

Related Child Applications (1)

Publications (2)

Family

ID=39683568

Family Applications (1)

Country Status (7)

Cited By (17)

Families Citing this family (71)

Citations (6)

Family Cites Families (10)

• 2007
  • 2007-12-03 EP EP07122152A patent/EP2068369A1/en not_active Withdrawn
• 2008
  • 2008-12-02 JP JP2010536432A patent/JP5416711B2/ja not_active Expired - Fee Related
  • 2008-12-02 ES ES08856838.1T patent/ES2365679T5/es active Active
  • 2008-12-02 CN CN2008801192393A patent/CN101889349A/zh active Pending
  • 2008-12-02 AT AT08856838T patent/ATE511215T1/de not_active IP Right Cessation
  • 2008-12-02 WO PCT/EP2008/066662 patent/WO2009071561A2/en not_active Ceased
  • 2008-12-02 EP EP08856838.1A patent/EP2215663B2/en active Active
• 2010
  • 2010-06-02 US US12/792,624 patent/US9246044B2/en active Active

Patent Citations (7)

Non-Patent Citations (2)

Also Published As

Similar Documents

Legal Events