NL2006160C2

NL2006160C2 - A method of manufacturing a solar cell and a solar cell.

Info

Publication number: NL2006160C2
Application number: NL2006160A
Authority: NL
Inventors: Johannes Reinder Marc Luchies; Klaas Heres
Original assignee: Tsc Solar B V
Priority date: 2011-02-08
Filing date: 2011-02-08
Publication date: 2012-08-09

Description

A method of manufacturing a solar cell and a solar cell

FIELD OF THE INVENTION

5 The invention relates to a method of manufacturing a solar cell comprising a semiconductor substrate with a first and a second side, back contacts at the second side and emitter regions defined at the first side, conductors extending from the first side to the second side.

10 The invention further relates to such a solar cell and a solar panel comprising such solar cell.

BACKGROUND OF THE INVENTION

Solar cells are large area semiconductor devices which 15 convert radiation (i.e. sunlight) into electricity. One important class of solar cells is the group of back-contacted solar cells, meaning that both ohmic contacts to the two oppositely doped regions of the solar cells are placed on the second, i.e. back surface of the solar cell.

20 This class of solar cells reduces shadowing losses caused by the front metal contact grid on standard solar cells. Suitably, an emitter is provided on the front or first side (the terms side and surface are hereinafter used exchangably) of the semiconductor substrate (hereinafter 25 also referred to as substrate). Therewith it is achieved that the junction between the oppositely charged regions in the substrate is close to the front surface which receives the incoming radiation. Typically, the emitter extends along the conductors through the substrate to its second side.

30 An example of such a solar cell is known from US3.903.428. This patent proposes the vias for the conductors. Patent EP0985233 is another example. After creating the via, phosphorous or any other dopant is 2 introduced in both surfaces of the substrate including the walls of the vias in order toe create a homogeneous and continuous emitter on both surfaces of the substrate. This results in a double carrier collecting junction, since the 5 junction is not only present near the front surface, but also near the back surface, and hence is double. The patent gives the example wherein the substrate is p-type doped and the emitter is n-type doped. Possible techniques to form an n-emitter include the screen printing of a phosphorous 10 containing paste on the areas of the cell where an emitter is to be created; the use of a gaseous source such as POCI3; spin-on and spray-on deposition techniques. Techniques such as ion implantation would be possible but not at an industrial level as yet; the solar cell is a large scale and 15 relatively cheap product per m2 surface area, when compared to other silicon based products such as integrated circuits.

J. Szlufcik et al., Opto-Electr. Rev., 8 (2000), 299-305 have worked on an alternative for the homogeneous emitter. This is called a selective emitter. Herein, the 20 emitter is partially present below the metallic conductor, particularly a grid of conductors, and partially below a surface passivation. The emitter region below the surface passivation is shallow and lowly doped, while the selective emitter beneath the metal conductor is highly doped and 25 extends more deeply into the substrate. Due to its high doping level, the selective emitter gives rise to lowly resistive contacts with the metal. The shallow extension and low doping of the emitter region, also diffusion region beneath an effective surface passivation reduces the emitter 30 dark saturation current. Szlufcik et al. propose the use of screen printing of phosphorous paste on the locations where the selective emitter is to be formed. These locations are for instance defined in the form of a finger pattern.

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Thereafter, a diffusion step occurs. The areas where the doping is directly deposited are deeply diffused whereas the areas in between the "fingers"are shallowly diffused due to gas phase transportation of doping at the surface. The 5 subsequent surface passivation is suitably applied by phase enhanced Chemical Vapour Deposition (PECVD) and is for instance a SiNx-layer. This silicon nitride layer also forms the antireflection coating (ARC) typically present on the front surface (i.e. first side) of the semiconductor 10 substrate. Alternatively, use can be made of a diffusion barrier. The doping, typically indicated as phosphorous doping, is then typically provided from the gas phase as POCI3 and thereafter diffused through the diffusion barrier so as to create a lowly doped shallow diffusion region. Such 15 a diffusion barrier could also be screen printed on the surface. It is then typically a paste with S1O2 as active component.

Recently, it has been observed that the use of n-type doped semiconductor substrates may lead to higher 20 efficiencies. This requires certain modifications; for a p-type diffusion, typically boron is used, whereas phosphorous is used for the n-type diffusion. Boron diffusion however requires a higher temperature than phosphorous-diffusion. When diffusing the phosphorous, with Boron being present at 25 the same side, then care has to be taken that the phosphorous does not diffuse into the p-type region with boron dopant. One manner of controlling is to apply a laser scribing process subsequently so as to achieve a proper isolation. An alternative manner of controlling, as known 30 from W02009/064183, is the application of a pre-diffusion step for the diffusion of phosphorous. It turns out possible in this manner, to apply the phosphorous doping step before the boron doping step. In order to achieve this, the first 4 side is blocked against doping upon provision of the doping on the second side and the second side is blocked against doping while doping the first side.

However, a problem with using boron as the p-type 5 dopant is the risk for creation of boron-rich layers at the substrate surface. Boron diffusion is for instance applied as BBr3 in an oxygen atmosphere. This converts the BBr3 to liquid boron oxide (B2O3) and gaseous brome (Br2) · The liquid boron oxide condenses on the silicon wafer surface. Chemical 10 reaction with the silicon surface produces silicon oxide (SiCt) and elemental boron. The S1O2 is partly dissolved in the liquid B203, resulting in a mixed-phase B2O3-S1O2 system, also known as boron silicate glass (BSG). Mainly during the heat treatment, the elemental boron diffuses according to 15 the boron gradient into the silicon wafer as well as into the BSG system. During this process a very high concentration of boron ("boron pile up") can occur at the surface of the wafer that transforms a surface layer of the silicon wafer into a SiB compound, forming a boron rich 20 layer (BRL). The Si-B compound is particularly hexaborylsilicon (SiBe) . This boron rich layer is however commonly associated with degradation of the carrier lifetime in the bulk of the wafer.

The method known from WO2009/064183 does not address 25 the problem how to achieve an emitter which does not result in the creation of a boron rich layer.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to 30 provide a process for manufacturing a solar cell wherein a selective emitter can be combined with conductors extending through the semiconductor substrate.

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It is a further object to provide a solar cell having both a selective emitter and conductors extending through the substrate in combination with back contacts. Most suitably the semiconductor substrate has n-type 5 conductivity.

This object is achieved in a method of manufacturing a solar cell comprising the steps of: providing a semiconductor substrate having an opposed first and second side and comprising n-type charge carriers 10 of a first conductivity type; applying a diffusion resistance layer of electrically insulating material onto the first side; patterning said diffusion resistance layer in accordance with a predefined pattern of selective emitter 15 regions to be applied into the semiconductor substrate; providing dopant species into the semiconductor substrate to form the selective emitter regions comprising p-type charge carriers; creating selective dopant diffusion regions through 20 controlled diffusion of further dopant species through the diffusion resistance layer, the selective emitter regions and the diffusion regions jointly operating as emitter.

According to the invention, selective emitter regions are combined with dopant diffusion regions. By limiting the 25 diffusion across the diffusion resistance layer, particularly to a diffusion rate at most equal to the diffusion in the semiconductor substrate, the creation of boron rich layers will be reduced to limited areas, i.e. the selective emitter regions. Additionally, the provision of 30 highly doped, selective emitter regions leads to a reduction in contact resistance with any conductor to be applied thereon. The issue of boron-rich layers may furthermore be solved either by the application of the conductor, i.e.

6 typically as a metal paste or by conversion of the boron rich layer into an oxide, for instance with a low-temperature oxidation step.

In an important embodiment, through-holes are provided 5 in the substrate, and the diffusion resistance layer extending on the walls of the through-holes. Particularly, the diffusion resistance layer furthermore acts as a diffusion barrier against metal diffusion. The metal in the through-hole forms part of the conductor (or via) provided 10 through the substrate in one suitable embodiment with terminals at the second or rear side - e.g. a back-contacted solar cell.

Preferably, the thickness of the diffusion resistance layer is 1 to 30 nm, more preferably in the range of 2 to 20 15 nm, most preferably in the range of 3 to 10 nm. More specifically, the resulting dopant concentration in the selective emitter is preferably at least 10 times as high as in the selective dopant diffusion region. More preferably, this ratio of doping concentrations is at least 100.

20 The diffusion resistance layer is suitably chosen from at least one layer of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide or other insulating material combinations, for instance comprising tantalum or titanium.. It is not excluded that a multilayer stack is used, such as 25 a multilayer stack of silicon oxide, silicon nitride and silicon oxide (ONO). Preferably an oxide is applied, and more preferably a high temperature oxide (HTO).

Most preferably, the diffusion resistance layer is applied, for instance, with Low -Pressure Chemical Vapour 30 Deposition (LPCVD), Atomic Layer Deposition (ALD) and thermal oxidation in the form of Rapid Thermal Anneal (RTA), as known to the skilled person. Thin layers may be applied 7 herewith in a suitable thicknesses and densities so as to optimize the diffusion rate of boron.

In accordance with a second aspect of the invention, a solar cell is provided that comprises a semiconductor 5 substrate with a front or first and an opposed rear or second side and provided with n-type dopant species in a first concentration. At least one selective emitter region is defined adjacent to the front side and comprises p-type dopant species. A diffusion region comprising p-type dopant 10 species surrounds said at least one selective emitter region, said diffusion region and said at least one selective emitter region jointly operating as an emitter. A field region is defined adjacent to the rear side and comprises n-type dopant species at a concentration higher 15 than the first concentration, which emitter, substrate and field region together define a p-i-n diode. Suitably, a diffusion resistance layer overlies the diffusion region, at least on the first side and more preferably also along walls of any via extending from the first side to the second side. 20 Such diffusion resistance layer is suitable to define the diffusion region in an appropriate concentration. It is however not excluded that the diffusion resistance layer is removed in an etching step after the provision of the diffusion region into the substrate through the diffusion 25 resistance layer. If removed, another adhesion layer is suitably applied.

The presence of vias through the substrate so as to connect first terminals to the selective emitter regions is most preferred and a typical feature of metal-wrap through 30 (MWT) and emitter-wrap through (EWT) solar cells, known per se to the skilled person. For sake of clarity, the term 'via' is used herein to refer to an electrical conductor in a through-hole. The via is suitably a completely filled 8 through-hole, although it is not excluded that voids could be left in the via due to limitations in the manufacturing process. The diffusion resistance layer is preferably present in the through-hole so as to avoid the generation of 5 boron-rich silicon layers. While the diffusion resistance layer on the front side of the substrate could be removed in an etching treatment, the diffusion resistance layer inside the through-hole is likely maintained.

Typically, the substrate is a monocrystalline 10 semiconductor substrate. More suitably, a passivation layer, also operating as an anti-reflection coating is present on the first side

In a further embodiment, the field region is applied patternwise, such that a first portion destined for 15 provision of the through-hole is kept outside the field region. This eliminates the need of the provision of a trench or groove or the like in a separate step. Still, the walls of the through-hole and any extension of the emitter region applied thereto may and suitable will extend to the 20 rear side of the substrate. This is deemed beneficial for improved robustness. Particularly an opened substrate surface such as a groove or trench may give rise to contamination and/or to increased diffusion along the substrate surface. Such effects can only harm the device 25 operation and lifetime.

Moreover, the extension of the through-hole from the front to the rear side of the substrate furthermore facilitates the application of the conductor by means of electroplating or electroless deposition rather than by 30 screenprinting a metal paste. Such replacement is for instance beneficial in order to lower alignment tolerance between the definition of (selective) emitter regions and conductors. When applying said conductors by means of 9 electroplating it is most suitable that the metal paste is replaced completely rather than merely in the through-holes, i.e. for the definition of conductors on the front side, on the rear side and in the through-holes. The filling of 5 through-holes by means of electroplating may be achieved for instance by a bridge process, but alternatively by coating or printing a conductor in the through-hole, so as to coat the through-hole wall. Examples of printable conductor materials suitable as a plating base include conductive 10 polymers, such as polyethylenedioxythiophene (PEDOT), conductive epoxies, silver, for instance in the form of nanoparticles and the like. In an electroplating bridge process a distance between two electroplated portions is bridged. The two portions of the through-holes are typically 15 the front and rear side. Bridge formation may be supported by bridge formation means, for instance the temporary provision of an electrode within the through-hole so as to provide a local voltage difference adequate for the electroplating process.

20 Applying conductors on the front side by means of electroplating is particularly suitable in combination with the definition of selective emitter regions. It may be suitable to apply an intermediate adhesion layer on the selective emitter regions. Such adhesion layer may be 25 beneficial for reduction of contact resistance and the prevention of any undesired contamination. Examples of such materials are for instance polysilicon, titanium nitride, tungsten, tungsten nitride, titanium tungsten nitride, silver, aluminium and any alloys therewith.

30 According to a further aspect of the invention, a method of manufacturing a solar cell is provided, comprising the steps of: 10 providing a semiconductor substrate having an opposed first and second side and comprising n-type charge carriers; providing dopant species into the semiconductor substrate to form the emitter regions comprising p-type 5 charge carriers; providing through-holes into the semiconductor substrate, extending from the first side towards or to the second side; providing conductors extending from said emitter 10 regions to the second side of the semiconductor substrate through the through-holes comprising the step of electroplating said conductors in said through-holes.

According to again a further aspect of the invention, a solar cell is provided comprising a semiconductor substrate 15 with a first side and an opposed second side, which semiconductor substrate is provided with n-type dopant species in a first concentration; an emitter region present adjacent to the first side and comprising p-type dopant species; a field region present adjacent to the second side 20 and comprising n-type dopant species at a concentration higher than the first concentration, which emitter, substrate and field region together constituting a p-i-n diode; and a via extending from the first side to the second side of the semiconductor substrate and coupled on 25 the first side of the substrate to the emitter region and on the second side to a back contact, and comprising electroplated metal.

In accordance with these aspects of the invention, a method of electroplating the vias is provided, as well as a 30 solar cell comprising the resulting vias. It has been observed by the inventors that several features, particularly when applied in combination may be used to replace the commonly used screenprinting by electroplating.

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Such replacement allows to reduce the size of the vias substantially, for instance with 50% or more, preferably with 75% or more. Therewith the diameter of the via may be reduced to less than 100 microns, preferably less than 50 5 microns, more preferably less than 25 microns. This immediately leads to an increase in available surface area and thus to an increase of efficiency. A first feature enabling electroplating are particularly the provision of selective emitter regions exposed on the first side. These 10 can be used as an initial plating base. The term 'initial plating base' is used to express that the selective emitter regions could be the plating base themselves or one or more intermediate conductive layers applied on the exposed selective emitters could be used as plating base. A second 15 feature enabling the use of the electroplating is the provision of the patterned field region. This prevents the need for applying an additional trench from the second side, As a result thereof, the via is substantially straight, and the risk of short-circuitry on the second side as a 20 consequence of the electroplating process is reduced. A further feature of the invention is the provision of an appropriate barrier layer in the through-hole, which is for instance the diffusion resistance layer.

It will be understood that any features discussed 25 hereabove in relation to another aspect and/or illustrated in the figure description may be combined with these aspects in relation to electroplating, unless clearly contradictory.

BRIEF INTRODUCTION OF THE FIGURES 30 These and other aspects of the invention will be further elucidated with reference to the figures in which: 12

Fig 1-6 are diagrammatical, cross-sectional views of consecutive steps in a first embodiment of the method of the invention;

Fig. 7 is a diagrammatical top view on the first side 5 of the solar cell;

Fig 8. is an enlarged view of a portion of Fig. 7;

Fig. 9-13 are diagrammatical, cross sectional views of consecutive steps in a second embodiment of the method of the invention.

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DETAILED DESCRIPTION OF ILLUSTRATED EMBODIMENTS

The Figures are not drawn to scale and merely intended for illustrative purposes. Equal reference numerals in different figures refer to like or equal parts.

15 Fig 1-5 show in cross-sectional, diagrammatical view several stages of the method of the invention, resulting in the device shown in Fig. 6. As a first step, Fig. 1 shows a semiconductor substrate 10 with a front side 11 and a rear side 12. The front side is the side that is intended for 20 receiving irradiation during use; the solar cell will be assembled on its rear side 12 to a carrier. It typically has been texturized in advance of doping processes. The semiconductor substrate 10 of this example is a monocrystalline silicon substrate. While silicon substrates 25 constitute the best available compromise between manufacturing costs and quality, it is not excluded that alternative substrates are used. Such alternative substrates could be made of III-V materials, but more likely incorporate one or more layers of a different material, such 30 as a III-V material, or SiGe, SiC and the like as known to the skilled person. The semiconductor substrate is doped with a dopant of the first conductivity type, which is in the preferred example n-type. The doping concentration is 13 moderate, for instance 1016 /cm3. The semiconductor substrate 10 is provided at both the front side 11 and the rear side 12 with a region of n+-doped material. Suitably, use is made of phosphorous doping in a manner known to the skilled 5 person, for instance by vapor deposition. In one embodiment, the phosphorous doping is applied on the rear side 12 only, so as to define region 13B. The front side 11 is therein blocked from diffusion, for instance with a back-to-back arrangement of substrates 10. According to another 10 embodiment, the phosphorous doping is diffused into the regions 13A, 13B of the substrate 10 by a heat treatment of approximately 850 °C for 5-50 minutes in an atmosphere containing O2 and P2O5 vapour. This results in the formation of a silicon oxide film (not shown) which incorporates P205. 15 At the interface the substrate and the silicon oxide film, the P2O5 is reduced to elemental phosphorous, which diffuses into said regions 13A, 13B. Subsequently, the silicon oxide film is removed by dipping the substrate in a 1-50% HF solution for about 0.5-10 minutes, or exposing the substrate 20 to a HF vapour.

Fig.2 shows the substrate 10 in a second stage, after an etching treatment. Herein, the region 13A at the front side 11 is removed by etching, for instance using a mixed solution of 1-30% HF and 0.1-50% HNO3. This result in a 25 substrate 10 that has been doped at its rear side 12 with a dopant species of the first conductivity type to define at least one field region 13B. Moreover, a plurality of trenches 35 are etched at the rear side 12 of the substrate 10 located where thereafter through holes 20 will be 30 created, or through-holes 20 have been created. The trenches 35 are typically in the order of 1 - 7 mm in width, while the depth is conveniently chosen such that the doped region 13B at the rear side 12 (back-surface field) is obstructed 14 by etching away typically 0.4 - 2 micron of silicon. These trenches 35 can also be etched near the edge of the substrate 10. Moreover, a through-hole 20 is provided into the semiconductor substrate 10, within the boundaries of the 5 trench region 35, and extends from the front side 11 to the rear side 12 thereof. Typically, a plurality of through-holes 20 is applied in a single solar cell, so as to reduce a lateral distance over which generated current has to be transported to a terminal. The through-holes are typically 10 applied by laser etching, although other forms of etching, such as reactive ion etching or a combination of reactive ion etching and wet-etching are not excluded. While the through-hole 20 is shown to be straight, it is not excluded that the through-hole 20 is further modified to have a 15 varying diameter, or that any sharp edges at its top and bottom side, i.e. on the front side 11 and the rear side 12 are removed. The diameter of the through-hole is typically in the order of 5-300 microns.

Fig. 3 shows the substrate 10 in a third stage, after 20 application of a diffusion resistance layer 22. The diffusion resistance layer 22 is suitably applied by chemical vapour deposition or thermal oxidation, and more preferably by low pressure chemical vapour deposition (LPCVD), atomic layer deposition (ALD) or a rapid thermal 25 anneal (RTA). Such state of the art techniques can be applied to provide a diffusion resistance layer of good thickness uniformity which covers the substrate sides. The diffusion resistance layer suitably comprises an inorganic material such as an oxide or a nitride of silicon, titanium, 30 tantalum, mixtures thereof, combinations thereof (a sublayer of S1O2, and a sublayer of SiN). Use of an oxide layer, particularly a silicon oxide film, is preferred, as it allows diffusion of boron into the semiconductor substrate 15 10 at a reduced rate. The exact composition as well as density of the diffusion resistance layer may be varied by tuning of the composition of the gas. In the present embodiment, the diffusion resistance layer 22 is 5 particularly intended so as to prevent a boron rich layer that is believed to be responsive for fast carrier lifetime degradation in the bulk of the substrate 10. The diffusion resistance layer is further intended to create selective emitter regions. However, it is not excluded, and it may 10 even be advantageous, that outside the selective emitter regions p+ material is present but in a lower dopant concentration, particularly resulting from diffusion through the diffusion resistance layer. The diffusion resistance layer 22 may have a relatively low thickness, for instance 15 in the order of 0.5-5 nm.

It is not excluded that the diffusion resistance layer is applied with an alternative technigue, such as a low temperature oxide, for instance a Plasma enhanced chemical vapour deposition (PECVD). Upon providing a boron oxide - in 20 situ converted from a boron source such as boron tribromide (BBr3) - the boron oxide then tends to be absorbed, at least partially, in the low temperature oxide, resulting in a boron silicate glass. Reduction of the boron diffusion may then be achieved by operating in an atmosphere substantially 25 free of hydrogen, and more particularly in an inert atmosphere such as nitrogen (N2) or argon.

As shown in Fig. 3, the diffusion resistance layer 22 of this embodiment extends both on the front side 11, the rear side 12 and on walls of the through-holes 20. This is 30 the consequence of application thereof in a chemical vapour deposition step without blocking of any of the sides to prevent the application of the barrier layer 22. However, that is not deemed necessary. For instance, either the front 16 side 11 or the rear side 12 may be blocked from deposition of the chemical vapour, particularly in a back-to-back arrangement of the semiconductor substrates 10. It is even possible, in line therewith, to apply a stacked arrangement 5 such that both the front side 11 and the rear side 12 of the stacked substrates 10 will not be exposed. This provides freedom to deposit alternative layers on the front side than in the through-hole. For instance, the through-hole 20 may contain a nitrogen-containing diffusion resistance layer 22, 10 while the front side 11 is provided with a high temperature oxide layer as diffusion resistance layer 22A allowing boron diffusion at a reduced rate. The diffusion resistance layer 22A is then subsequently opened in accordance with a predefined pattern so as to create apertures 25.

15 The provision of such pattern is suitably carried out with photolithography, typically by using a mask, as known to the skilled person. In the present domain of solar cells, high resolution patterning such as known from integrated circuit manufacturing is however not required. A more 20 simplistic solution as the screenprinting of a local mask around an aperture area, and thereafter providing an etchant liquid in the thus created, screenprinted basin, is not excluded. Such a mask is suitably removed again prior to the subsequent high temperature doping step. Alternatively, one 25 could use a screenprinting slurry or an inkjet printing slurry, which includes an etchant in itself. One particularly preferred embodiment, is the use of a screenprinting slurry or paste based on a borate acid etchant. This enables to etch the diffusion resistance layer 30 22A and to provide doping into the semiconductor substrate 10 in a single step.

Fig. 4 shows the substrate 10 in a fourth stage, after the provision of the doping species of a second type, in 17 this case p+ type. The Boron diffusion source may be a vapour source or a coating source. In the oven the substrate is heated for a certain period of time and to a certain temperature so as to diffuse Boron into the front side of 5 the substrate 10, and create selective emitter regions 30, and around those diffusion regions 31 of a lower concentration. While the present figures show the selective emitter regions 30 and the diffusion regions 31 are separate regions, it will be understood that these are portion of a 10 continuous emitter. Simultaneously, the phosphorous doping at the rear side 12 of the substrate 10 is diffused as well, so as to create a double-diffused field region 33. The trench 35 provided in an earlier stage is now separating the double diffused region 33 from the boron doped region 31 in 15 the through-hole 20, thereby preventing any short-circuit between the double-diffused field region 33 and the conductor to be provided in the through-hole 20. Successful results have been obtained with a Boron vapour source for the diffusion. Two substrates are put back-to-back into the 20 oven and heated at 900-1000°C for 30-120 minutes, for instance at 950 °C for 1 hours in an atmosphere including an O2 and boron oxide (B2O3) vapor. As explained above, this B2O3 vapor is typically in situ created from a Boron tribromide (BBr3) vapour in the presence of oxygen. The boron oxide 25 vapour reacts with the silicon surface to create elemental boron and silicon oxide. The elemental boron then diffuses into the silicon substrate.

The silicon oxide is typically contaminated with boron oxide, resulting in a borosilicate glass. After the 30 termination of the diffusion treatment, the borosilicate glass is suitably removed. The removal of the borosilicate glass may be effected either with an acid such as HF that will also remove at least part of the diffusion resistance 18 layer 22A. Alternatively, use can be made of hot water or any other known etchant which allows selective etching of the borosilicate glass. In the event that a boron-rich layer develops in the selective emitter regions 30, it will be 5 present directly at the substrate surface, in a thickness of typically at most 20 nm. An oxidation step may then be carried out to oxidize the silicon rich layer and a thin silicon layer below it. The oxidation step will further create a new oxide on the front side 11 outside the 10 selective emitter regions 30, if the diffusion resistance layer 22A has been removed completely. It has turned that out, when applying conductors with screenprinting techniques, these oxides need not to be removed separately.

Fig. 5 shows the substrate 10 in a fifth stage, after 15 the application of a passivation layer 32A, 32B on both the front side 11 and the rear side 12. The passivation layer suitably comprises SiN, as known to the skilled person, but alternative materials are by no means excluded. It goes without saying that the passivation layers 32A, 32B could be 20 applied in separate steps and then do not need to have identical composition. The passivation layer 32A, 32B may be applied as well in the through-hole 20, on top of the diffusion resistance layer 22. Suitably, the process is tuned so as to achieve higher growth rates on the front side 25 11 and/or on the rear side 12 than in the through-hole 20.

Instead of growing the passivation layer 32A, 32B into the through-hole, a separate barrier layer could be applied.

Instead of applying a nitride passivation layer, stacks of amorphous silicon layers may be deposited on the front 30 side 11 and optionally on the rear side 12. These amorphous silicon layers are suitably deposited by Plasma enhanced chemical vapour deposition (PECVD), for instance in a parallel plate plasma deposition driven by a 13.5 MHz power 19 source, or in an inductively coupled plasma PECVD set up.

The thickness of amorphous silicon layers is suitably 20 nm or less, more preferably 10 nm or less. The stacks comprise an intrinsic layer and a p-doped layer on the front side 11, 5 and an intrinsic layer and a n-doped layer at the rear side 12. It has turned out that such amorphous silicon layers not only act as passivation layers, but also result in silicon heterojunction solar cells.

Fig. 6 shows the resulting solar cell 100, after 10 application of conductors 40, 41 and of terminals 51, 52.

The conductors include a via 40, i.e. the filled through-silicon through-hole and the conductor 41 on the front side 11. The conductor 41 on the front side 11 suitably comprises silver, the via 40 for instance comprises a silver/aluminum 15 alloy or silver. Such type of conductors are typically applied using a metal paste by screenprinting in a process known in the art, as deemed most beneficial from a cost perspective. The screenprinting paste applied on the front side 11 is typically an acid-containing screenprinted paste 20 that is able, upon heating, to etch away underlying layers, i.e. portions of the passivation layer 32A and the diffusion resistance layer 22. The screenprinting paste applied in the via 40 is suitably free of acid, so as to ensure that the diffusion resistance layer 22 and any optionally applied 25 barrier layer is not removed. However, alternative manufacturing processes as known in the art are not excluded from the scope of the present invention. The present solar cell device 100 is provided with first terminals 51 and second terminals 52. It is observed that typically a 30 plurality of both the first terminals 51 and the second terminals 52 are present on the rear side 12 of the substrate 10, and that both are substantially dot-shaped. Suitably, the processing is carried out such that both 20 terminals are applied in a single process step. Therefore, most suitably, the via 40 extends to the same level as the substrate 10.

Fig. 7 and Fig. 8 show top views of the resulting solar 5 cell 100. Fig. 8 shows herein a detail of Fig. 7. An array of conductors 41 is provided that are connected to the underlying selective emitter regions 30. The conductor 41 suitably extends by several tens of microns outside the perimeter of the via 40.The selective emitter regions 30 are 10 in the form of straight lines at mutually egual distances. The conductors 41 extend along and over the selective emitter regions 30. This is deemed beneficial so as to have minimum resistance. It is however not excluded that the conductors 41 only partly extend or merely extend over a 15 portion of the selective emitter regions 30.

Fig. 9-13 show consecutive steps of a second embodiment of the method of the invention in cross-sectional diagrammatical views. With respect to the choice of layers, and specific process steps, this second embodiment 20 preferably uses the materials and processes specified as preferred in the first embodiment, such as a typically moderately n-type doped monocrystalline silicon substrate 10, use of phosphorous doping for instance by vapour deposition, etc. These materials and processes will not be 25 repeated in detail hereinforth.

As a first step, Fig. 9 shows a semiconductor substrate 10 with a front side 11 and a rear side 12. The semiconductor substrate 10 is provided at the rear side 12 with a region 13 of n+-doped material. In accordance with 30 the present embodiment, the n+-doped region 13 is applied according to a predefined pattern. It is moreover merely present at the rear side 12 and not at the front side 11.

The predefined pattern may be provided for instance by 21 applying a suitable mask in advance of the doping step, or by provision of a solid phase dopant that is applied in accordance with a pattern by screenprinting or inkjetprinting, or patterned, for instance in an etching 5 treatment, after deposition of the dopant. One suitable implementation is deposition of an oxide Si02 layer of typically 40-150nm by means of inkjet. This oxide will be masking the areas near the through-hole and the wafer edge. Subsequently phosphorus is diffused into the substrate at 10 the locations the mask is not present.. Hereafter the phosphorus oxide layer is etched (PSG etch) and subsequently a stacked layer 15 of oxide and nitride is deposited on the back-side 12 of the substrate. The thickness of the oxide and nitride stack is typically between respectively 50-200nm 15 and 5-30nm. Then an alkaline texturization etch is performed, which typically etches 5-15nm from the front side 11 of the substrate. Also the edges of the wafer are etched, removing any unwanted phosphorus doping at the edges. The oxide/nitride layer stack on the back-side blocks the 20 texturization from etching the back-side 12. .

Fig. 10 shows the substrate 10 in a second stage in the processing, after provision of a through-hole 20 and the provision of a diffusion barrier 22. The through-hole 20 is provided into the semiconductor substrate 10, and extends 25 from the front side 11 to the rear side 12 thereof.

Typically, a plurality of through-holes 20 is applied in a single solar cell, so as to reduce a lateral distance over which generated current has to be transported to a terminal. The diffusion barrier 22 extends in this example on the 30 front side 11 and in the through-hole 20. It is patterned so as to define an aperture 25. A suitable etchant for the diffusion barrier 22 may be applied by screenprinting, inkjet printing. Laser etching may be used alternatively.

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Fig. 11 shows the substrate 10 in a third stage, after application of p-type dopant so as to define the highly doped selective emitter 30 and the diffusion region 31. Moreover, in the heat treatment for diffusion of the p-type 5 dopant, the n-type dopant on the second side is simultaneously further diffused to constitute a field region 33. The distance between the field region 33 and the diffusion region 31 extending along a wall in the through-hole 20 is chosen in accordance with a design rule so as to 10 prevent short-circuitry. This design rule is determined by the difference between the through-hole diameter typically between 5 - 300 micron, while the oxide mask around the through hole typically has a diameter of between 1 and 7 mm.

Fig. 12 shows the application of an antireflective 15 coating layer of oxide and/or silicon nitride 32A at the front side 11.

Fig.13 shows the resulting solar cell 100, obtained by the provision of conductive material to define conductors 40, 41 and terminals 51, 52. The via metal paste composition 20 is chosen such that it will not form a contact to the side walls of the via 40 in the subsequent firing through step. Metal 41 and 52 are contacting respectively the emitter 31 and base regions 33 after firing through the anti-reflective layer 32A and back-side protection layer 15. Terminal 51 is 25 connecting via to the emitter to the front side selective emitters 30.. The conductors include a via 40, i.e. the filled through-silicon through-hole and the conductor 41 on the front side 11. The first terminals 51 and second terminals 52, are defined in one screen or stencil printing 30 step. It is observed that typically a plurality of both the first terminals 51 and the second terminals 52 are present on the rear side 12 of the substrate 10, and that both are substantially dot-shaped. Suitably, the processing is 23 5 carried out such that both terminals are applied in a single process step. Therefore, most suitably, the via 40 extends to the same level as the substrate 10.

Claims

A method for manufacturing a solar cell, comprising the steps of: 5. providing a semiconductor substrate with opposite first and second sides and containing n-type charge carriers; - applying a diffusion resistance layer of electrically conductive material to the first side 10 in accordance with a predetermined pattern of selective emitter regions to be formed in the semiconductor substrate; - applying doping to the semiconductor substrate to form the selective emitter regions that contain p-type charge carriers; - creating diffusion regions of doping by controlled diffusion of further doping through the diffusion resistance layer, which selective emitter regions and which diffusion regions together serve as emitter.

2. A method according to claim 1, further comprising the step of providing through-holes (through-holes) through the semiconductor substrate extending from the first side in the direction of or up to the second side, and applying the diffusion resistance layer in the holes.

3. Method as claimed in claim 2, wherein the predetermined pattern of selective emitter regions is entirely on the first side without extending into the holes.

The method of claim 1, wherein the diffusion resistance layer is patterned in a single step together with the application of doping in the selective emitter regions. 5

The method of claim 1 or 4, wherein the diffusion resistance layer patterning takes place with a printing process.

A method according to any one of the preceding claims, wherein the thickness of the diffusion resistance layer is between 1 and 30 nm, which thickness is measured on the first side of the substrate.

The method of any one of the preceding claims, wherein the diffusion resistance layer is a high temperature oxide.

8. Method as claimed in claim 7, wherein the high-temperature oxide is applied with low-pressure chemical vapor deposition, atomic layer deposition or thermal oxidation in a rapid thermal anneal treatment.

9. A method according to claim 5 or 6, wherein a boron-rich silicon layer formed in the selective emitter regions is degraded in a low temperature oxidation step.

10. The method of claim 2, further comprising the step of applying conductive material to the selective emitter regions, to form conductors of said selective emitter regions through the holes to the second side of the semiconductor substrate, and to provide back side contacts on the second side of the semiconductor substrate, wherein a first group of the rear contacts is connected to said conductors and a second group of the rear contacts is connected to a field area present on the second side of the semiconductor substrate

A solar cell comprising a semiconductor substrate with a first side and an opposite second side, said substrate comprising: 10. n-type conductor carriers in a first concentration - comprising at least a selective emitter region present on the first side and p-type charge carriers; - a diffusion region comprising p-type charge carriers that surrounds said at least one selective emitter region, which diffusion region and which at least one selective emitter region serving together as an emitter, and - a field region present on the second side and containing n-type charge carriers in a concentration higher than the first concentration, which emitter, substrate and field area together form a pin diode.

12. Solar cell according to claim 11, wherein the selective emitter region has a doping concentration that is at least ten times that of the doping concentration in the diffusion region.

A solar cell according to claim 11 or 12, wherein the diffusion region is covered by a diffusion resistance layer.

A solar cell according to claim 11 or 13, further comprising vias through the semiconductor substrate, which vias have walls which are preferably provided with a diffusion resistance layer, and optionally a barrier layer.

15. Solar panel comprising at least one solar cell according to one of claims 12 to 14 and a panel support, wherein at least some of the rear contacts of the solar cell are connected to conductors in the solar panel

A method for manufacturing a solar cell, comprising the steps of: - providing a semiconductor substrate with opposite first and second sides and containing n-type charge carriers; - applying doping to the semiconductor substrate to form one or more emitter regions that contain p-type charge carriers; Making holes (through holes) through the substrate, which extend from the first side to the second side; - arranging conductors extending from the emitter regions to the second side of the semiconductor substrate through the holes, in which the conductors are provided in said holes with electroplating.

17. A method according to claim 16, wherein said emitter regions contain selective emitter regions which are exposed on the first side of the substrate and serve as an initial plating base for electroplating the conductors.

18. A method according to claim 17, wherein an electrically conductive intermediate layer is applied to the selective emitters, which intermediate layer extends to said holes.

The method of any one of claims 16 to 18, wherein a conductive coating is applied to the walls of the holes prior to the electroplating process. 5

A method according to claim 19, wherein the conductive coating is applied in a liquid form, for example by printing or spraying.

21. A method according to claim 16, further comprising the step of applying a field region to the second side of the semiconductor substrate in a predetermined pattern such that a first portion of the substrate through which a first hole is to be formed remains outside the field region which field area is applied by arranging n-type charge carriers in a concentration higher than the concentration of charge carrier in (the bulk of) the substrate, which first part of the substrate serves as insulation between the conductor in the first hole which is connected is with an emitter area, and the field area.

A solar cell comprising a semiconductor substrate with a first side and an opposite second side, which substrate is provided with: 25. n-type conductor carriers in a first concentration - comprising an emitter region present on the first side and p-type charge carriers; - a field region present on the second side and containing n-type charge carriers in a concentration higher than the first concentration, which emitter region, substrate and field region together form a pin diode, and - a via which extends from the first to the the second side of the semiconductor substrate and is connected on the first side to the emitter region and on the second side to a rear contact which comprises metal obtained by electroplating.

The solar cell of Claim 22, wherein the via is electrically isolated from the field area by a first portion of the substrate located on the second side.