NL2006161C2

NL2006161C2 - Method of manufacturing a solar cell and solar cell thus obtained.

Info

Publication number: NL2006161C2
Application number: NL2006161A
Authority: NL
Inventors: Klaas Heres; Johannes Reinder Marc Luchies; Patrick Willem Hubert Heuts
Original assignee: Tsc Solar B V
Priority date: 2011-02-08
Filing date: 2011-02-08
Publication date: 2012-08-09

Description

Method of manufacturing a solar cell and solar cell thus obtained

FIELD OF THE INVENTION

5 The present invention relates to a method of manufacturing a solar cell, comprising the steps of (1) providing a semiconductor substrate having a first and an opposed second side and a plurality of through-holes extending from the first side to the second side, which 10 semiconductor substrate is provided with an emitter region and with a field region, which field region comprises charge carriers of a first conductivity type and is defined adjacent to the second side, which emitter region comprises charge carriers of a second conductivity type, opposed to 15 the first conductivity type, and is defined adjacent to the first side; (2) applying an anti-reflective coating onto the barrier layer on the first side of the substrate, and (3) applying metal paste into the through-holes, and applying a heat treatment for converting said through-holes filled with 20 metal paste into vias.

The present invention further relates to a solar cell thus obtained

BACKGROUND OF THE INVENTION

25 Back-contacted solar cells such as manufacturable in accordance with the invention have been under development over the last decade. They are based on a monocrystalline or polycrystalline semiconductor substrate, typically a silicon substrate. The first side of this substrate is typically the 30 side at which radiation enters the substrate for conversion into electrical energy. Typically, both the substrate surface is textured and an anti-reflection coating is provided on the first side so as to ensure that the 2 radiation passes into the semiconductor substrate rather than being reflected on its surface. Recently, it has been found that n-type semiconductor substrate with an n-type doped field region and a p-type doped emitter region may 5 provide a higher overall efficiency.

In the back-contacted solar cells, the terminals of positive and negative polarity, connected to the emitter region and the field region, are both arranged on the back side, i.e. the second side, of the semiconductor substrate. 10 Specific metallization schemes are known as metallization wrap through (MWT) or emitter wrap through (EWT). Advantages of back-contacted solar cells include simplification of assembly of solar cells into panels, as well as an increase in the effective surface area on the first side through 15 reduction of the amount of conductors on the first side.

Vias provide the connection between the emitter region on the first side and the first terminals on the second side of the semiconductor substrate. Such vias are typically provided by screenprinting metal paste that converted into a 20 suitable conductor in a heat treatment. Typically not merely the vias are provided with screenprinting, but also any conductors on the first side of the semiconductor substrate and the terminals on the second side of the substrate.

One example of a process for forming back-contacted 25 solar cells, is known from W02009/067005 A1. This process teaches the provision of aluminium paste that is annealed in the heat treatment. The annealing results in melting and thus a better filling of the via. It further results in alloying of the silicon substrate with the aluminium. But 30 aluminium is also a p-type dopant. Such p-type dopant may diffuse into the n-type substrate and recombine with the n-type charge carriers during the heat treatment. A substrate zone with a very low dopant concentration may then be 3 generated. This substrate zone around the via could act as an insulation so as to prevent that currents running through the via from or to the emitter region will result in leakage currents into the substrate directly.

5 However, aluminum is known to diffuse in silicon very quickly. In view of the presence of the first and second terminals of opposite polarity adjacent to each other on the second side of the substrate, and the extension of the field region into the semiconductor substrate, a reliability risk 10 is present in that the aluminum will generate a leakage path between the via and the field region.

An alternative approach is known from WO2010/049268A1. The patent application proposes the provision of the emitter region on the second side and the provision of the field 15 region on the first side and along the walls of the through-holes extending to the second side. A passivation layer is then provided both on the first side and on the walls of the through-holes. The passivation layer further functions as an anti-reflection layer and is specified to be preferably a 20 PECVD deposited silicon nitride layer. The silicon nitride layer may be present directly on the semiconductor substrate surface or on a thin oxid that has been deposited either by oxidation or by coating. Instead of using a silicon nitride layer, use can be made of a separate passivation layer, for 25 instance of amorphous silicon or silicon carbide, and a separate antireflection layer.

It is however a disadvantage of this alternative approach, that the emitter is located further away from the first side, where the radiation enters the semiconductor 30 substrate. Such reversal of emitter and field region is deemed to have a negative impact on the overall efficiency of the solar cell. Moreover, the extension of the usually hard and rigid passivation layer of typically nearly 100 nm 4 thickness in the through-holes typically introduces stresses resulting from differential thermal expansion (and contraction) during and after heat treatments and in thermal cycling during use.

5 In view of the disadvantages of both approaches, there is a need to provide an improved method of manufacturing a back-contacted solar cell, wherein the emitter region is located adjacent to the first side, which is intended for receiving irradiation and wherein the risk of shunting 10 between the vias and the semiconductor substrate is reduced and preferably prevented.

SUMMARY OF THE INVENTION

In accordance with a first aspect of the invention, a 15 method of manufacturing a solar cell is provided comprising the steps of:

Providing a semiconductor substrate having a first and an opposed second side and a plurality of through-holes extending from the first side to the second side, which 20 semiconductor substrate is provided with an emitter region and with a field region, which field region comprises charge carriers of a first conductivity type and is defined adjacent to the second side, which emitter region comprises charge carriers of a second conductivity type, opposed to 25 the first conductivity type, and is defined adjacent to the first side;

Applying a barrier layer onto the first side and into the through-holes;

Applying an anti-reflective coating onto the barrier 30 layer on the first side of the substrate;

Applying conductive material into the through-holes so as to form vias, wherein the barrier layer prevents acid- 5 catalysed diffusion of metal during via formation into the semiconductor substrate.

In accordance with a second aspect in accordance with the invention, a solar cell is provided comprising a 5 semiconductor substrate having a first and an opposed second side and a plurality of vias extending from the first side to the second side, which semiconductor substrate is provided with an emitter region and with a field region, which field region comprises charge carriers of a first 10 conductivity type and is defined adjacent to the second side, which emitter region comprises charge carriers of a second conductivity type, opposed to the first conductivity type, and is defined adjacent to the first side, which vias comprise conductive material in a through-hole for 15 electrically coupling the emitter region to first terminals on the second side of the semiconductor substrate, at least one second terminal being electrically coupled to the field region. Herein a barrier layer is present on the first side of the semiconductor substrate and in the through-holes, 20 said barrier layer acting as a diffusion barrier against acid-catalyzed diffusion of metal into the semiconductor substrate during via formation and acting as an adhesion layer on the first side of the semiconductor substrate for an anti-reflective coating present thereon.

25 In accordance with the invention, a barrier layer is provided prior to deposition of the antireflection coating. The barrier layer effectively fulfills the functions of adhesive layer for the antireflection coating and of diffusion barrier for the prevention of acid-catalysed 30 diffusion of metal into the semiconductor substrate during via formation. Most suitably, the barrier layer is an electrically insulating layer, which further contributes to the prevention of shunting.

6

The present invention is based on the insight that a barrier layer needs to be deposited such as to be suitable for use within a through-hole needs to be stable under acid-catalysed conditions, particularly in the presence of acid 5 in a solvent. Thereto, both the material and the deposition conditions have an impact.

Most suitably, the barrier layer has a thickness of at least 2 nm, more preferably of at least 3 nm, or even of at least 5 nm. Preferably, the thickness is at most 25 nm, more 10 preferably at most 15 nm and more preferably 10 nm.

Suitably, the barrier layer is a conformal barrier layer. As a conformal layer, the barrier layer suitably is characterized in a very good step coverage and a small thickness variation. The step coverage is suitably at least 15 95%, more preferably at least 98% and even more preferably 99.5% or even closer to the absolute limit of 100% step coverage. Particularly inside the through-hole a step coverage of virtually 100% is desired. The thickness variation on the first side of the semiconductor substrate 20 and inside the through-holes of at most 50%, more preferably at most 25% and even more preferably at most 15%. It is not excluded that there is a difference in thickness of the barrier layer on the first side of the semiconductor substrate and in the through-holes. Preferably, this 25 thickness difference is however limited to 100%, more preferably 50%, more preferably 30% of the thinnest layer. Most preferably, the barrier layer is deposited with atomic layer deposition. This technique has been found to provide a dense and well-ordered layer that meets the requirements of 30 functioning as a barrier layer. It can moreover be deposited with a very high step coverage up to 100% and not merely on planar surfaces but also in trenches and through-holes with a high aspect ratio. In accordance with the present 7 invention, the aspect ratio of the through-holes is suitably between 5 and 50, preferably between 10 and 25.

A wide variety of materials is available for deposition as a barrier layer, for instance hafnium oxide, silicon 5 oxide, silicon nitride. Multilayers, for instance stacks of silicon oxide and silicon nitride, including ONO, NO, NON, ON, ONONO stacks may be applied alternatively. Suitably, the materials used as a barrier layer are free of metals suitable as a dopant of the semiconductor substrate.

10 Thereto, aluminum oxide is deemed not appropriate.

One additional advantage of the use of a conformal barrier layer is that any texture defined on the first side is not flattened off. Furthermore, any subsequent antireflection coating can be deposited on a smooth surface, which likely 15 leads to an optimal deposition process and hence, a homogeneous layer. Such resulting antireflection coating with a low thickness variation has a beneficial effect on the transmission of radiation into the substrate.

In one embodiment, the barrier layer is deposited prior to 20 doping the semiconductor substrate for creation of the emitter region. The barrier then serves the function as a diffusion resistance layer. Suitably, the emitter region is formed by diffusion of a boron dopant at a high temperature of for instance 700-1100°C, preferably between 900-1000°C.

25 Both in view of the high temperature and the small size of the boron atom, it is possible that a barrier layer against acid-catalysed diffusion may further act as a diffusion resistance layer that enables controlled diffusion.

Suitably, the barrier layer is selected such that the dopant 30 species of the second conductivity type (i.e. boron) will diffuse through the barrier layer at a diffusion rate that is at most substantially equal to a diffusion rate of the said dopant species of the second conductivity in the 8 semiconductor substrate. It is herein not excluded that the boron diffusion may be in the form of diffusion of boron oxide .

This embodiment serves the prevention of issues 5 relating to boron diffusion into through-holes. Boron diffusion is typically applied as BBr3 in an oxygen atmosphere. This converts the BBr3 to liquid boron oxide (B2O3) and gaseous brome (Br2) . The liquid boron oxide condenses on the silicon wafer surface. Chemical reaction 10 with the silicon surface produces silicon oxide (Si02) and elemental boron. The Si02 is partly dissolved in the liquid B2O3, resulting in a mixed-phase B2C>3-Si02 system, also known as boron silicate glass (BSG). Mainly during the heat treatment, the elemental boron diffuses according to the 15 boron gradient into the silicon wafer as well as into the BSG system. During this process a very high concentration of boron ("boron pile up") can occur at the surface of the wafer that transforms a surface layer of the silicon wafer into a SiB compound, forming a boron rich layer (BRL). The 20 Si-B compound is particularly hexaborylsilicon (SiBe) . This boron rich layer is however commonly associated with degradation of the carrier lifetime in the bulk of the wafer. The problem tends to become more pronounced due to the presence of the through-holes in the substrate, as the 25 effective surface area of the substrate therewith increases and gives rise to variations in diffusion of the boron compounds across the wafer.

Subsequent removal of the barrier layer after the boron diffusion is not deemed necessary. While a boronsilicate 30 glass may be formed, particularly in case of patterning such barrier layer at the front side, such boron silicate glass may be removed selectively with respect to the barrier layer .

9

In certain embodiments, the barrier layer is further patterned on the front side prior to the doping, so as to achieve a difference in concentration between a exposed regions and non-exposed regions of the semiconductor 5 substrate. A selective emitter will be formed in the exposed regions; diffusion regions will be formed in the non-exposed regions. A concentration difference between the selective emitter and the diffusion regions may be further increased by additionally doping the selective emitter, for instance 10 by application of a solid state dopant source.In a further embodiment, the barrier layer is defined as a passivation layer, separately or as a combination with a further layer. This has the advantage that there is a larger design freedom in choosing the antireflection coating. Examples include an 15 antireflection coating comprising nanorods; an antireflection coating comprising a first and a second sublayer, for instance of oxide and nitride; a layer stack of different materials, a layer comprising a core-shell structure such as known from W02009/050639 and 20 W02010/018490, for instance of titanium oxide and titanium nitride particles.

In one embodiment, the conductive material is applied as a metal paste composition. Such metal paste composition comprises rheology aids, anti-oxidants, a solvent, and an 25 organic acid as a basis of the flux. Typically use is made of rosin as the organic acid on which the flux is based. An activator responsible for attacking metal surfaces resulting in cleaning is typically present but could be left out or be present in minor amounts ("Low activity"). The flux is 30 responsible for removal of underlying passivation layers and the prevention of oxidation of the metal, so as to ensure that a proper low-resistive contact is formed. In order to protect the barrier layer inside the through-hole, the metal 10 paste composition used for filling the through-hole preferably is chosen to be a metal paste composition with a low acid value, for instance lower than 150 and preferably lower than 130. The acid value is related to the organic 5 acid and corresponds to the KOH mg equivalent. The acid value is determined using a simple KOH titration. One suitable metal paste is for instance a low activity silver paste sold by Heraeus under the tradename HeraSol SOL 109.

In an alternative embodiment, the conductive material 10 is applied by means of electroplating or electroless deposition rather than by screenprinting a metal paste. Such replacement is for instance beneficial in order to lower alignment tolerance between the definition of (selective) emitters and conductors. When applying said conductors by 15 means of electroplating it is most suitable that the metal paste is replaced completely rather than merely in the through-holes, i.e. for the definition of conductors on the front side, on the rear side and in the through-holes. The filling of through-holes by means of electroplating may be 20 achieved for instance by a bridge process, but alternatively by coating or printing a conductor in the through-hole, so as to coat the through-hole wall. Examples of printable conductor materials suitable as a plating base include conductive polymers, such as polyethylenedioxythiophene 25 (PEDOT), conductive epoxies, silver, for instance in the form of nanoparticles and the like. PEDOT is for instance commercially available as an aqueous dispersion, mixed with polystyrene sulfonic acid. This aqueous composition excellently wets an oxide or nitride surface. In an 30 electroplating bridge process a distance between two electroplated portions is bridged. The two portions of the through-holes are typically the front and rear side. Bridge formation may be supported by bridge formation means, for 11 instance the temporary provision of an electrode within the through-hole so as to provide a local voltage difference adequate for the electroplating process.

Applying conductors on the front side by means of 5 electroplating is particularly suitable in combination with the definition of selective emitters. These selective emitters will then constitute the plating base on top of which metal may be applied. It may be suitable to apply an intermediate adhesion layer on the selective emitters. Such 10 adhesion layer may be beneficial for reduction of contact resistance and the prevention of any undesired contamination. Examples of such materials are for instance polysilicon, titanium nitride, tungsten, tungsten nitride, titanium tungsten nitride, silver, aluminium and any alloys 15 therewith.

In a further embodiment, the field region is applied patternwise, such that a first portion intended for definition of the through-hole is kept outside the field region. This eliminates the need of the provision of a 20 trench or groove or the like in a separate step. Still, the walls of the through-hole and any extension of the emitter region applied thereto may and suitable will extend to the rear side of the substrate. This is deemed beneficial for improved robustness. Particularly an opened substrate 25 surface such as a groove or trench may give rise to contamination and/or to increased diffusion along the substrate surface. Such effects can only harm the device operation and lifetime. Moreover, the extension of the through-hole from the front to the rear side of the 30 substrate furthermore facilitates the application of the conductive material by means of electroplating or electroless deposition.

12

BRIEF INTRODUCTION OF THE FIGURES

These and other aspects of the invention will be further elucidated with reference to the figures, in which: 5 Fig 1-4 show in diagrammatical cross-sectional view several stages of the method of the invention;

Fig. 5 shows in diagrammatical cross-sectional view the device of the invention according to one embodiment.

10 DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The Figures are not drawn to scale and merely intended for illustrative purposes. Equal reference numerals in different figures refer to like or equal parts.

Fig 1-4 show in cross-sectional, diagrammatical view 15 several stages of the method of the invention, resulting in the device shown in Fig. 5. As a first step, Fig. 1 shows a semiconductor substrate 10 with a first side 11 and a second side 12. The first side 11 will also be referred to hereinafter as the front side. The second side 12 will also 20 be referred to as the rear side. The front side is the side that is intended for receiving irradiation during use; the solar cell will be assembled on its rear side 12 to a carrier. It typically has been texturized in advance of doping processes. The semiconductor substrate 10 of this 25 example is a monocrystalline silicon substrate. While silicon substrates constitute the best available compromise between manufacturing costs and quality, it is not excluded that alternative substrates are used. Such alternative substrates could be made of III-V materials, but more likely 30 incorporate one or more layers of a different material, such as a III-V material, or SiGe, SiC and the like as known to the skilled person. The semiconductor substrate is doped with a dopant of the first conductivity type, which is in 13 the preferred example n-type. The doping concentration is moderate, for instance 1016 /cm3. The semiconductor substrate 10 is provided at the rear side 12 with a region of n++-doped material. Suitably, use is made of phosphorous doping 5 in a manner known to the skilled person, for instance by vapor deposition. According to one embodiment, the phosphorous doping is diffused into the regions 13B of the substrate 10 by a heat treatment of approximately 800 °C for 5-50 minutes in an atmosphere containing 02 and P205 vapour. 10 This results in the formation of a silicon oxide film (not shown) which incorporates P205 . At the interface the substrate and the silicon oxide film, the P205 is reduced to elemental phosphorous, which diffuses into said regions 13B. Subsequently, the silicon oxide film is removed by dipping 15 the substrate in a 1-50% HF solution for about 0.5-10 minutes, or exposing the substrate to a HF vapour.

Typically, the phosphorous doping is carried out both at the front side 11 and at the rear side 12, and a substrate layer at the front side 11 is thereafter etched away. It will be 20 clear that this is however merely one suitable embodiment.

Moreover, a through-hole 20 is provided into the semiconductor substrate 10, and extends from the front side 11 to the rear side 12 thereof. Typically, a plurality of through-holes 20 is applied in a single solar cell, so as to 25 reduce a lateral distance over which generated current has to be transported to a terminal. The through-holes are typically applied by laser etching, although other forms of etching, such as reactive ion etching or a combination of reactive ion etching and wet-etching are not excluded. While 30 the through-hole 20 is shown to be straight, it is not excluded that the through-hole 20 is further modified to have a varying diameter, or that any sharp edges at its top and bottom side, i.e. on the front side 11 and the rear side 14 12 are removed. The diameter of the through-hole is typically in the order of 5-400, preferably 100-300 microns .

A selective emitter 30 is provided in the semiconductor 5 substrate 10 at the first side 11. The selective emitter 30 is intended as a contact region for a conductor to be applied on top of the first side 11, and has a relatively high concentration of dopant. The provision of the selective emitter in accordance with a predefined pattern may be 10 achieved with diffusion or implantation through with a mask. Alternatively, use can be made of printing technologies such as screenprinting and inkjetprinting, for deposition of a paste. In one suitable embodiment, use is made of a paste composition comprising a boron acid. Such boron acid may be 15 used for etching any diffusion resistance layer - if present - and for locally doping the semiconductor substrate 10. A diffusion resistance layer - not shown in Figure 1 -is suitably sufficiently thin to allow diffusion of boron through this layer. The advantage thereof will be that the 20 diffusion rate is reduced to a level comparable to the diffusion rate of boron in the silicon substrate. It is therewith prevented that an excess of boron is left near to the semiconductor surface, resulting in a boron rich layer that is deemed to have a negative impact on carrier 25 lifetime. Such diffusion resistance layer is particularly a high temperature oxide. It is suitably applied by chemical vapour deposition or thermal oxidation, and more preferably by low pressure chemical vapour deposition (LPCVD), atomic layer deposition (ALD) or a rapid thermal anneal (RTA). Such 30 state of the art techniques can be applied to provide a diffusion resistance layer of good thickness uniformity which covers the substrate sides. The diffusion resistance layer suitably comprises an inorganic material such as an 15 oxide or a nitride of silicon, titanium, tantalum, tungsten, mixtures thereof (TiWN, SiON), combinations thereof (a sublayer of S1O2, and a sublayer of SiN). Use of an oxide layer, particularly a silicon oxide film, is preferred, as 5 it allows diffusion of boron into the semiconductor substrate 10 at a reduced rate. The exact composition as well as density of the diffusion resistance layer may be varied by tuning of the composition of the gas. If present, the diffusion resistance layer suitably has a relatively low 10 thickness, for instance in the order of 0.5-5 nm, more preferably at most than 3 nm.

Fig. 2 shows the semiconductor substrate after doping the substrate 10 with boron, and carrying out a heat treatment for diffusion thereof. It is observed that another 15 p-type dopant source could be used alternatively, though boron is preferred. The Boron diffusion source may be a vapour source or a coating source. In the oven the substrate is heated for a certain period of time and to a certain temperature so as to diffuse Boron into the front side of 20 the substrate 10, and create selective emitter regions 30, and around those diffusion regions 31 of a lower concentration. While the present figures show the selective emitter regions 30 and the diffusion regions 31 are separate regions, it will be understood that these are portion of a 25 continuous emitter. Simultaneously, the phosphorous doping at the rear side 12 of the substrate 10 is diffused as well, so as to create a double-diffused field region 33.

Successful results have been obtained with a Boron vapour source for the diffusion. Two substrates are put back-to-30 back into the oven and heated at 900-1000°C for 30-120 minutes, for instance at 950 °C for 1 hours in an atmosphere including an O2 and boron oxide (B2O3) vapor. As explained above, this B2O3 vapor is typically in situ created from a 16

Boron tribromide (BBr3) vapour in the presence of oxygen. The boron oxide vapour reacts with the silicon surface to create elemental boron and silicon oxide. The elemental boron then diffuses into the silicon substrate.

5 The silicon oxide is typically contaminated with boron oxide, resulting in a borosilicate glass. After the termination of the diffusion treatment, the borosilicate glass is suitably removed. The removal of the borosilicate glass may be effected either with an acid such as HF.

10 Alternatively, use can be made of hot water or any other known etchant which allows selective etching of the borosilicate glass. In the event that a boron-rich layer develops in the selective emitter regions 30, it will be present directly at the substrate surface, in a thickness of 15 typically at most 20 nm. A low temperature oxidation step may then be carried out to oxidize the silicon rich layer and a thin silicon layer below it. Therewith the silicon rich layer may be removed.

In order to separate the emitter region 31 and the 20 field region 33, a trench 35 has been applied in the through-hole 20 from the second side 12 of the substrate 10. This trench 35 is suitably provided prior to the doping with boron and the subsequent diffusion step. The extension of the field region 13B is then still most restricted, which 25 simplifies the removal.

Fig. 3 shows the substrate 10 in a subsequent step, after application of the barrier layer 22, comprising a portion 22A on the first side 11 of the semiconductor substrate 10 and a portion 22B in the through-hole 20. It is 30 herein not evident that any material apparently suitable as a barrier layer may be applied. The microstructure and properties of many materials, and particularly electrically insulating materials, turns out to depend on the deposition 17 and/or growth process. This is for instance known for silicon oxide, one of the most widely applied insulating materials in semiconductor processing. Silicon oxide is typically present as an amorphous layer, with inherent voids 5 or channels or contamination resulting from the deposition process. A thermal oxide has properties different from a chemical oxide, both in terms of structural order and surface smoothness. Therefore, the ability of a material for formation of an adequate diffusion barrier typically depends 10 on the deposition process. In accordance with the invention, the diffusion barrier is chosen to act as a barrier against acid-catalysed diffusion in via formation. Suitable manners of formation of a via include filling, at least partially, of through-holes with screenprinting metal paste, or 15 electroplating. In both cases, the via formation occurs in the presence of a solvent and an acid; screenprinting of metal paste typically uses an alcohol as a solvent, such as butyl carbitol, dibutyl carbitol, glycol and polyhydroxy alkphatic and aryl alcohols. Electroplating preferably uses 20 water as a solvent. Acids are present therein; in the case of a metal paste, rosin is suitably used, which comprises abietic acid and pimaric acid. For electroplating, sulfuric acid is typically present. In order to act as a diffusion barrier in acid-catalysed metal diffusion, the barrier layer 25 is suitably grown or deposited rather than being formed wet-chemically. In view of its application after the heat treatments for diffusion of dopant, a certain temperature limitation exists. Even though some further dopant diffusion is not detrimental, a treatment above 1000 °C will induce 30 major changes in an uncontrollable manner. Moreover, the complete surface area of the through-hole needs to be covered. Suitably, the barrier layer comprises a silicon based material wherein the Si/O ratio is smaller than 0.75, 18 preferably smaller than 0.7, more preferably smaller than 0.6 and optimally in the order of 0.5. Such material has a low-hydrogen content that is deemed suitable for its performance as a diffusion barrier.

5 In this example as shown, the barrier layer is a conformal barrier layer. The conformal barrier layer is applied in a structure with a high aspect ratio. Physical vapor deposition methods, such as evaporation and sputtering, have limited abilities to coat structures with 10 high aspect ratios and thus are not suitable for the invention. Wet chemical methods are applied onto the surface. However, their resulting thickness is limited, typically to 1 or 1.5 nm. This may be suitable as a thin oxidation layer for adhesion purposes, but is insufficient 15 as a barrier layer, particularly taking into account that wet chemical oxides are not dense. Conformal CVD reactions must have their slowest, rate-limiting steps on the surface of the growing film, rather than in the gas phase. Particularly high aspect ratios can be coated conformally by 20 a CVD method in which two complementary reactant vapors are supplied to a surface in alternate pulses. In this way, their reactions are forced to be entirely on the surface. This method is known as Atomic Layer Deposition (ALD). The barrier layers provided with ALD turn out to be conformal, 25 have a good thickness uniformity and a low leakage current when applying an electric field. Moreover, the silicon to oxygen ratio of ALD layers may be tuned to a ratio of nearly 0.5, for instance by application of additional oxygen/ozon or on the basis of ammonia catalysed hydrolysis of 30 tetraethoxysilane (TEOS).

In a further embodiment, use is made of a double layer process, comprising a first layer of silicon oxide, wherein the ratio between silicon and oxide is below 0.75, 19 preferably below 0.6 and most suitably around 0.5, and a second layer comprising a moisture barrier. A suitable moisture barrier is for instance a silicon rich layer, wherein the ratio between silicon and oxide is higher than 5 in the first layer. Alternatively, use can be made of silicon nitride

In one embodiment, use is made of a remote plasma atomic layer deposition process using an O2 plasma. Use is made of a FlexAL apparatus of Oxford Instruments. A constant 10 60 sscm O2 flow and pressure of 15mTorr are maintained in the reactor. The silicon precursor is injected into the reactor by fast (2o ms open-close) ALD valves. A 400W inductively coupled O2 plasma is used for oxidation. The total ALD cycle time, including pump and purge steps, is 4s. The reactor 15 wall is kept at a constant temperature of 120 °C and the precursor lines are kept at 50 °C. An increase in the deposition temperature results in a reduction of layer thickness with constant number of cycles. A deposition temperature of at least 200 °C appears suitable, so as to 20 minimize the incorporation of hydrogen into the layer. This improves the quality of the barrier. Preferably, the amount of hydrogen in the layer is less than 10 at%, preferably less than 5at%. The number of ALD cycles is suitably less than 300, for instance 100-200.

25 In a further embodiment, use is made of a batch ALD

reactor for deposition of silicon oxide and silicon nitride. A gas anneal was formed at 400 °C in an inert argon atmosphere with 3% H2. Silicon oxide was deposited using Si2Cl6 and Ο3/Ο2 as precursor gas. Deposition temperatures 30 were varied between 300 and 400 °C, leading to a growth rate in the range of 0.1-0.5 nm per cycle. Silicon nitride was deposited from SiH2Cl2 and NH3 as precursor gases. Deposition temperatures in the range of 400-500 °C were used, with a 20 growth rate in the order of 0.05-0.1 nm per cycle. With both experiments, leakage currents of less than 10“8 (A/cm2) at an electric field of 3MV/cm were observed. This further holds for O-N-O multilayers.

5 Fig. 4 shows the substrate 10 in a further stage, after the application of a passivation layer 32A, 32B on both the front side 11 and the rear side 12. The passivation layer 32A, 32B suitably comprises SiN, as known to the skilled person, but alternative materials are by no means excluded. 10 It goes without saying that the passivation layers 32A, 32B could be applied in separate steps and then do not need to have identical composition. The passivation layer 32A also serves as an antireflection coating. As shown in this Figure 4 the barrier layer 22A is patterned to create an aperture 15 25 corresponding to the location of the selective emitter 30. Provision of such aperture 25 is however not deemed necessary, particularly not when screenprinting the conductor in the subsequent slip.

Instead of applying a nitride passivation layer, stacks 20 of amorphous silicon layers may be deposited on the front side 11 and optionally on the rear side 12. These amorphous silicon layers are suitably deposited by Plasma enhanced chemical vapour deposition (PECVD), for instance in a parallel plate plasma deposition driven by a 13.5 MHz power 25 source, or in an inductively coupled plasma PECVD set up.

The thickness of amorphous silicon layers is suitably 20 nm or less, more preferably 10 nm or less. The stacks comprise an intrinsic layer and a p-doped layer on the front side 11, and an intrinsic layer and a n-doped layer at the rear side 30 12. It has turned out that such amorphous silicon layers not only act as passivation layers, but also result in silicon heterojunction solar cells.

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Fig. 5 shows the resulting solar cell 100, after that conductors 40, 41 and terminals 51, 52 have been applied.

The conductors include a via 40, i.e. the filled through-silicon through-hole and the conductor 41 on the front side 5 11. The conductor 41 on the front side 11 suitably comprises silver, the via 40 for instance comprises a silver/aluminum alloy or silver. Such type of conductors are typically applied using a metal paste by screenprinting in a process known in the art, as deemed most beneficial from a cost 10 perspective. The screenprinting paste applied on the front side 11 is typically an acid-containing screenprinted paste that is able, upon gentle heating to for instance 150-300 °C, to etch away underlying layers, i.e. portions of the passivation layer 32A and the diffusion resistance layer 22. 15 The screenprinting paste applied in the via 40 is suitably free of acid, so as to ensure that the diffusion resistance layer 22 and any optionally applied barrier layer is not removed. However, alternative manufacturing processes as known in the art are not excluded from the scope of the 20 present invention. The present solar cell device 100 is provided with first terminals 51 and second terminals 52. It is observed that typically a plurality of both the first terminals 51 and the second terminals 52 are present on the rear side 12 of the substrate 10, and that both are 25 substantially dot-shaped. Suitably, the processing is carried out such that both terminals are applied in a single process step. Therefore, most suitably, the via 40 extends to the same level as the substrate 10.

Claims

A method for manufacturing a solar cell, comprising the steps of:

Method according to claim 1, wherein the barrier layer is applied with atomic layer deposition.

The method according to claim 1 or 2, wherein the barrier layer is applied in a layer thickness of at least 2 nm and at most 25 nm, preferably in a layer thickness of 3 to 10 nm.

The method of claim 1 or 2, wherein the barrier layer comprises a first sublayer and a second sublayer. 5

The method of claim 4, wherein the first sublayer has a lower silicon to oxygen ratio than the second layer.

5. Providing a semiconductor substrate with a first and an opposite second side and a plurality of holes (through holes) extending from the first side to the second side, which semiconductor substrate is provided with an emitter region 10 and a field region, which field area comprises charge carriers of a first conductivity type and is present on the second side of the semiconductor substrate, which emitter area contains charge carriers of the second conductivity type, opposite to the first conductivity type, and is present on the first side of the semiconductor substrate, Applying a barrier layer on the first side and in the holes; Applying an anti-reflection layer to the barrier layer on the first side of the substrate; The provision of conductive material in the holes to form vias, wherein the barrier layer occurs acid-catalyzed diffusion of metal to the semiconductor substrate during the formation of the vias.

The method of claim 1 or 3, wherein the barrier layer is applied by oxidation of the semiconductor substrate in a rapid thermal anneal (RTA)

7. Method according to claim 1, wherein the conductive material is applied with electroplating.

8. Method according to claim 1, wherein the conductive material is applied as a metal paste and in which advantageously a metal paste with an acid value of less than 130 is used for filling the holes.

The method of Claim 8, wherein the holes are filled with a silver paste. 25

The method of claim 1, wherein the anti-reflection layer has a non-uniform composition.

11. The method of claim 1, wherein a diameter of a hole on the first side of the semiconductor substrate is smaller than a diameter of the hole at a predetermined depth.

12. Method as claimed in claim 1, comprising the steps of: Applying conductive material on the first side that extends from the holes to contact points of the emitter region, and. Providing first and second contacts on the second side, wherein the first contacts are electrically connected to the vias and the second contacts 10 are electrically connected to the field area.

13. Solar cell comprising a semiconductor substrate with a first and an opposite second side and a plurality of filled holes (through holes) extending from the first side to the second side, which semiconductor substrate is provided with an emitter region and a field region, which field region comprises charge carriers of a first conductivity type and is present on the second side of the semiconductor substrate, which emitter region comprises charge carriers of the second conductivity type, opposite to the first conductivity type, and is present on the first side of the semiconductor substrate, which filled holes of conductive material comprising for electrically connecting the emitter region to first contacts on the second side of the semiconductor substrate, wherein at least a second contact is electrically connected to the field region, wherein a barrier layer is present on the first side of the semiconductor substrate and in the holes, which barrier This layer serves as a barrier against acid-catalyzed metal diffusion into the semiconductor substrate during filling of the vias to form vias, and which barrier layer serves as an adhesion layer on the first side of the semiconductor substrate for an anti-reflection layer present thereon.

The solar cell according to claim 13, wherein the barrier layer is applied with atomic layer deposition.

A solar panel with a plurality of solar cells according to claim 13 or 14 that are assembled on a carrier.