WO2012067509A1 - Method for producing a semiconductor device and a semiconductor device - Google Patents

Method for producing a semiconductor device and a semiconductor device Download PDF

Info

Publication number
WO2012067509A1
WO2012067509A1 PCT/NL2011/050786 NL2011050786W WO2012067509A1 WO 2012067509 A1 WO2012067509 A1 WO 2012067509A1 NL 2011050786 W NL2011050786 W NL 2011050786W WO 2012067509 A1 WO2012067509 A1 WO 2012067509A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
boron
semiconductor device
semiconductor substrate
amorphous boron
Prior art date
Application number
PCT/NL2011/050786
Other languages
French (fr)
Inventor
Lis Karen Nanver
Peter Roelf Venema
Adrianus Henricus Gerardus Vlooswijk
Caroline Mok Kai Rine
Wiebe Barteld De Boer
Original Assignee
Tempress Systems Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tempress Systems Bv filed Critical Tempress Systems Bv
Publication of WO2012067509A1 publication Critical patent/WO2012067509A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type
    • H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
    • H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer or HIT® solar cells; solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
    • H01L31/1868—Passivation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Abstract

A method for manufacturing a semiconductor device, includes: providing a first conductivity-type bulk doped semiconductor substrate with a first surface and a second surface opposite thereto; removing the native oxide on at least one of the first and the second surface to expose the semiconductor material; by chemical vapor deposition using a boron precursor gas forming a layer of amorphous boron on top of the exposed semiconductor material such that an effective p++ type layer is formed.

Description

Method for producing a semiconductor device and a semiconductor device Field of the invention
The present invention relates to a method of producing a semiconductor device and such a semiconductor device .
Background of the invention
From the prior art, various types of semiconductor devices are known that comprise highly doped layers and/or passivating layers on a semiconductor substrate surface. One such type relates to a solid state photovoltaic cell which is known as to convert the energy of sunlight or another light source directly into electricity by the photovoltaic effect. In general, the photovoltaic effect is described as the generation of a potential difference at the junction of two different materials when receiving energy from sunlight or other radiation.
The general processes of the photovoltaic effect comprises:
• generating the charge carriers due to the absorption of photons in the materials that form a junction;
• separating the photo-generated charge carriers in the junction;
• collecting the photo-generated charge carriers at the terminals of the junction.
Figure 1 schematically shows a cross-sectional view of a typical structure of a solid state photovoltaic cell from the prior art. In figure 1 , a typical photovoltaic cell (or solar cell) 1 comprises a silicon substrate base layer 9 for generating photon-generated carriers, a silicon based emitter layer 7 arranged on top of the base layer 9 for collecting the photon-generated carriers, a front contact 3 connected to the emitter layer 7, a back surface field (BSF) layer 11 arranged on the bottom of the base layer 9 for
counteracting the diffusion of minority photon-generated carriers to reach a rear contact 15, the rear contact 15 connected to the BSF layer 11, an anti-reflection coating (ARC) layer 5 arranged on top of the emitter layer 7 for decreasing the reflection of light from the photovoltaic cell 1. The ARC layer 5 may serve as a passivation layer for passivating the surface of the photovoltaic cell 1 and optionally acting as hydrogen source for bulk passivation. Under certain circumstances the BSF layer 11 may serve as passivation layer.
However, a passivation layer 13 may be arranged on the bottom of the BSF layer 11 for passivating the surface of the photovoltaic cell 1 and reducing the surface
recombination in the rear side.
Typically, the BSF layer 11 is made of, with the same type as the base layer, high doped n type material or p type material. An electric field is formed in the BSF layer 11 which introduces a barrier to minority photon-generated carriers to reach the rear contact 15, thus reduces the recombination in the rear contact 15.
An internal electric field formed by a p-n junction between the base layer 9 and the emitter layer 7 in the photovoltaic cell 1 that facilitates the separation of the photon- generated carrier pairs, i.e., electrons and holes.
The major obstacles of the photovoltaic cell in the prior art document are relatively low cell efficiency, which is limited by optical and electrical losses, and relatively high cell cost.
It is noted that also other semiconductor device types like diodes and photodiodes that comprise highly doped layers like an emitter and/or passivating or BSF layers on a semiconductor substrate may also suffer from the recombination effect at the respective interface with the semiconductor substrate.
Also prior art methods are known for depositing highly doped layers on the
semiconductor substrate. To obtain highly doped p-type (or p+) layers or passivating layers on semiconductor substrate, chemical vapor deposition processes based on a boron precursor, are available that typically operate at temperatures above 700 °C even up to about 900 °C. In such process at the surface of the semiconductor substrate boron is released from the precursor and diffuses into the semiconductor substrate which results in the creation of boron containing highly doped semiconductor layer(s). The high process temperature may have an adverse effect on components of the
semiconductor device that is being fabricated.
Summary of the invention
It is an objective of the invention to reduce or mitigate the disadvantages from the prior art. According to an aspect of the invention, there is provided a method for manufacturing a semiconductor device, comprising:
providing a first conductivity-type bulk doped semiconductor substrate with a first surface and a second surface opposite thereto;
removing the native oxide on at least a portion of at least one of the first and the second surface to expose the semiconductor material;
by chemical vapor deposition using a boron precursor gas forming a layer of amorphous boron on top of the exposed semiconductor material such that an effective p++ type layer is formed.
According to an aspect of the invention, there is provided a method as described above, wherein the amorphous boron layer is formed by chemical vapor deposition from the boron precursor gas mixture comprising di-borane, and an inert gas.
According to an aspect of the invention, there is provided a method as described above, wherein the inert gas is selected from nitrogen and argon.
According to an aspect of the invention, there is provided a method as described above, wherein the amount of inert gas in the gas mixture is at least about 90 vol%.
According to an aspect of the invention, there is provided a method as described above, wherein the gas mixture contains about 5 vol% of di-borane or less.
According to an aspect of the invention, there is provided a method as described above, wherein the chemical vapor deposition process is one selected from a chemical vapor deposition process, a plasma enhanced, PE, CVD process, an atomic layer deposition,
ALD, process, an ultra-high- vacuum, UHV, CVD process and an inductive coupled plasma, ICP, CVD process.
According to an aspect of the invention, there is provided a method as described above, wherein the chemical vapor deposition process is an process at substantially
atmospheric pressure.
According to an aspect of the invention, there is provided a method as described above, wherein the chemical vapor deposition process is an process at a reduced pressure between about 10 and about 760 Torr (about 10 - 1010 hPa).
According to an aspect of the invention, there is provided a method as described above, wherein the deposition process temperature is at least 300°C.
According to an aspect of the invention, there is provided a method as described above, wherein the deposition process temperature is between about 350 and about 450°C. According to an aspect of the invention, there is provided a method as described above, wherein the deposition process temperature is about 400°C.
According to an aspect of the invention, there is provided a method as described above, wherein the formed boron layer is a conformal layer.
According to an aspect of the invention, there is provided a method as described above, further comprising:
- after forming the amorphous boron layer, exposing the semiconductor device to a nitrogen ambient, substantially free of di-borane, and
- ramping the process temperature to a high temperature between about 700 and about 900 °C.
According to an aspect of the invention, there is provided a method as described above, further comprising:
covering the first surface by an ARC/passivation layer;
forming contacts on both surfaces and fire these at least through the ARC/passivation layer.
According to an aspect of the invention, there is provided a method as described above, wherein the semiconductor substrate is one selected from a silicon substrate, a germanium substrate, a silicon carbide substrate and a diamond-like substrate or layer. According to an aspect of the invention, there is provided a method as described above, further comprising creating a second conductivity-type layer on top of one of the first and the second surface, wherein the second conductivity type is opposite to the first conductivity type.
According to an aspect of the invention, there is provided a semiconductor device comprising:
a semiconductor substrate having a first surface and a second surface;
a highly doped layer arranged on at least a portion of the first surface side of the semiconductor substrate;
wherein the highly doped layer on the first or second surface of the semiconductor substrate is formed by an amorphous boron layer; manufactured in accordance with a method as described above.
According to an aspect of the invention, there is provided a semiconductor device as described above wherein the semiconductor device is arranged as a device selected from a group comprising a diode, a photodiode and a solar cell. According to an aspect of the invention, there is provided a semiconductor device as described above wherein the amorphous boron-layer is applied on the first surface to form an p+ emitter of a n-type semiconductor substrate.
Thereto, the amorphous boron-layer is contacted by a front-contact metal with relatively better electrical contact, i.e. provides relatively low contact resistance, and consequently relatively less metal is needed. Thus, the Schottky-contact directly to the semiconductor emitter layer is eliminated, and the efficiency and the reliability of the emitter series resistance are improved.
Moreover, the emitter layer that can be contacted is formed uniformly over the whole front surface and no lithography is needed to place the contacts, for example on the regions that are more highly-doped than others. High doping is normally needed to give low contact resistance.
According to an aspect of the invention, there is provided a semiconductor device as described above wherein the amorphous boron layer is arranged as a passivating or back surface field layer.
Furthermore, a p-n junction is formed at a relatively low temperature between the amorphous boron-layer and a first surface of a semiconductor substrate base layer of the n-type semiconductor substrate. In case the semiconductor device embodies a diode , a photodiode or photovoltaic cell, together with the amorphous boron layer, the p-n junction lowers the saturation current, i.e. dark current, and improves the electric power output of the semiconductor device.
When applying the amorphous boron layer as BSF layer, the processing cost is reduced by combining the back surface field (BSF) layer and the passivation layer as one layer. The production process of the semiconductor device is also simplified.
According to an aspect of the invention, there is provided semiconductor device as described above wherein a shallow boron- semiconductor material mixed layer is arranged in between the amorphous boron-layer and the semiconductor substrate base layer of the semiconductor substrate.
Advantageously, a considerable boron drive into the semiconductor substrate base layer, due to the relatively high boron-concentration gradient at the surface, improves the reproducibility of the semiconductor device. According to an aspect of the invention, there is provided a semiconductor device as described above, wherein the semiconductor substrate is a n-type semiconductor substrate and the amorphous boron layer is arranged as a back surface field layer.
According to an aspect of the invention, there is provided a semiconductor device as described above, wherein the amorphous boron layer is arranged as a p-type emitter. According to an aspect of the invention, there is provided a semiconductor device as described above, wherein a boron-semiconductor material mixed layer is arranged between the emitter layer and the semiconductor substrate layer of the semiconductor device.
According to an aspect of the invention, there is provided a semiconductor device as described above, wherein the semiconductor substrate is a silicon substrate.
According to an alternative aspect of the invention, there is provided a semiconductor device as described above, wherein the semiconductor substrate is one selected from a germanium substrate, a silicon-carbide substrate and a diamond-like substrate or layer. According to an aspect of the invention, there is provided a semiconductor device as described above, wherein the base layer contains one or more buried dot structures, the dot structures being formed from Si, Ge or an III-V compound.
Brief description of the drawings
The invention will be explained in detail with reference to some drawings that are only intended to show embodiments of the invention and not to limit the scope. The scope of the invention is defined in the annexed claims and by its technical equivalents.
The drawings show:
Figure 1 shows a cross-sectional view of a typical structure of a prior art p-type bifacial photovoltaic cell.
Figure 2 shows a cross-sectional view of an embodiment with an amorphous boron- layer arranged to a first surface of a semiconductor substrate of an n-type photovoltaic cell according to the invention.
Figure 3 shows a cross-sectional view of an embodiment with an amorphous boron- layer arranged to a second surface of a semiconductor substrate of a p-type photovoltaic cell according to the invention.
Figure 4 shows a flow diagram of an example of a method for manufacturing a photovoltaic cell according to an embodiment of the invention. Figure 5 shows a flow diagram of an example of a method for manufacturing a photovoltaic cell according to an embodiment of the invention.
Figure 6a shows the IV-characteristics of the photovoltaic cell with relatively high saturation current.
Figure 6b shows the IV-characteristics of the photovoltaic cell with relatively low saturation current.
Figure 7 shows a cross-sectional view of a semiconductor device in accordance with an embodiment of the present invention. Detailed description of embodiments
Below the invention is illustrated by an exemplary embodiment of a photovoltaic cell. It is recognized that the invention also relates to other semiconductor device types in which highly doped p-type ( p+) or passivating layers are located on a semiconductor substrate surface, such as diode, photodiode and photovoltaic cell structures.
In figure 2, an embodiment of the invention with an amorphous boron layer arranged to a first surface of a semiconductor substrate of a n-type photovoltaic cell is shown. A n- type photovoltaic cell 101 comprises a n-type semiconductor substrate base layer 109, with a first surface on top and a second surface on the bottom, for generating photon- generated carriers, an amorphous boron emitter layer 107 arranged on top of the n-type semiconductor substrate base layer 109 for collecting the photon-generated carriers, a front contact 103 connected to the amorphous boron emitter layer 107, a n+ type back surface field (BSF) layer 11 1 arranged on the bottom of the base layer 109, a rear contact 115 connected to the BSF layer 111, an anti-reflection coating (ARC) layer 105 arranged on top of the amorphous boron emitter layer 107 for decreasing the reflection of light from the front side of the n-type photovoltaic cell 101. Further, a passivation layer 113 is arranged on the bottom of the BSF layer 111 for passivating the surface of the photovoltaic cell 101 and reducing the surface recombination in the rear side. The ARC layer 105 may also serve as passivation layer for passivating the surface of the photovoltaic cell 101 and optionally for acting as hydrogen source for bulk passivation.
The passivation layer 113 may also serve as anti-reflection coating layer for decreasing the reflection of light from the rear side of the n-type photovoltaic cell 101. According to an embodiment of the invention, an interface with the function of a p-n junction is formed at relatively low temperature, e.g. below 700°C, or between about 500°C and about 700°C, or between about 350°C and about 450°C, or at about 400°C or even down to about 300°C, between the amorphous boron emitter layer 107 and the first surface of the semiconductor substrate base layer 109.
It is observed that already the presence of the interface between the amorphous boron layer and the n-type semiconductor substrate base layer, i.e., in case of practically no boron doping of the silicon substrate, provides the function of a p-n junction.
Note that, when the temperature is higher than 750°C, the amorphous boron emitter layer 107 may not be formed due to desorption of boron from the substrate surface and/or reaction with the semiconductor material. Also there may be a deeper boron doping profile into the n-type semiconductor substrate base layer 109. The thickness of the amorphous boron emitter layer formed is typically in the nm-range up to about 1 - 10 nm.
The amorphous boron layer and the p-n junction suppress the electron injection from the n-type semiconductor substrate base layer 109, to further separate the electron-hole pairs, and thus lower the saturation current, i.e. dark current, and improve the electric power output of the photovoltaic cell 101.
According to an embodiment of the invention, the interface of the p-n junction is formed in a relatively low temperature, e.g. below 700°C, and is substantially damage- free, i.e. having relatively low defect density.
According to an embodiment of the invention, the front contact 103 and the rear contact 115 may be formed from metallic stacks, such as Aluminum (Al), Silver (Ag), Nickel (Ni), Copper (Cu), or any conductive material compatible with solar technology.
The amorphous boron emitter layer 107 advantageously acts as a diffusion barrier layer between the n-type semiconductor substrate base layer 109 and the front contact 103. The diffusion barrier layer function may prevent a relatively destructive silicidation process made by the front contact metal and the semiconductor material. The silicidation process may increase the emitter contact resistance due to the dopant depletion at the silicide-semiconductor interface. Thus, the direct contact between the amorphous boron emitter layer 107 and the front contact 103 provides a relatively low contact resistance and consequently relatively less metal coverage is needed, which provides more surface area for photon collection. According to an embodiment, the thickness of the amorphous boron emitter layer 107 is about 3 nm, and the amorphous boron emitter layer 107 functions as a tunneling layer.
According to an embodiment of the invention, the n-type semiconductor substrate base layer 109 may further comprise a shallow boron-doped region emitter layer (not shown in figure 2) in between the amorphous boron emitter layer 107 and the semiconductor substrate base layer 109. The shallow boron-doped region emitter layer is formed at a relatively lower temperature than what is normally used to drive-in dopants or to anneal/activate implanted dopants, e.g. below 700°C, or between about 500°C and about 700°C, , or between about 350°C and about 450°C, or at about 400°C or down to about 300°C, when depositing the amorphous boron emitter layer 107 on top of the semiconductor substrate base layer 109.
Moreover, doping of the silicon substrate from the amorphous boron layer is more reliable than doping directly from the gas phase, also for diffusion temperatures above 700°C. For doping temperatures above 700°C which could be achieved by firing or a rapid thermal annealing step (RTA), it is advantageous to first deposit an amorphous boron layer below about 700°C. The high gradient in boron concentration at the silicon surface and the high total amount of boron atoms in the amorphous boron layer provides a relatively more effective p+ doping source. The shallow boron-doped region layer provides a considerable doping of boron to the semiconductor substrate base layer 109 that improves the reproducibility of the emitter doping, due to the relatively high boron-concentration gradient at the surface of the semiconductor substrate base layer 109, i.e. at the interface with the amorphous boron emitter layer 107.
The shallow boron-doped region emitter layer further suppresses the minority carrier (electrons) injection from the n-type semiconductor substrate base layer 109, to further separate the photon-generated electron-hole pairs, and thus improve the efficiency of electric power output. According to the invention, the amorphous boron layer is even more effective in suppressing the minority carrier (electron) injection.
Due to the fact that the shallow boron-doped region emitter layer is covered with the amorphous boron emitter layer 107, the direct Schottky-contact between the shallow boron-doped region emitter layer and the front contacts 103 is eliminated.
According to a preferred embodiment, a doping temperature for driving boron into the n-type semiconductor substrate base layer 109 below about 700°C is selected. Therefore, a controllable thickness of the shallow boron-doped region emitter layer in the n-type semiconductor substrate base layer 109 and a controllable thickness of the amorphous boron emitter layer 107 are formed in the nm-range, e.g. the thickness may be down to less than 1 nm.
According to an embodiment of the invention, a boron-silicon mixed layer may be formed between the amorphous boron emitter layer 107 and the semiconductor substrate base layer 109. The boron- silicon mixed layer may be formed at a relatively low temperature, e.g. below 700°C, or between about 500°C and about 700°C, or between about 350°C and about 450°C, or at about 400°C or down to about 300°C, when depositing the amorphous boron emitter layer 107 on top of the semiconductor substrate base layer 109.
According to an embodiment of the invention, the n-type semiconductor substrate base layer 109 may further comprise a blanket layer (not shown in figure 2). The blanket layer may comprise a plurality of buried dots, that may be quantum dots, of other material than the semiconductor material of the substrate, e.g. Germanium (Ge) or some types of III- V compounds. The dots may be buried below an epitaxial layer of the same material as the substrate on which the amorphous boron layer is to be deposited. As known to the skilled in the art, the quantum dots may be located alternatively below an epitaxial layer on the surface opposing the surface where the amorphous boron layer is located.
The quantum dots may increase the efficiency of the photovoltaic cell 101 for absorbing energy from light sources with relatively high wavelength, e.g. using Germanium (Ge) for Infrared (IR) light, or from light sources with relatively low wavelength, e.g. using Gallium arsenide (GaAs) for Ultraviolet (UV) light. The blanket layer is formed at a relatively low temperature, e.g. below 700°C.
Note that the dots are not stable above about 700°C as their material will intermix with the semiconductor material in the n-type semiconductor substrate base layer 109 at such a high temperature.
According to an embodiment of the invention, the semiconductor substrate base layer 109 is a silicon substrate base layer. In an alternative embodiment of the invention, the semiconductor substrate base layer 109 is a germanium substrate base layer.
In figure 3, an embodiment of the invention with an amorphous boron layer arranged to a second surface of a p-type semiconductor substrate of a photovoltaic cell is shown. A photovoltaic cell 201 comprises a p-type semiconductor substrate base layer 209, with a first surface on top and a second surface on the bottom, for generating photon- generated carriers, an amorphous boron layer 211 arranged on the bottom of the p-type semiconductor substrate base layer 209, for providing an effective p++-doping for the p-type semiconductor substrate base layer 209 , a n-type emitter layer 207 arranged on top of the p-type semiconductor substrate base layer 209 for collecting the photon- generated carriers, a front contact 203 connected to the n-type emitter layer 207, a rear contact 215 connected to the amorphous boron layer 211, an anti-reflection coating (ARC) layer 205 arranged on top of the emitter layer 207 for decreasing the reflection of light from the photovoltaic cell 201. Additionally, the ARC layer may serve as a passivation layer for passivating the surface of the photovoltaic cell 201 and reducing the surface recombination at the front side.
Note that the amorphous boron layer 211 may serve also as a passivation layer for passivating the surface of the photovoltaic cell 201 and reducing the surface
recombination.
According to an embodiment of the invention, the back surface field (BSF) layer and passivation layer of the photovoltaic cell are implemented as one single amorphous boron layer 211, since the amorphous boron has passivating properties and provides a relatively more effective p+-doping to the p-type semiconductor substrate base layer 209.
According to an embodiment of the invention, an effective p++ layer (not shown in figure 3) is formed at relatively low temperature, e.g. below 700°C, or between about 500°C and about 700°C, , or between about 350°C and about 450°C, or at about 400°C or down to about 300°C, between the amorphous boron layer 211, i.e. p++-doping layer, and the second surface of the p-type semiconductor substrate base layer 209. This is due to the fact that, when the temperature is higher than 750°C, the amorphous boron layer 211 may not be formed and all the boron therein may be doped to the p-type semiconductor substrate base layer 209 due to desorption from the surface and boron reaction with silicon. There will also be a deeper boron doping of the n-type
semiconductor substrate base layer 209.
According to an embodiment of the invention, the interface of the amorphous boron layer 211 and the base layer 209 is formed at a relatively low temperature, e.g. below 700°C, and is substantially damage-free, i.e. with relatively low defect density. The lower the formation temperature, the lower the thermally induced effects on other layers will be.
According to an embodiment of the invention, the p-type semiconductor substrate base layer 209 further comprises a shallow boron-doped region in between the amorphous boron layer 211 and the p-type semiconductor substrate base layer 209.
According to an embodiment of the invention, the p-type semiconductor substrate base layer 209 may further comprise a shallow boron-doped region layer (not shown in figure 3) in between the amorphous boron layer 211 and the p-type semiconductor substrate base layer 209. The shallow boron-doped region layer is formed at a relatively lower temperature than what is normally used to drive-in dopants or to anneal/activate implanted dopants, e.g. below 700°C, or between about 500°C and about 700°C, or between about 350°C and about 450°C, or at about 400°C or down to about 300°C. This is due to the fact that, when the temperature is higher than 750°C, the amorphous boron layer 211 may not be formed due to desorption from the surface and boron reaction with the Si. There will also be a deeper boron doping of the n-type
semiconductor substrate base layer 209.
Moreover, the doping temperature below 700°C is more reliable than the doping temperature above 700°C, due to the existence of the amorphous boron layer 211, which provides a relatively more effective p+ doping region.
The deposition of the amorphous boron layer produces an effective p++-doping of the surface of the semiconductor substrate base layer 209, wherein the reproducibility is improved, due to the relatively high boron-concentration gradient at the surface of the semiconductor substrate base layer 209.
The shallow boron-doped region layer further suppresses the electron injection from the p-type semiconductor substrate base layer 209, to further separate the photon-generated carrier electron-hole pairs, and thus improve the efficiency of the electric power output. According to a preferred embodiment, a doping temperature for driving boron into the silicon below about 700°C is selected. Therefore, the thickness of the shallow boron- doped region layer in the p-type semiconductor substrate base layer 209 is formed in a controllable nm-range, and consequently a thickness of the amorphous boron layer 211 is created in the range of a few nm below about 10 nm, e.g. the thickness may be down to less than 1 nm. According to an embodiment of the invention, a boron-silicon mixed layer can be formed between the amorphous boron layer 211 and the p-type semiconductor substrate base layer 209. The boron-silicon mixed layer is formed at a relatively low temperature, e.g. below 700°C, or between about 500°C and about 700°C, or down to about 300°C. According to an embodiment of the invention, the p-type semiconductor substrate base layer 209 may further comprise a blanket layer (not shown in figure 3). The blanket layer may comprise a plurality of buried dots, that can be quantum dots, of other material that the semiconductor substrate, e.g. Germanium (Ge) or some type of III-V compounds. The dots may be buried below an epitaxial layer of the same material as the substrate on which the amorphous boron layer is to be deposited, or alternatively below an epitaxial layer on the surface opposing the surface where the amorphous boron layer is located.. The dots may increase the efficiency of the photovoltaic cell 201 for absorbing energy from light sources with relatively high wavelength, e.g. using Germanium (Ge) for Infrared (IR) light, or from light sources with relatively low wavelength, e.g. using Gallium arsenide (GaAs) for Ultraviolet (UV) light. The blanket layer is formed at a relatively low temperature, e.g. below 700°C. This is due to the fact that the quantum dots are not stable above about 700°C as their material will intermix with the semiconductor materials in the p-type semiconductor substrate base layer 209 at a relatively high temperature.
According to an embodiment of the invention, the semiconductor substrate base layer 209 is a silicon substrate base layer. In an alternative embodiment of the invention, the semiconductor substrate base layer 209 is a germanium substrate base layer.
In Figure 4, a flow diagram of an example of a method for manufacturing a
photovoltaic cell according to an embodiment as depicted in figure 3 is shown.
First, in action 301, a semiconductor substrate is provided. In an embodiment, the semiconductor substrate is a silicon (Si) substrate. In an alternative embodiment, the semiconductor substrate is a germanium (Ge) substrate. The semiconductor substrate has a first surface and a second surface opposite thereto. For instance, a boron doped textured silicon wafer is provided.
Subsequently, in action 303, a n-type emitter surface is deposited and/or diffused on top of the first surface of the semiconductor substrate. For instance, this action can be done by depositing a POy layer and drive-in by high-temperature diffusion of the
phosphorous to ensure surface doping. The POy layer may be a phosphor glass formed from a gas containing POC13 or from sprayed H3P04, which is well known for the skilled person.
Subsequently, in action 304, the POy layer on at least the first surface is removed by etching.
Subsequently, in action 305, the native oxide or POy layer on the second surface is removed. For instance, this action can be done by wet chemical etching using e.g. HF etchant.
Subsequently, in action 307, a layer of amorphous boron is deposited/formed on top of the second surface in such a way that in the semiconductor substrate a layer of amorphous boron is formed and some boron is diffused into the substrate. The amorphous boron is deposited/formed at temperatures below about 700°C. An effective p+-doping of the c-Si has been demonstrated at temperatures down to 300°C, but lower temperatures should also be possible. Most experiments have been done at 500°C to 700°C. The amorphous boron layer can be deposited on a silicon surface (in a process chamber) by using a silicon substrate and a boron precursor with either:
• an oxygen- free silicon surface and an oxygen- free gas environment by
supplying a relatively low concentration of boron-containing gas of about 1 - 50 ppm; or
• a silicon surface with a thin silicon-dioxide layer and an oxygen- free gas
environment by supplying a relatively high concentration of boron-containing gas (the supply gas being e.g. 2% B2H6 in argon or nitrogen) at a level of above about 100 ppm. When using high concentration, a thick layer of amorphous boron is deposited and can be used to thermally drive-in boron.
It is noted that CVD processes may have a wide window of operation in which a layer can be deposited. In an embodiment, the CVD process is an atmospheric process (760 Torr). Alternatively, the CVD process may be run at reduced pressure (e.g., 60 or 30 Torr, or even about 10 Torr), or in a range between about 10 (13 hPa) to about 760 Torr (1010 hPa).
It is noted that as will be appreciated by the skilled person, in a preferred setting of the CVD process, the growth rate of the amorphous boron layer is controlled by transport (i.e., depletion) of boron-containing reactant in the gas phase. Further, the CVD process may be an ALD (atomic layer deposition) process, or a PECVD (Plasma Enhanced CVD) or ICP-CVD (Inductive coupled plasma CVD), or an ultra high vacuum (UHV) CVD process.
In case of UHV CVD the pressure range will be typically between 10~6 and about 10"11 Torr.
In an embodiment, the amorphous boron layer is formed by chemical vapor deposition from a boron precursor gas mixture which comprises di-borane, and an inert gas.
The inert gas may be nitrogen or argon.
In an embodiment, the amount of inert gas in the gas mixture is at least about 90 vol%. Additionally or alternatively, the gas mixture contains about 5 vol% of di-borane or less.
Moreover, the deposition of the amorphous boron layer may be performed by evaporation. Additionally, the fabrication of the amorphous boron layer may be done in a single semiconductor substrate process or a batch process for a plurality of semiconductor substrates.
Subsequently, in action 309, the first surface of the semiconductor substrate is covered by an ARC/passivation layer. For instance, this action can be done by depositing Si x:H using Plasma-enhanced chemical vapor deposition (PECVD).
Finally, in action 311, the contacts on both surfaces of the semiconductor substrate are formed and/or annealed (heat-treated) at least through the ARC/passivation layer on both surfaces. For instance, this action can be done by screen printing contacts and firing these through a SiNx:H layer.
It is noted that after formation of the amorphous boron layer, the manufacturing process may comprise a formation of a nitride layer by ramping the process temperature up to about 900 °C in a nitrogen ambient substantially free of di-borane. After formation of the amorphous boron layer, the inflow of the di-borane containing gas mixture is stopped and preferably purged by inflow of nitrogen gas.
In an embodiment, during this nitridation process a portion of the amorphous boron layer is being diffused into the semiconductor substrate surface.
In figure 5, a flow diagram of an example of a method for manufacturing a photovoltaic cell according to the embodiment as depicted in figure 2 is shown. First, in action 401, a substrate is provided. The substrate has a first surface and a second surface opposite thereto. For instance, this action can be done by manufacturing a phosphorous doped textured silicon wafer.
Subsequently, in action 403, a n++-doped back surface field is deposited and/or diffused on top of the second surface of the semiconductor substrate. For instance, this action can be done by depositing a POy layer and drive-in by high-temperature diffusion of the phosphorous to ensure surface doping.
Subsequently, in action 404, the POy layer on the at least the second surface is removed by etching.
Subsequently, in action 405, native oxide on the first surface is removed. For instance, this action can be done by wet chemical etching using e.g. HF etchant.
Subsequently, in action 407, a layer of amorphous boron is deposited/formed on top of the first surface of the silicon substrate in such a way that in said silicon substrate is effectively p+-doped. The amorphous boron is deposited at temperatures below about 700°C. Especially for the higher temperatures in this temperature range, a considerable doping of the c-Si is achieved (up to solid solubility, but in all cases/temperatures a layer that emits holes (effective p+-doping) is formed). In a process chamber, the amorphous boron layer can be deposited on a silicon surface by using a silicon substrate with either:
· an oxygen- free silicon surface and an oxygen free gas environment by
supplying a relatively low concentration of boron-containing gas (e.g. at a concentration between 1 - 50 ppm); or
• a silicon surface with a thin silicon dioxide layer and an oxygen- free gas
environment by supplying a relatively high concentration of boron-containing gas (the supply gas being e.g. 2% B2H6 in argon or nitrogen) at a level of above about 100 ppm. .
In an embodiment, the amorphous boron layer is formed by chemical vapor deposition from a boron precursor gas mixture comprising di-borane and an inert gas. The inert gas may be nitrogen or argon. In an embodiment, the amount of inert gas in the gas mixture is at least about 90 vol%. Additionally or alternatively, the gas mixture contains about 5 vol% of di-borane or less. Subsequently, in action 409, the first surface of the semiconductor substrate is covered by an ARC/passivation layer. For instance, this action can be done by depositing Si x:H or AlOx by Plasma-enhanced chemical vapor deposition (PECVD).
Subsequently, in action 410, the second surface of the semiconductor substrate is coated with an ARC/passivation layer , e.g. depositing SiNx:H by PECVD.
Finally, in action 411, the contacts on both surfaces of the semiconductor substrate are formed and/or annealed (heat-treated) at least through the ARC/passivation layer on both the first and second surfaces of the semiconductor substrate (preferably not through the amorphous boron layer). For instance, this action can be done by screen printing contacts and annealing these through a SiNx:H layer on both the front side and the rear side of the photovoltaic cell.
It is noted that the amorphous boron layer may be deposited when applying a masking technique on a semiconductor surface to create a patterned amorphous boron layer on that semiconductor surface. In an embodiment, this allows to create p++ areas of amorphous boron on the second surface.
It is to be understood that the embodiments of the invention described hereinabove only show specific process flows and device structures. However, the amorphous boron layer may be used at different instances in the production process and may be applicable to other cell designs than addressed in this description.
In figure 6a, the I-V (current- voltage) characteristics of a photovoltaic cell with a Schottky junction, or the I-V characteristics of a photovoltaic cell with a leaky pn- junction, or one with relatively high saturation current, is shown. In figure 6b, the I-V characteristics of a photovoltaic cell with a p-n junction, i.e. one with relatively low saturation current, is shown. In both figure 6a and 6b, the x-axis shows the current value of the photovoltaic cell and the y-axis shows the voltage value of the photovoltaic cell. The I-V curve with a solid line shows the current- voltage relationship when the photovoltaic cell is in the illuminated status. The I-V curve with the dashed line shows the current-voltage relationship when the photovoltaic cell is in the dark status. The size of the shadowed rectangle area indicates the maximum output power value of the photovoltaic cell. When comparing figure 6a with figure 6b, it is observed that the I-V curve with the dashed line shifts slightly from the left direction to the right direction. It implies that, in the dark status of photovoltaic cell, additional voltage source of the forward bias is needed in order to generate current. Moreover, it is observed that the size of the shadowed rectangle area depicted in figure 6b is greater than figure 6a. It implies that, in the illuminated status of photovoltaic cell, under the condition of the same current, the photovoltaic cell with p-n junction has much higher voltages than the photovoltaic cell with Schottky contact, and thus generates more power. It also implies that the advantage of the boron layer by forming an effective p-n junction is of its low leakage and suppression of the surface recombination.
Figure 7 shows a cross-sectional view of a semiconductor device in accordance with an embodiment of the present invention.
A n-type semiconductor device 701 comprises a n-type semiconductor substrate base layer 709, with a first surface on top and a second surface on the bottom, an amorphous boron emitter layer 707 arranged on top of the n-type semiconductor substrate base layer 709, a front contact 703 connected to the amorphous boron emitter layer 707, a n+ type back surface field (BSF) layer711 arranged on the bottom of the base layer 709, a rear contact 715 connected to the BSF layer 711.
Further, a passivation layer 713 may be arranged on the bottom of the BSF layer 711 for passivating the surface of the semiconductor device and reducing the surface recombination in the rear side.
The method of the present invention can be run in various CVD reactor systems depending on the type of CVD process.
In a preferred embodiment, the boron deposition process is carried out in a LPCVD reactor that can maintain a process pressure between about 10 - 760 Torr. Such a LPCVD reactor is capable of loading substrates at low temperature, and at low pressure to degas the substrates and also keep the exposed silicon surfaces free from formation of native oxides, while at later stage the pressure can be increased to enhance the deposition rate of the amorphous boron layer on the semiconductor substrate.
It is to be understood that the invention which is described above with reference to a number of embodiments, is only limited by the annexed claims and its technical equivalents. In this document and in its claims, the verb "to comprise" and its conjugations are used in their non-limiting sense to mean that items following the word are included, without excluding items not specifically mentioned. In addition, reference to an element by the indefinite article "a" or "an" does not exclude the possibility that more than one of the element is present, unless the context clearly requires that there be one and only one of the elements. The indefinite article "a" or "an" thus usually means "at least one".

Claims

Claims
1. A method for manufacturing a semiconductor device, comprising:
providing a first conductivity-type bulk doped semiconductor substrate with a first surface and a second surface opposite thereto;
removing the native oxide on at least a portion of at least one of the first and the second surface to expose the semiconductor material;
by chemical vapor deposition using a boron precursor gas forming a layer of amorphous boron on top of the exposed semiconductor material such that an effective p++ type layer is formed.
2. Method according to claim 1, wherein the amorphous boron layer is formed by chemical vapor deposition from the boron precursor gas mixture comprising di-borane, and an inert gas.
3. Method according to claim 2, wherein the inert gas is selected from nitrogen and argon.
4. Method according to claim 2 or 3, wherein the amount of inert gas in the gas mixture is at least about 90 vol%.
5. Method according to any one of claims 2 - 4, wherein the gas mixture contains about 5 vol% of di-borane or less.
6. Method according to any one of the preceding claims 2 - 5, wherein the chemical vapor deposition process is one selected from a chemical vapor deposition process, a plasma enhanced, PE, CVD process, an atomic layer deposition, ALD, process, an ultra-high-vacuum, UHV, CVD process and an inductive coupled plasma, ICP, CVD process.
7. Method according to any one of claims 2 - 6, wherein the chemical vapor deposition process is a process at substantially atmospheric pressure.
8. Method according to any one of claims 2 - 5, wherein the chemical vapor deposition process is a process at a reduced pressure between about 10 and about 760 Torr [about 10 - 1010 hPa)].
9. Method according to any one of claims 2 - 8, wherein the deposition process temperature is at least 300°C.
10. Method according to any one of claims 2 - 8, wherein the deposition process temperature is between about 350 and about 450°C.
11. Method according to any one of claims 2 - 8, wherein the deposition process temperature is about 400°C.
12. Method according to any of the preceding claims 1 - 11, wherein the formed boron layer is a conformal layer.
13. Method according to claim 8, further comprising:
- after forming the amorphous boron layer, exposing the semiconductor device to a nitrogen ambient, substantially free of di-borane, and
- ramping the process temperature to a high temperature between about 700 and about 900 °C.
14. Method according to any one of preceding claims 1 - 13, further comprising: covering the first surface by an ARC/passivation layer;
forming contacts on both first and second surfaces and fire the contacts, in such a way that the contacts on the first surface extends at least through the ARC/passivation layer.
15. Method according to any one of preceding claims 1 - 13, wherein the
semiconductor substrate is one selected from a silicon substrate, a germanium substrate, a silicon carbide substrate and a diamond-like substrate or layer.
16. Method according to any one of the preceding claims further comprising creating a second conductivity-type layer on top of one of the first and the second surface, wherein the second conductivity type is opposite to the first conductivity type.
17. A semiconductor device comprising:
a semiconductor substrate having a first surface and a second surface;
a highly doped layer on at least a portion of at least one of the first and second surface, wherein the highly doped layer on the first or second surface of the semiconductor substrate is formed by an amorphous boron layer; manufactured in accordance with a method according to any one of the claims 1 - 16.
18. Semiconductor device according to claim 17, wherein the semiconductor device is arranged as a device selected from a group comprising a diode, a photodiode and a solar cell.
19. Semiconductor device according to claim 17 or 18, wherein the amorphous boron layer is arranged as a passivating or back surface field layer.
20. Semiconductor device according to claim 17 or 18, wherein the amorphous boron layer is arranged as p+ emitter on n-type semiconductor substrate.
21. Semiconductor device according to claim 20, further comprising:
an anti-reflection coating (ARC) layer arranged on top of the p+ emitter layer.
22. Semiconductor device according to any one of claims 17 - 21, wherein a boron- semiconductor material mixed layer is arranged between the amorphous boron layer and the semiconductor substrate.
23. Semiconductor device according to any one of the preceding claims 17 - 22, wherein the semiconductor substrate is one selected from a silicon substrate, a germanium substrate, a silicon-carbide substrate and a diamond-like substrate or layer.
24. Semiconductor device according to any one of the preceding claims 17 - 23, wherein the semiconductor device contains one or more buried dot structures, that can be quantum dots, the dot structures being formed from Si, Ge, Si-Ge or an III-V compound.
PCT/NL2011/050786 2010-11-19 2011-11-17 Method for producing a semiconductor device and a semiconductor device WO2012067509A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
NL2005730 2010-11-19
NL2005730A NL2005730C2 (en) 2010-11-19 2010-11-19 Photovoltaic cell and a method for producing such a photovoltaic cell.

Publications (1)

Publication Number Publication Date
WO2012067509A1 true WO2012067509A1 (en) 2012-05-24

Family

ID=44121505

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/NL2011/050786 WO2012067509A1 (en) 2010-11-19 2011-11-17 Method for producing a semiconductor device and a semiconductor device

Country Status (3)

Country Link
NL (1) NL2005730C2 (en)
TW (1) TW201222639A (en)
WO (1) WO2012067509A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20140110177A (en) * 2013-03-05 2014-09-17 엘지전자 주식회사 Bifacial solar cell
WO2014191492A1 (en) * 2013-05-29 2014-12-04 Robert Bosch Gmbh Method for producing a solar cell

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101813123B1 (en) * 2016-08-24 2017-12-29 주성엔지니어링(주) Solar cell and Method of manufacturing the same

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03141636A (en) * 1990-08-06 1991-06-17 Plasma Physics Corp Semiconductor device
JPH03166772A (en) * 1989-11-25 1991-07-18 Fuji Electric Corp Res & Dev Ltd Manufacture of thin film solar cell
AU749022B2 (en) * 1998-06-29 2002-06-13 Unisearch Limited A self aligning method for forming a selective emitter and metallization in a solar cell
US20040045598A1 (en) * 2002-09-06 2004-03-11 The Boeing Company Multi-junction photovoltaic cell having buffer layers for the growth of single crystal boron compounds
US20050189015A1 (en) * 2003-10-30 2005-09-01 Ajeet Rohatgi Silicon solar cells and methods of fabrication

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03155680A (en) * 1989-08-25 1991-07-03 Fuji Electric Corp Res & Dev Ltd Manufacture of thin film solar cell

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03166772A (en) * 1989-11-25 1991-07-18 Fuji Electric Corp Res & Dev Ltd Manufacture of thin film solar cell
JPH03141636A (en) * 1990-08-06 1991-06-17 Plasma Physics Corp Semiconductor device
AU749022B2 (en) * 1998-06-29 2002-06-13 Unisearch Limited A self aligning method for forming a selective emitter and metallization in a solar cell
US20040045598A1 (en) * 2002-09-06 2004-03-11 The Boeing Company Multi-junction photovoltaic cell having buffer layers for the growth of single crystal boron compounds
US20050189015A1 (en) * 2003-10-30 2005-09-01 Ajeet Rohatgi Silicon solar cells and methods of fabrication

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
NANVER L K ET AL: "Pure-boron chemical-vapor-deposited layers: A new material for silicon device processing", 2010 18TH IEEE INTERNATIONAL CONFERENCE ON ADVANCED THERMAL PROCESSING OF SEMICONDUCTORS (RTP 2010) IEEE PISCATAWAY, NJ, USA, 28 September 2010 (2010-09-28) - 1 October 2010 (2010-10-01), pages 136 - 139, XP002642158, ISBN: 978-1-4244-8400-3 *
SARUBBI F ET AL: "Chemical Vapor Deposition of [alpha]-Boron Layers on Silicon for Controlled Nanometer-Deep p<+>n Junction Formation", JOURNAL OF ELECTRONIC MATERIALS TMS USA, vol. 39, no. 2, 11 December 2009 (2009-12-11), pages 162 - 173, XP002642159, ISSN: 0361-5235 *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20140110177A (en) * 2013-03-05 2014-09-17 엘지전자 주식회사 Bifacial solar cell
KR101983361B1 (en) * 2013-03-05 2019-05-28 엘지전자 주식회사 Bifacial solar cell
WO2014191492A1 (en) * 2013-05-29 2014-12-04 Robert Bosch Gmbh Method for producing a solar cell

Also Published As

Publication number Publication date
NL2005730C2 (en) 2012-05-22
TW201222639A (en) 2012-06-01

Similar Documents

Publication Publication Date Title
US20230197877A1 (en) Solar cell having an emitter region with wide bandgap semiconductor material
US8872020B2 (en) Heterojunction solar cell based on epitaxial crystalline-silicon thin film on metallurgical silicon substrate design
JP5885238B2 (en) Optoelectronic device having a heterojunction
US8686283B2 (en) Solar cell with oxide tunneling junctions
US9634160B2 (en) Solar cell and method for manufacturing the same
US20140102524A1 (en) Novel electron collectors for silicon photovoltaic cells
US8124502B2 (en) Semiconductor device manufacturing method, semiconductor device and semiconductor device manufacturing installation
JP2008021993A (en) Photovoltaic device including all-back-contact configuration, and related method
US20230275167A1 (en) Solar cell, method for preparing the same, and photovoltaic module
KR20150097613A (en) Solar cell with silicon oxynitride dielectric layer
US20140096817A1 (en) Novel hole collectors for silicon photovoltaic cells
CN110943143A (en) Method for manufacturing a photovoltaic solar cell with heterojunction and emitter diffusion regions
Bultman et al. Methods of emitter formation for crystalline silicon solar cells
KR20110086833A (en) Semiconductor device manufacturing method, semiconductor device and semiconductor device manufacturing installation
US20120048376A1 (en) Silicon-based photovoltaic device produced by essentially electrical means
US20100230771A1 (en) Methods and arrangement for diffusing dopants into silicon
NL2005730C2 (en) Photovoltaic cell and a method for producing such a photovoltaic cell.
EP2993699B1 (en) Method for fabricating crystalline photovoltaic cells
WO2021246865A1 (en) Methodology for efficient hole transport layer using transition metal oxides
KR101129422B1 (en) Fabrication method of solar cell and solar cell fabrication by the same
KR20140061576A (en) Thin film type solar cell, method for manufacturing the same and method for manufacturing optical absorber layer for thin film type solar cell
EP2180531A1 (en) Semiconductor device manufacturing method, semiconductor device and semiconductor device manufacturing installation
KR20120122022A (en) Method for Fabricating Solar Cell
KR20160005569A (en) Method for manufacturing solar cell

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 11788607

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 11788607

Country of ref document: EP

Kind code of ref document: A1