WO2009066500A1 - 半導体装置のコンフィギュレーション方法 - Google Patents

半導体装置のコンフィギュレーション方法 Download PDF

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Publication number
WO2009066500A1
WO2009066500A1 PCT/JP2008/066216 JP2008066216W WO2009066500A1 WO 2009066500 A1 WO2009066500 A1 WO 2009066500A1 JP 2008066216 W JP2008066216 W JP 2008066216W WO 2009066500 A1 WO2009066500 A1 WO 2009066500A1
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WO
WIPO (PCT)
Prior art keywords
variable resistance
terminal variable
semiconductor device
device configuration
resistance switching
Prior art date
Application number
PCT/JP2008/066216
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English (en)
French (fr)
Inventor
Shogo Nakaya
Original Assignee
Nec Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corporation filed Critical Nec Corporation
Priority to JP2009542496A priority Critical patent/JP5212378B2/ja
Priority to US12/742,018 priority patent/US8189365B2/en
Publication of WO2009066500A1 publication Critical patent/WO2009066500A1/ja

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/101—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including resistors or capacitors only
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0009—RRAM elements whose operation depends upon chemical change
    • G11C13/0011—RRAM elements whose operation depends upon chemical change comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/003—Cell access
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G11C2013/009—Write using potential difference applied between cell electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/10—Resistive cells; Technology aspects
    • G11C2213/17—Memory cell being a nanowire transistor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/50—Resistive cell structure aspects
    • G11C2213/53—Structure wherein the resistive material being in a transistor, e.g. gate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/75—Array having a NAND structure comprising, for example, memory cells in series or memory elements in series, a memory element being a memory cell in parallel with an access transistor

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Theoretical Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Logic Circuits (AREA)

Abstract

ソース電極、ドレイン電極及びゲート電極を有する複数の３端子可変抵抗スイッチ素子が互いに直列接続され、３端子可変抵抗スイッチ素子のソース電極と３端子可変抵抗スイッチ素子に隣接する３端子可変抵抗素子のドレイン電極とが配線セグメントを介して互いに接続されたレーンを有し、配線セグメントに所定の電位を保持する電位保持部が接続され、各レーンの中のそれぞれ１つの３端子可変抵抗スイッチ素子から列グループが構成され、列グループに属する３端子可変抵抗スイッチ素子のゲート電極それぞれに共通のゲート線が接続される。
PCT/JP2008/066216 2007-11-21 2008-09-09 半導体装置のコンフィギュレーション方法 WO2009066500A1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2009542496A JP5212378B2 (ja) 2007-11-21 2008-09-09 半導体装置のコンフィギュレーション方法
US12/742,018 US8189365B2 (en) 2007-11-21 2008-09-09 Semiconductor device configuration method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-301480 2007-11-21
JP2007301480 2007-11-21

Publications (1)

Publication Number Publication Date
WO2009066500A1 true WO2009066500A1 (ja) 2009-05-28

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US (1) US8189365B2 (ja)
JP (1) JP5212378B2 (ja)
WO (1) WO2009066500A1 (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5858036B2 (ja) * 2011-03-02 2016-02-10 日本電気株式会社 再構成可能回路
US9543957B2 (en) 2013-07-24 2017-01-10 Kabushiki Kaisha Toshiba Reconfigurable logic circuit device

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012147315A1 (ja) * 2011-04-25 2012-11-01 パナソニック株式会社 抵抗変化型不揮発性記憶装置およびその駆動方法
US9082494B2 (en) 2012-01-13 2015-07-14 Micron Technology, Inc. Memory cells having a common gate terminal
US8737114B2 (en) * 2012-05-07 2014-05-27 Micron Technology, Inc. Switching device structures and methods
CN106575703B (zh) * 2014-06-26 2019-12-17 英特尔公司 基于氧化物的三端子电阻式开关逻辑器件
US10553532B2 (en) 2014-12-24 2020-02-04 Intel Corporation Structure and method to self align via to top and bottom of tight pitch metal interconnect layers

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001525606A (ja) * 1997-12-04 2001-12-11 アクソン テクノロジーズ コーポレイション プログラム可能なサブサーフェス集合メタライゼーション構造およびその作製方法
WO2003094227A1 (en) * 2002-04-30 2003-11-13 Japan Science And Technology Agency Solid electrolyte switching device, fpga using same, memory device, and method for manufacturing solid electrolyte switching device
WO2006070683A1 (ja) * 2004-12-28 2006-07-06 Nec Corporation スイッチング素子、スイッチング素子の製造方法、書き換え可能な論理集積回路、およびメモリ素子
WO2007063655A1 (ja) * 2005-11-29 2007-06-07 Nec Corporation プログラム回路、半導体集積回路、電圧印加方法、電流印加方法および比較方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3496661B2 (ja) 2000-06-15 2004-02-16 日本電気株式会社 データパスに適したプログラマブル相互接続網を有する再構成可能デバイス
JP2004158119A (ja) * 2002-11-06 2004-06-03 Sharp Corp 不揮発性半導体記憶装置
US7606059B2 (en) * 2003-03-18 2009-10-20 Kabushiki Kaisha Toshiba Three-dimensional programmable resistance memory device with a read/write circuit stacked under a memory cell array
JP4356542B2 (ja) 2003-08-27 2009-11-04 日本電気株式会社 半導体装置
US7492635B2 (en) * 2005-01-06 2009-02-17 Samsung Electronics Co., Ltd. NOR-type hybrid multi-bit non-volatile memory device and method of operating the same
KR100657958B1 (ko) 2005-04-13 2006-12-14 삼성전자주식회사 직렬 연결 구조의 저항 노드들을 갖는 메모리 소자
JP4313372B2 (ja) * 2005-05-11 2009-08-12 シャープ株式会社 不揮発性半導体記憶装置
JP4594878B2 (ja) 2006-02-23 2010-12-08 シャープ株式会社 可変抵抗素子の抵抗制御方法及び不揮発性半導体記憶装置
WO2007145295A1 (ja) * 2006-06-16 2007-12-21 Panasonic Corporation 不揮発性メモリ装置
US7778063B2 (en) * 2006-11-08 2010-08-17 Symetrix Corporation Non-volatile resistance switching memories and methods of making same
JP4496238B2 (ja) * 2007-06-04 2010-07-07 株式会社東芝 不揮発性メモリ装置
WO2009001534A1 (ja) * 2007-06-22 2008-12-31 Panasonic Corporation 抵抗変化型不揮発性記憶装置
JP2009026382A (ja) * 2007-07-19 2009-02-05 Hitachi Ltd 半導体記憶装置
JP5214208B2 (ja) * 2007-10-01 2013-06-19 スパンション エルエルシー 半導体装置及びその制御方法
JP2010055719A (ja) * 2008-08-29 2010-03-11 Toshiba Corp 抵抗変化メモリ装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001525606A (ja) * 1997-12-04 2001-12-11 アクソン テクノロジーズ コーポレイション プログラム可能なサブサーフェス集合メタライゼーション構造およびその作製方法
WO2003094227A1 (en) * 2002-04-30 2003-11-13 Japan Science And Technology Agency Solid electrolyte switching device, fpga using same, memory device, and method for manufacturing solid electrolyte switching device
WO2006070683A1 (ja) * 2004-12-28 2006-07-06 Nec Corporation スイッチング素子、スイッチング素子の製造方法、書き換え可能な論理集積回路、およびメモリ素子
WO2007063655A1 (ja) * 2005-11-29 2007-06-07 Nec Corporation プログラム回路、半導体集積回路、電圧印加方法、電流印加方法および比較方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5858036B2 (ja) * 2011-03-02 2016-02-10 日本電気株式会社 再構成可能回路
US9299424B2 (en) 2011-03-02 2016-03-29 Nec Corporation Reconfigurable circuit and method for refreshing reconfigurable circuit
US9543957B2 (en) 2013-07-24 2017-01-10 Kabushiki Kaisha Toshiba Reconfigurable logic circuit device

Also Published As

Publication number Publication date
US20100246240A1 (en) 2010-09-30
US8189365B2 (en) 2012-05-29
JP5212378B2 (ja) 2013-06-19
JPWO2009066500A1 (ja) 2011-04-07

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