WO2009034603A1 - 半導体メモリ - Google Patents

半導体メモリ Download PDF

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Publication number
WO2009034603A1
WO2009034603A1 PCT/JP2007/001007 JP2007001007W WO2009034603A1 WO 2009034603 A1 WO2009034603 A1 WO 2009034603A1 JP 2007001007 W JP2007001007 W JP 2007001007W WO 2009034603 A1 WO2009034603 A1 WO 2009034603A1
Authority
WO
WIPO (PCT)
Prior art keywords
read
voltage
regular
capacitor
logic level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2007/001007
Other languages
English (en)
French (fr)
Inventor
Isao Fukushi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Semiconductor Ltd filed Critical Fujitsu Semiconductor Ltd
Priority to KR1020107004403A priority Critical patent/KR101139163B1/ko
Priority to PCT/JP2007/001007 priority patent/WO2009034603A1/ja
Priority to JP2009531987A priority patent/JP5035348B2/ja
Publication of WO2009034603A1 publication Critical patent/WO2009034603A1/ja
Priority to US12/696,580 priority patent/US8213253B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)

Abstract

　レギュラーキャパシタは、高論理レベルを保持するレギュラーメモリセルの電荷により飽和され、低論理レベルを保持するレギュラーメモリセルからの電荷では飽和されない。リファレンスキャパシタは、高論理レベルを保持するリファレンスメモリセルからの電荷により飽和される。差動センスアンプは、レギュラーキャパシタから読み出されるレギュラー読み出し電圧と、リファレンスキャパシタから読み出される飽和電圧であるリファレンス読み出し電圧より第１電圧だけ低い電圧との差を差動増幅し、メモリセルに保持されていたデータの論理を生成する。メモリセルのキャパシタの特性がばらつく場合にも、リファレンス電圧および高論理レベルに対応する読み出し電圧のばらつきを小さくできる。これにより、リファレンス電圧と低論理レベルに対応する読み出し電圧との差を相対的に大きくできる。この結果、読み出しマージンを向上できる。
PCT/JP2007/001007 2007-09-14 2007-09-14 半導体メモリ Ceased WO2009034603A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1020107004403A KR101139163B1 (ko) 2007-09-14 2007-09-14 반도체 메모리
PCT/JP2007/001007 WO2009034603A1 (ja) 2007-09-14 2007-09-14 半導体メモリ
JP2009531987A JP5035348B2 (ja) 2007-09-14 2007-09-14 半導体メモリ
US12/696,580 US8213253B2 (en) 2007-09-14 2010-01-29 Semiconductor memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/001007 WO2009034603A1 (ja) 2007-09-14 2007-09-14 半導体メモリ

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/696,580 Continuation US8213253B2 (en) 2007-09-14 2010-01-29 Semiconductor memory

Publications (1)

Publication Number Publication Date
WO2009034603A1 true WO2009034603A1 (ja) 2009-03-19

Family

ID=40451628

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/001007 Ceased WO2009034603A1 (ja) 2007-09-14 2007-09-14 半導体メモリ

Country Status (4)

Country Link
US (1) US8213253B2 (ja)
JP (1) JP5035348B2 (ja)
KR (1) KR101139163B1 (ja)
WO (1) WO2009034603A1 (ja)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013214345A (ja) * 2012-03-05 2013-10-17 Fujitsu Semiconductor Ltd 不揮発性ラッチ回路及びメモリ装置
US9460760B2 (en) 2015-01-23 2016-10-04 Globalfoundries Inc. Data-dependent self-biased differential sense amplifier
JP2019518300A (ja) * 2016-04-05 2019-06-27 マイクロン テクノロジー，インク． 強誘電体メモリセルからの電荷抽出
JP2022134618A (ja) * 2021-03-03 2022-09-15 国立大学法人東北大学 抵抗変化型素子を備えた記憶回路

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5727892B2 (ja) * 2010-08-26 2015-06-03 株式会社半導体エネルギー研究所 半導体装置
FR3045982B1 (fr) * 2015-12-18 2019-06-14 Commissariat A L'energie Atomique Et Aux Energies Alternatives Cellule logique a faible consommation
US9786347B1 (en) * 2016-03-16 2017-10-10 Micron Technology, Inc. Cell-specific reference generation and sensing
US10153021B1 (en) 2017-06-09 2018-12-11 Micron Technology, Inc. Time-based access of a memory cell
US10153022B1 (en) 2017-06-09 2018-12-11 Micron Technology, Inc Time-based access of a memory cell
US10475498B2 (en) * 2017-07-18 2019-11-12 Micron Technology, Inc. Self-boost, source following, and sample-and-hold for accessing memory cells
US10667621B2 (en) 2018-04-19 2020-06-02 Micron Technology, Inc. Multi-stage memory sensing
US10867653B2 (en) 2018-04-20 2020-12-15 Micron Technology, Inc. Access schemes for protecting stored data in a memory device
US10622050B2 (en) * 2018-05-09 2020-04-14 Micron Technology, Inc. Ferroelectric memory plate power reduction
US11360704B2 (en) 2018-12-21 2022-06-14 Micron Technology, Inc. Multiplexed signal development in a memory device
US10726917B1 (en) * 2019-01-23 2020-07-28 Micron Technology, Inc. Techniques for read operations

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004093088A1 (ja) * 2003-04-10 2004-10-28 Fujitsu Limited 強誘電体メモリおよびそのデータ読み出し方法
JP2007184016A (ja) * 2006-01-04 2007-07-19 Fujitsu Ltd 強誘電体メモリ

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4031904B2 (ja) 2000-10-31 2008-01-09 富士通株式会社 データ読み出し回路とデータ読み出し方法及びデータ記憶装置
JP3866913B2 (ja) 2000-11-21 2007-01-10 富士通株式会社 半導体装置
JP2003109378A (ja) * 2001-09-28 2003-04-11 Matsushita Electric Ind Co Ltd 半導体記憶装置
US7227769B2 (en) 2004-03-08 2007-06-05 Fujitsu Limited Semiconductor memory
JP4647313B2 (ja) * 2005-01-06 2011-03-09 富士通セミコンダクター株式会社 半導体メモリ
JP4452631B2 (ja) * 2005-01-21 2010-04-21 パトレネラ キャピタル リミテッド， エルエルシー メモリ

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004093088A1 (ja) * 2003-04-10 2004-10-28 Fujitsu Limited 強誘電体メモリおよびそのデータ読み出し方法
JP2007184016A (ja) * 2006-01-04 2007-07-19 Fujitsu Ltd 強誘電体メモリ

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013214345A (ja) * 2012-03-05 2013-10-17 Fujitsu Semiconductor Ltd 不揮発性ラッチ回路及びメモリ装置
US9460760B2 (en) 2015-01-23 2016-10-04 Globalfoundries Inc. Data-dependent self-biased differential sense amplifier
JP2019518300A (ja) * 2016-04-05 2019-06-27 マイクロン テクノロジー，インク． 強誘電体メモリセルからの電荷抽出
US11087816B2 (en) 2016-04-05 2021-08-10 Micron Technology, Inc. Charge extraction from ferroelectric memory cell
US11322191B2 (en) 2016-04-05 2022-05-03 Micron Technology, Inc. Charge extraction from ferroelectric memory cell
JP2022134618A (ja) * 2021-03-03 2022-09-15 国立大学法人東北大学 抵抗変化型素子を備えた記憶回路
JP7677611B2 (ja) 2021-03-03 2025-05-15 国立大学法人東北大学 抵抗変化型素子を備えた記憶回路
US12424273B2 (en) 2021-03-03 2025-09-23 Tohoku University Storage circuit provided with variable resistance type elements

Also Published As

Publication number Publication date
JP5035348B2 (ja) 2012-09-26
KR101139163B1 (ko) 2012-04-26
KR20100064363A (ko) 2010-06-14
US8213253B2 (en) 2012-07-03
JPWO2009034603A1 (ja) 2010-12-16
US20100128515A1 (en) 2010-05-27

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