WO2009024172A1 - Testeur de puce, système de test de puce, configuration de test de puce, procédé d'identification d'une défaillance de ligne ouverte et programme d'ordinateur - Google Patents

Testeur de puce, système de test de puce, configuration de test de puce, procédé d'identification d'une défaillance de ligne ouverte et programme d'ordinateur Download PDF

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Publication number
WO2009024172A1
WO2009024172A1 PCT/EP2007/007387 EP2007007387W WO2009024172A1 WO 2009024172 A1 WO2009024172 A1 WO 2009024172A1 EP 2007007387 W EP2007007387 W EP 2007007387W WO 2009024172 A1 WO2009024172 A1 WO 2009024172A1
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WO
WIPO (PCT)
Prior art keywords
dut
signal
power supply
common line
terminal
Prior art date
Application number
PCT/EP2007/007387
Other languages
English (en)
Inventor
Michael Daub
Alf Clement
Bernd Laquai
Original Assignee
Verigy (Singapore) Pte. Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Verigy (Singapore) Pte. Ltd. filed Critical Verigy (Singapore) Pte. Ltd.
Priority to PCT/EP2007/007387 priority Critical patent/WO2009024172A1/fr
Publication of WO2009024172A1 publication Critical patent/WO2009024172A1/fr

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Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R35/00—Testing or calibrating of apparatus covered by the other groups of this subclass
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31901—Analysis of tester Performance; Tester characterization
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31924—Voltage or current aspects, e.g. driver, receiver

Definitions

  • Chip Tester Chip Test System
  • Chip Test Setup Method for Identifying an Open-line Failure and Computer Program
  • the present invention generally relates to a chip tester, a chip test system, a chip test setup, a method for identifying an open-line failure and a computer program.
  • the present invention creates a chip tester for testing a plurality of devices under test (DUTs) .
  • the chip tester comprises an input for connection to a common line, a bias source for biasing the common line and a controller.
  • the controller is adapted to control a provision of a first signal for a first device under test and the provision of a second signal for a second device under test, to control the first device under test and the second device under test such that, in a measurement phase, an effect of an electrical characteristic of the first device under test to the DC state at the input is distinguishable from an effect of an electrical characteristic of the second device under test to the DC state at the input.
  • the chip tester comprises a measurement unit adapted to measure a DC state at the input which is present in the measurement phase. Also, the chip tester comprises a diagnosis unit adapted to decide whether an open-line failure is present with respect to the first device under test on the basis of the measured DC state at the input.
  • the present invention creates a chip test system according to claim 17, a chip test setup according to claim 18, a method for identifying an open-line failure according to claim 22 and a computer program according to claim 26.
  • Fig. 1 shows a block schematic diagram of a chip test setup, according to an embodiment of the present invention
  • Fig. 2 shows a block schematic diagram of a chip test setup, according to an embodiment of the present invention
  • Fig. 3 shows an equivalent circuit of a chip test setup, according to an embodiment of the present invention
  • Fig. 4 shows a graphical representation of a measurement phase in a chip test setup, according to an embodiment of the present invention
  • Fig 5a shows a graphical representation of a measurement phase in a chip test setup, according to an embodiment of the present invention
  • Fig. 5b shows a graphical representation of a measurement phase in a chip test setup, according to an embodiment of the present invention
  • Fig. 5c shows a graphical representation of a measurement phase in a chip test setup, according to an embodiment of the present invention
  • Fig. 6 shows a graphical representation of a "connect” to "open” margin
  • Fig. 7 shows a graphical representation of a current flow as a function of a force voltage in a chip test setup, according to an embodiment of the present invention.
  • Fig. 8 shows a flow chart of a method according to an embodiment of the present invention.
  • Fig. 1 shows a block schematic diagram of a chip test setup, according to an embodiment of the present invention.
  • the chip test setup of Fig. 1 is designated in its entirety with 100 and comprises a chip tester 110, a DUT board 120, and two DUTs 130, 132.
  • the chip tester 110 by itself has to be considered as an embodiment of the invention, even without the DUT board 120 and the DUTs 130, 132.
  • a combination comprising the chip tester 110 and DUT board 120 will be considered as another embodiment of the present invention, also designated as a chip test system.
  • the chip tester 110 and the DUT board 120 may be provided by different manufacturers. Also, the DUTs 130, 132 are typically provided by a different company, when compared to the chip tester 110 and/or the DUT board 120.
  • the chip tester 110 comprises an input 140 for connection to a common line 142.
  • the input 140 may for example be a dedicated input of the chip tester, or may be an input/output of the chip tester which is configured to act as an input.
  • the chip tester further comprises a measurement unit 144, which is adapted to measure a DC state at the input 140.
  • the measurement unit 144 may for example be a part of a channel module of the chip tester. Alternatively, the measurement unit 144 may be part of a centralized measurement system, which can be connected to the input 144 (e.g. via a system of switches and lines). If the measurement unit 144 is part of a channel module 146, the channel module may for example further comprise an optional output unit 148, which is also coupled to the input or port 140.
  • the chip tester 110 comprises a diagnosis unit 150, which may be coupled to the measurement unit 144 to receive the measurement results.
  • the chip tester 110 comprises a bias source 152 for biasing the common line 142.
  • the common line 142 is also designated as "shared line” herein.
  • the chip tester 110 comprises a controller 160 which is coupled to two signal providers 162, 164 to control the provision of a first signal 166, which is output by the first signal provider 162, and of a second signal 168, which is output by the second signal provider 164.
  • the DUT board 120 is generally adapted to provide for an electrical connection between the chip tester 110 and at least two DUTs 130, 132.
  • the DUT board 120 comprises chip tester contact elements adapted to provide for an electrical connection between the DUT board 120 and the chip tester 110.
  • the chip tester contact elements on the DUT board are adapted to engage with corresponding contact elements of the chip tester.
  • the contact elements of the chip tester may for example be provided in the form of a POGO interface.
  • the DUT board 120 comprises a common line 142 which is routed such that at least two DUTs 130, 132 can be connected to the common line.
  • the DUT board 120 comprises DUT contact elements 170, 172 for establishing an electrical contact between the common line 142 and terminals of the first device 130 and the second device 132.
  • the DUT board 120 comprises a route for providing the first signal 166 output by the signal provider 162 to the first DUT 130.
  • the DUT board 120 further comprises another DUT contact element 174 for providing the first signal 166 to a terminal of the first DUT 130.
  • the DUT board 120 also comprises a route for providing the second signal 168 to a terminal of the second DUT 132.
  • DUT board 120 comprises a DUT contact element 176 for establishing an electrical contact between the second signal 168 and a respective terminal of the second DUT 132.
  • the DUT board 120 comprises DUT contact elements 178, 180 for providing a reference potential GND to the DUTs 130, 132.
  • the DUT board 120 comprises a common line biasing circuit 190 which is adapted to bias the common line 142 on the basis of a bias signal 192 provided by the bias source 152 of the chip tester 110.
  • the bias signal 192 is fed to the DUT board via a contact element between the chip tester and the DUT board 120.
  • the biasing circuit 190 may for example comprise a capacitor 194, which may for example be connected between bias signal 192 and the reference potential GND.
  • the biasing circuit 190 may comprise an impedance element 196 (e.g. a resistor, or any other resistive element) , which may be connected in series between the bias signal 192 and the common line 142.
  • An impedance of the impedance element 196 may be matched to a transmission line impedance of the common line 142, but various impedances may be used for the impedance element 196.
  • the controller 160 is, in an embodiment of the invention, adapted to control a provision of a first signal 166 for the first DUT 130 and the provision of the second signal 168 for the second DUT 132, to control the first DUT 130 and the second DUT 132, such that in a measurement phase, the impact of an electrical characteristic of the first DUT 130 to a DC state at the input 140 is distinguishable from an effect of an electrical characteristic of the second DUT to the DC state at the input 140. Consequently, by appropriately controlling the first signal 166 and the second signal 168, the chip tester is able to recognize whether a specific of the DUTs, for example, the first DUT 130, is connected to the common line.
  • the chip tester is adapted to control the first signal 166 and the second signal 168 such that the effiects of the electrical characteristics of the DUTs 130, 132 on the DC state of the common lines 142, which can be measured at the input 140, are distinguishable, a measurement of the state of the input 140 is sufficient in order to identify whether one of the DUTs is not connected to the common line (which condition is designated as an open-line failure) .
  • an open-line failure is any undesirable open circuit between the common line 142 and the respective DUT, for example an interruption of a trace on a DUT board, an interruption at a contact element between the DUT board and the DUT, or an interruption in the DUT itself.
  • the above described chip tester 110 allows an advanced identification of a location of an open-line failure in a setup in which multiple DUTs are connected to a common line.
  • the chip tester 110 provides an improved diagnosis result when compared to conventional chip testers.
  • Open-line failures can be recognized more rapidly without extensive additional investigation. Accordingly, such failures can also be corrected or repaired very quickly and efficiently. Therefore, reliability of the test equipment and test throughput can be improved due to the improved diagnosis of open-line failures. As a consequence test costs can be reduced. Also, under some circumstances it can be avoided that fully operational DUTs are discarded as defective.
  • the DUTs 130, 132 may be nominally identical DUTs, i.e. DUTs having the same nominal specifications.
  • the DUTs 130, 132 may be two
  • DUTs taken out of a single integrated circuit fabrication process defined to produce, under ideal conditions, DUTs having identical electrical characteristics.
  • the above described provision of the first signal 166 and the second signal 168 is preferably performed such that even identical DUTs 130,132 provide different electrical characteristics at their respective terminals connected to the common line 142.
  • the signals 166, 168 provided to the DUTs 130, 132 are chosen such that the first DUT 130 exhibits at a terminal connected to the common line 142 a different voltage-current-characteristic with respect to the reference potential GND than the second DUT 132.
  • the first signal 166 and the second signal 168 are provided such that the signals at the contact elements 170,172 exhibit an instantaneous dependence on the signals 166,168.
  • the signals 166,168 are analog signals which have an immediate impact on the terminals connected to the common line 142 of the DUTs 130,132.
  • the first signal 166 and the second 168 are both power supply signals, which are connected to power supply contacts of the DUTs 130,132.
  • the DUTs 130, 132 are brought to different power supply states by controlling the signals 166, 168.Consequently, the DUTs 130,132 may have different electrical characteristics, such that the effect of an electrical characteristic of the first DUT 130 to the DC state of the input 140 is distinguishable from the effect of the electrical characteristic of the second DUT 132 to the DC state of the input 140.
  • the controller 160 may be adapted to control the provision of the signals or power supply signals 166, 168 such that the first DUT 130 is powered down and such that the second DUT 132 is powered up in the measurement phase.
  • an open-line failure with respect to the first DUT 130 e.g. interruption of an electrical connection between the terminal of the first DUT 130 and the common line 142, or an interruption within the first DUT 130
  • the DUT 130 may comprise a terminal protection diode connected between the terminal coupled to the common line 142 and the terminal coupled to the first signal 166.
  • the second DUT 132 may have an input protection diode connected between the terminal coupled to the common line 142 and the terminal connected to the second signal 168.
  • Said terminal protection diodes may for example be conductive (or forward biased) when a potential at. the terminals coupled to the common line 142 is higher than (i.e. more positive) a potential of a supply terminal coupled to the first signal 166 or to the second signal 168. Details regarding the terminal protection diodes will subsequently be described.
  • an embodiment of the present invention may implement an advanced multi-phase procedure for subsequently checking for open-line failures of the first DUT 130 and of the second DUT 132.
  • levels of the first signal 166 and the second signal 168 are swapped after a first measurement phase to obtain a second measurement phase.
  • the signals 166,168 are controlled such that in a failure- free case, the first DUT 130 dominates (or dominantly determines) the DC state of the common line 142 and/or the DC state at the input 140 of the chip tester 110 when compared to the second DUT 132.
  • the signals 166, 168 are chosen such that in a first failure-free case, the second DUT 132 dominates the state of the common line 142 and/or the state of the input 140 when compared to the first device.
  • the signals 166, 168 may be chosen such that in a measurement phase the first DUT 130 takes a current from
  • the signals 166, 168 may configure the DUTs such that the first DUT 130 acts as a stronger load with respect to the common line 142 than the second DUT 132.
  • the different load characteristics of the DUTs 130, 132 may then be evaluated in order to determine, whether an open-line failure is present. The presence of an open-line failure may, for example, be detected if the DUT does not comprise a load characteristic which has been expected for the failure-free case.
  • the load characteristics of the DUTs 130, 132 may for example be monitored directly by measuring the voltage at the input 140 in response to the bias signal 192 biasing the common line 142.
  • An actual potential of the common line 142 is not only determined by the bias signal 142 but also by the load characteristic of the DUTs 130, 132, such that the potential of the common line 142 allows for a determination of the load state.
  • Fig. 2 shows a block schematic diagram of a multi-DUT test setup.
  • the test setup of Fig. 2 is designated in its entirety with 200.
  • the test setup 200 is adapted to provide input signals to inputs of multiple DUTs via one or more common lines.
  • the test setup 200 comprises a chip tester 210, and a DUT board or circuit board 220.
  • the chip tester 210 may be identical to the chip tester 110 of Fig. 1.
  • two output channels 230, 232 for outputting data signals to the DUT are shown in block schematic diagram 200. It should be noted that the presence of output channels is not required for the inventive concept of determining a position of an open-line failure.
  • the DUT board 220 may for example comprise contact elements for at least two DUTs, such that a contact between the DUTs and traces on the DUT board can be established.
  • the DUT board 220 further comprises at least one common line 242, to which terminals (preferably input terminals) of at least two DUTs are connected.
  • a total of four DUTs 250, 252, 254, 256 also designated as DUT A , DUT B , DUT C , and DUT 0
  • two common lines 242, 262 are shown.
  • the common lines 242, 262 are bus-like lines which comprise branches to connect the terminals of the individual DUTs.
  • the first common line 242 comprises a first branch point 242a, a second branch point 242b, a third branch point 242c, and a fourth branch point 242d.
  • the second common line 262 comprises four branch points, 262a, 262b, 262c and 262d.
  • a trace e.g. a transmission line on the DUT board
  • a trace branches from a second common line 262 to connect a terminal of the first DUT 250 with the second common line 262.
  • the first DUT 250 (as well as the other DUTs) may be connected to the common line 242, 262 via DUT contact elements (e.g. a DUT socket), which may for example allow for an exchange of the DUTs.
  • a trace branches from the first common line 242 at the branch point 242b for connecting a terminal of the second DUT 252 with the first common line.
  • a trace branches from the second common line at the branch point 262b to connect a terminal of the second DUT 252 with the second common Line.
  • traces for connecting the third DUT 254 and the fourth DUT 256 branch from the common lines 242, 262 at branch points 242c, 242d, 262c, 262d.
  • all the transmission lines preferably have a predetermined characteristic impendence, for example 50 Ohm. However, other characteristic impedances may be chosen. Also, characteristic impedances may vary for the sake of matching, if appropriate.
  • Termination circuit 270 is, for example, connected to the branch points 242d, 262d via transmission linesi.
  • Termination circuit 270 may for example comprise an individual terminal resistor 272, 274 for each common line
  • One terminal of the resistor 272 is for example connected to the common transmission line 242, and the second terminal of the resistor 272 is for example connected to a termination node 276.
  • the first terminal of the termination resistor 274 may be coupled to the second common line 262, and a second terminal of the termination resistor 274 may be coupled to the termination node 276.
  • the termination node 276 may also be coupled, via one or more capacitors 278, 280 with a reference potential GND.
  • the termination capacitances 278, 280 may for example have a capacitance of approximately 100 ⁇ F.
  • a termination voltage source 290 may be connected to the termination node 276.
  • the termination voltage source 290 may for example be formed by a device power supply of the chip tester. However, alternative termination sources may be used.
  • the termination voltage source may for example comprise a relatively large buffer capacitance 292 which may, for example, have a capacitance of the order of 100 ⁇ F..
  • the capacitance 292 may either be integral to the termination voltage source 290 or may be connected in parallel with an output of the termination voltage source.
  • the termination voltage source 290 and the capacitance 292 are also connected to the reference potential GND. However, this is not necessary, and other configurations are possible.
  • the common lines 242, 262 may for example comprise address lines, for example for the testing of addressable memory devices.
  • the DUTs 250, 252, 254, 256 may for example be memory devices having address inputs (or column address inputs) and/or block address inputs.
  • the common lines may also be data lines and/or control lines.
  • driver sharing brings along some architectural impacts. In respect to continuity, driver sharing introduces new hurdles (or challenges) and therefore also physical limitations (or challenges) .
  • the hurdles can be described as follows.
  • All shared pins or common pins e.g. DUT terminals connected to a common line
  • All shared pins or common pins are biased together at the end of the shared bus or common bus. Consequently, there is a common connection.
  • Voltage changes are distributed over all shared pin lines or common pin lines and the connected devices. In other words, there is a coupling between two different common lines 242, 262 in the termination circuit 270.
  • a specialized DC based method is able to detect an open failure in the case of all lines open and a single line open.
  • a single line open is a case in which a connection between a terminal of a device under test and a corresponding line (for example a corresponding common line, or shard line) is interrupted. The interruption may for example be located on the DUT board, at in interface between the DUT board and a DUT package, or within the DUT package .
  • a "short" failure has a global impact.
  • a specialized DC-based method is able to detect a "short” failure.
  • the effect (of the "short” failure) has a global impact on all shared devices or common devices per bus, as all common lines are traced together.
  • both a "short” failure and an "open” failure can be detected using specialized DC-based methods. It should be noted here that the concept described within the present application is particularly suited for the detection of "open” failure conditions. Consequently, it is not necessary (but optionally possible) to introduce a detection of "short” failure conditions in the ' embodiments of the present invention.
  • Fig. 3 shows an equivalent circuit diagram of the test setup 200 of Fig. 2.
  • the equivalent circuit of Fig. 3 is designated in its entirety to 300.
  • said equivalent circuit is valid if a termination voltage source is activated.
  • the device power supply or termination voltage source 290 DPS
  • the termination voltage source 290 is actually connected to the termination node 276, thus applying a predetermined termination voltage VTERM to the termination node 276.
  • Termination node 276 is tied to a fixed potential by the termination voltage source connected to the termination node 276. Consequently, any current signals arriving for example from the first common line 242 at the termination node 276 will be sinked by the termination voltage source 290. Consequently, the potential of the termination node 276 does not significantly change. Therefore, there is no coupling between the common lines 242, 262 via the termination node 276.
  • the DC-based method can be considered to be a test method based on a per pin measurement unit (PPMU) measurement with connected termination source 290 (wherein the termination source 290 may, for example, comprise a Daisy chain device power supply (DPS) terminating a common line) .
  • PPMU per pin measurement unit
  • DPS Daisy chain device power supply
  • Having an active signal (provided by the termination circuits) on the line is in contradiction to a standard continuity principle.
  • the described concept allows handling the commonly connected shared lines (also designated as common lines) as separate lines.
  • enabling the termination voltage source 290 isolates the connected shared lines (common lines) 242, 262 during the measurement (tied to a defined voltage) .
  • enabling the termination voltage source is an important idea to overcome the hurdles introduced by driver sharing.
  • the equivalent circuit 300 of Fig. 3 will be briefly described. It should be noted that the equivalent circuit 300 of Fig. 3 is based on the chip test setup 200 of Fig. 2, wherein it is assumed that the termination voltage source 290 is coupled to the termination node 276 (e.g. by closing a relay) . Moreover, it is assumed that the output channels 230, 232 of the chip tester 210 are replaced by analog measurement units. For example, the output channel 230 may be part of a channel module comprising an output driver and an analog measurement unit, which is also designated as "per-pin measurement unit" (PPMU) . Thus, for the present measurement, the output drivers 230, 232 are deactivated and replaced by per-pin measurement units PPMU.
  • PPMU per-pin measurement unit
  • the measurements described in the following are to be considered as DC measurements.
  • high frequency effects like, for example, transmission line effects can be neglected.
  • the transmission lines i.e. traces on the DUT board or cables
  • the resistance of the transmission lines is negligible.
  • the individual common lines e.g. lines 242, 262
  • the termination node 276 is tied to a fixed potential, which is determined by the termination voltage source 290. Consequently, decoupled equivalent circuits can be established.
  • a first equivalent circuit 310 can be established, describing the first common line 242 by an equivalent connection 342.
  • Circuit components of the DUTs 250, 252, 254, 256 are connected to the first common line 242 are represented by equivalent circuits 350a, 352a.
  • the termination resistor 272, the capacitor 292 and the termination voltage source 290 are represented by equivalent elements 372, 392, 390.
  • the per-pin measurement unit connected to the first common line 242 is represented by an equivalent element 394.
  • the termination circuit 270 serves as a source for biasing the first common line 242.
  • the per-pin measurement unit of the channel module connected to the common line 242 serves as a measurement instrument for measuring any effects of the DUTs 250, 252, 254, 256 on the DC state of the common line 242.
  • an equivalent circuit 320 describes the second common line 262, represented by the equivalent line 362, as well as the termination circuit, the DUTs and the per-pin measurement unit connected to the second common line 262.
  • the termination circuit 270 for the second common line 262 is represented by a resistor 374 (which represents the resistor 274), a capacitor 392 (which represents capacitor 292) and a voltage source 390 (which represents the termination voltage source 290) . It should be noted that the termination voltage source 290 and the capacitor 292 are represented in both equivalent circuits 310, 320, as these elements are shared for both common lines 242, 262.
  • circuit parts of the DUTs 250, 252, 254, 256 connected to the second common line 262 are represented by equivalent circuits 350b, 352b.
  • a per-pin measurement unit connected to the second common line 262 is represented by an equivalent circuit 396.
  • a termination device power supply for example the termination voltage source 290, is used as an active voltage source.
  • a termination resistance e.g. a 50 Ohm resistance, acts as a current limiting element or current limiting factor (confer resistors 272, 274 and equivalent resistors 372, 374) .
  • the per-pin measurement unit PPMU is used as a pure voltmeter. The per-pin measurement unit is set to provide a high impedance throughout the measurement.
  • a specific device under test is disconnected and/or powered down (0 V) .
  • supply potentials of the specific DUT are set to the reference potential GND. While it is not necessary to set all the supply potentials of the specific DUT to the reference potential GND, this solution may be used in an embodiment of the present invention.
  • only one of the supply potentials e..g. a supply potential of an interface part of the specific DUT
  • All other DUTs or at least one other DUT, within the same domain (i.e. which are connected to the same common line 242, 262) are powered up.
  • some supply potentials of the other DUTs are set to a non-zero value, as will be described in more detail in the following.
  • the voltage of the termination source i.e. the voltage of the termination voltage source
  • force voltage the voltage of the termination source
  • the measured voltage does not equal the forward bias voltage of the diodes. Rather, the voltage is an undefined voltage that heavily depends on the leakage in this case.
  • the force voltage i.e. the voltage of the termination voltage source 290
  • the threshold voltage of a diode which is present in the device under test. Consequently, increasing the force voltage increases the forward bias voltage of the diode. If the force voltage is smaller than the threshold voltage, there is only a very limited current flow, as the diode is still blocking (or at least not sufficiently forward biased to provide a measurable current) .
  • the forward bias voltage is tied to the bias current (behaves exponentially) , this allows the retrieval of a reliable voltage margin to differentiate between "connect" and "open state".
  • the measured voltage margin is an indicator of the current value flowing.
  • the current can be calculated making use of the following equation:
  • the voltage measured by a per-pin measurement unit deviates from the voltage of the termination voltage source 390 by the voltage drop over the resistor 372.
  • the current flowing through the resistor 372 is substantially determined by a current flowing into the DUTs 350a, 352a (or flowing outward from the DUTs 350a, 352a) .
  • Fig. 4 shows an equivalent circuit of the measurement setup for identifying an open-line failure according to an embodiment of the present invention.
  • a block schematic diagram of Fig. 4 is designated in its entirety with 400. It should be noted here that the block schematic diagram 400 comprises substantially the same components as the block schematic diagram 300. Thus, identical means are designated with identical reference numerals and will not be explained here again.
  • the first DUT 350a comprises a terminal 410, which is connected to the common line 342.
  • the second DUT 352a comprises a terminal 412 which is connected to common line 342.
  • the first DUT 350a comprises a power supply terminal 420
  • the second DUT 352a comprises a power supply terminal 422.
  • the first DUT 350a may be equivalent to the first DUT 130 of the test setup 100
  • the second DUT 352a may be equivalent to the second DUT 132 of the test setup 100
  • the power supply terminal 420 may be equivalent to the terminal of the first DUT 130 connected to the contact element 174, and thus connected to receive the first signal 166.
  • the power supply terminal 422 of the second DUT 352a may be equivalent to the terminal connected to the conduct element 176 of the DUT 132. Consequently, the power supply terminal 422 may receive, or may be coupled to, the second signal 168.
  • a terminal protection diode 430 may be connected between the terminal 410 and the power supply terminal 420.
  • a terminal protection diode 432 may be connected between the terminal 412 and the power supply terminal 422.
  • the terminal 410 may, for example, be an input terminal of the DUT 350a and that the terminal 412 may for example, be an input terminal of the second DUT 352a.
  • the terminals 410, 412 may also be output terminals or input/output terminals having programmable input/output direction.
  • the first DUT 350a and the second DUT 352a may further comprise additional power supply terminals, which may, for example, be connected to the reference potential GND, or to another supply potential .
  • a force voltage may be present at the termination voltage source 390.
  • the same voltage, or a voltage of the same value may be applied to the power supply terminal 422 of the second DUT 352.
  • the force voltage is a positive voltage (positive with respect to the reference potential GND) .
  • a negative force voltage might also be used in an appropriate circuit configuration.
  • the power supply terminal 420 of the first DUT 350a is set to zero Volt. This can, for example, be achieved by providing a voltage of 0 V as the first signal 166, and by providing a voltage having the value of the force voltage as the second signal 168.
  • the voltage of the common line 342 can be measured by the per-pin measurement unit 394, which is preferably programmed not to provide any current to the common line 342 and not to sink any currents from the common line 342.
  • the per-pin measurement unit 394 is programmed to be in a high impedance state so that only a negligible leakage current flows into the per-pin measurement unit 394, which is significantly smaller than the current flowing through the diode 430 of the first DUT 350a. Assuming now that the terminal 410 of the first DUT 350a is not connected to the common line 342, the behavior in the case of an "open" failure can be analyzed.
  • the presence of the second DUT 352a does not have any effect on the measurement result.
  • the signals are supplied to said supply potentials of the DUTs such that at least one terminal protection diode of a DUT is forward biased in a failure- free case, while corresponding terminal protection diodes of other DUTs are not forward biased or even reverse biased under the same measurement conditions.
  • This can be achieved by supplying different supply potentials to different DUTs connected to the common line 342.
  • a reliable measurement may be achieved if the operation conditions of the DUTs are controlled such that a current flowing through the terminal of a specific DUT under consideration is at least 10 times larger than currents flowing through the corresponding input terminals of the other (or all the other) DUTs connected to the same common line 342 for given measurement conditions in a failure-free case.
  • the termination voltage source 390 and the potential of the supply terminal 422 are not absolutely necessary to set the termination voltage source 390 and the potential of the supply terminal 422 to exactly the same values.
  • a sufficiently small deviation may be tolerated, provided that the deviation does not result in excessive leakage current and also provided that the current flowing through the powered down device (e.g. the first DUT 350a) is still sufficiently larger (e.g. 10 times larger) than the current flowing through the input terminal 412 of the powered up device.
  • the powered down device e.g. the first DUT 350a
  • the current flowing through the powered down device is still sufficiently larger (e.g. 10 times larger) than the current flowing through the input terminal 412 of the powered up device.
  • identical potentials have been assumed here.
  • Fig. 5a shows an equivalent circuit of the test setup 200, which has already been described with reference to Figs. 3 and 4. Thus, same means and signals are designated with same reference numerals.
  • Fig. 5a shows a condition under which a termination voltage source 390 is set to 800 mV, e.g. by controlling a device power supply to set this value.
  • the supply potential for the power supply terminal 422 of the second DUT 352 is set to 80OmV, for example, by setting the signal provider 164 to provide a second signal 168 correspondingly.
  • a supply potential for the power supply terminal 420 of the first DUT 350a is set to zero Volt.
  • a current flowing through the input terminal 412 of the second DUT 352a is negligible, while a current flowing through the input terminal 410 of the first DUT 350a is approximately 1.4 mA.
  • a voltage drop across the resistor 372 is about 7OmV (50 Ohm x 1.4 mA) , such that the potential of the common line 342 is approximately 730 mV. If the first DUT 350a was not connected (e.g. in the case of an open-line failure) the potential of the common line 342 would be expected to be 800 mV, as provided by the termination voltage source 390.
  • a "margin" i.e. a difference between the voltage of the common line 342 in a failure- free case and in the case of an open-line failure, is approximately 70 mV.
  • Fig. 5b shows an equivalent circuit of another measurement setup.
  • the measurement set up of Fig. 5b is identical to the measurement setup of Fig. 5a, but the only differences being the operation point of the circuit in the measurement setup of Fig. 5b, a voltage of 900 mV is applied to the termination voltage source 390. Also, the voltage of 900 mV is applied to the power supply terminal 422 of the second DUT 352a. The voltage of 0 V is applied to the power supply terminal 420 of the first DUT 350a. Thus, a current of approximately 2.5 mA is flowing into the terminal 410 of the first DUT 350a. Again, a current flowing through the terminal 412 of the second DUT 352a is negligible.
  • a voltage drop across the resistor 372 is approximately 125 mV, such that a voltage at the common line 342 is approximately 770 mV.
  • the voltage of approximately 770 mV can be measured by the per-pin measurement unit 394. It should be noted that in case of an open-line failure with respect to the first DUT 350a, the voltage on the common line 342 would be 900 mV. Therefore, the margin as defined above is 130 mV.
  • Fig. 5c shows an equivalent circuit of another measurement setup.
  • the structure of the measurement setup of Fig. 5c is identical to the measurement setups of Figs. 5a and 5b.
  • the voltage of the termination voltage source 390 is set to 1000 mV.
  • the voltage at the power supply terminal 422 of the second DUT 352a is set to 1000 mV r and the voltage at the power supply terminal 420 of the first DUT 350a to 0 V.
  • the current through the diode 430 of the first DUT 350a is approximately 3.7 mA.
  • a voltage drop across the resistor 372 is approximately 180 mV, and a voltage of the common line 342, which can be measured by the per-pin measurement unit 394, is approximately 820 mV.
  • the margin in this case is approximately 180 mV.
  • the common line 342 takes a voltage of approximately 0 V, if there is a short circuit between the common line 342 (or any lines branching from the common line 342) and the reference potential. Thus, a short circuit condition can be identified by measuring the voltage of the common line, but the location of the short circuit cannot easily be determined.
  • a potential difference between a potential provided by the termination voltage source 390 and a supply potential for the power supply terminal 420 of the first DUT 350a is chosen to be larger than a threshold voltage of an input protection diode of the first device under test.
  • a potential difference between the potential provided by the termination voltage source 390 and a supply potential for the power supply terminal 422 of the second DUT 352a is chosen to be smaller than a threshold voltage of an input protection diode of the second device under test.
  • the voltage detected can be mapped to the forward bias voltage of the internal device protection diode or terminal protection diode.
  • the resulting voltage (measured, for example, by the per-pin measurement unit 394) will equal (or will at least be approximately equal) the force voltage specified by the termination device power supply (DPS), as there is no current flow (or only a sLight negligible current flow) .
  • DPS termination device power supply
  • the location of the open fault can be determined. It should be noted that with the above setup described with respect to Figs. 4 and 5a to 5c, it can be detected whether there is an open failure with respect to the first DUT 350a. In contrast, an open failure with respect to a second DUT 352a will not be detected in the measurement set up of Figs. 4 and 5a to 5c. However, an open failure with respect to the second DUT 352 can of course be detected by reiterating the measurement, as will be described below. Consequently, in an embodiment of the present invention it is possible to detect the location of the open failure.
  • Fig. 6 shows a graphical representation of a relationship between the force voltage (i.e. the voltage applied to the terminal voltage source 390) and the pass-fail margin (i.e. the difference between the voltage measured by the per-pin measurement unit in the failure-free case and in the case of an open-line failure) .
  • the graphical representation of Fig. 6 is designated in its entity with 600.
  • An abscissa 610 describes the force voltage in terms of volts
  • an ordinate 612 describes the pass-fail margin in terms of volts.
  • Fig. 6 shows a "connect” to "open” margin common pins average- "connect” state.
  • the common pin average is an average over a large number of common lines.
  • the graphical representation of Fig. 6 shows the relationship between the force voltage and the pass-fail margin for four different sites or DUTs, as can be seen from the legend 620.
  • Fig. 7 shows a graphical representation of a relationship between the force voltage and a current into a device under test.
  • the graphical representation of Fig. 7 is designated in its entity with 700.
  • An abscissa 710 describes the force voltage in terms of volts
  • an ordinate 712 describes the current into a DUT in terms of mA.
  • the graphical representation of Fig. 7 shows a single site result describing a current flow.
  • the graphical representation of Fig. 7 shows a common pins average for a "connect" state.
  • the common pin average is an average over a large number of common lines.
  • graphical representation 700 of Fig. 7 shows two curves, as can be seen from the legend 720.
  • a first curve 730 describes the current into a device if all sockets (e.g. DUT sockets) are populated, and a second curve 732 describes the current into a device if a single socket is populated.
  • the measurement sequence according to this embodiment comprises the following steps:
  • a power supply for a plurality of devices is configured such, that a first device under test is powered down. It's power supply terminal is set to a low voltage, for example to 0 V (with respect to a reference potential) .
  • the configuration of the power supply- is performed such that at least one other DUT is powered up, it's power supply terminal being set to a higher voltage than the corresponding power supply terminal of the first DUT.
  • the second DUT is in a state which is called a "powered-up" state.
  • the voltage is applied to a termination voltage source such that, in a failure-free case, a detectable current flows to an input terminal of the first DUT, and such that a negligible current flows to a corresponding terminal of the second DUT. Subsequently, the voltage of the common line (or the current provided by the termination circuit) is measured.
  • the configuration of the power supply for the DUTs is changed, such that the first DUT is powered up, while the second DUT is powered down.
  • the significant and detectable current flows through the second DUT, and only a negligible current flows through the first DUT (via the ccoorrrreess;ponding input terminals connected to the common line) .
  • an open failure with respect to the first DUT can be detected on the basis of the measurement (e.g. the measurement of the voltage of the common line, or of the current provided by the termination circuit) .
  • the measurement e.g. the measurement of the voltage of the common line, or of the current provided by the termination circuit
  • BPOL measurement a measurement with both polarities
  • all sites (or DUTS) are powered down to make clamps visible and to remove the influence of powered up DUTs. In this case, it is not easily possible to differentiate between sites (or DUTs) .
  • Fig. 8 shows a flow chart of a method according to an embodiment of the present invention.
  • the method of Fig. 8 is designated in its entirety with 800.
  • the method. 800 comprises a first step 810 of applying a bias source to a common line, to bias the common line.
  • the method 800 further comprises a second step 820 of controlling the provision of a first signal for a first DUT and a provision of a second signal for a second DUT, to control the first DUT and the second DUT such that, in a measurement phase, the effect of an electrical characteristic of the first DUT to a DC state of the common line is distinguishable from the effect of an electrical characteristic of the second DUT to the DC state at the input.
  • the method 800 further comprises a third step 830 of measuring a DC state of the common line in the measurement phase.
  • the method 800 further comprises a fourth step 840 of deciding, whether an open-line failure is present with respect to the first DUT, on the basis of the measured DC state of the common line.
  • the method 800 can be supplemented by any of the steps and functionalities which are described within the present document. Moreover, the present invention comprises a computer program for performing the method 800.
  • the inventive methods can be implemented in hardware or in software.
  • the implementation can be performed using a digital storage medium, in for example a floppy disk, a DVD a CD, a ROM, a PROM, an EPROM, an EEPROm or a FLASH memory having electronically readable control signals stored thereon, which cooperate with a programmable computer system such that the inventive method is performed.
  • the present invention is, therefore, a computer program product with a program code stored on a machine readable carrier, the program code being operative for performing the inventive method when the computer program product runs on a computer.
  • the inventive method is, therefore, a computer program having a program code for performing the inventive method when the computer program runs on a computer.
  • a specialized DC based continuity test method is implemented, which is able to detect "fault” and “open” failures in a reliable way.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

L'invention porte sur un testeur de puce (110) destiné à tester une pluralité de dispositifs à tester (DUT) (130, 132), lequel testeur comprend une entrée (140) pour une connexion à une ligne commune (142), une source de polarisation (152) pour polariser la ligne commune et un contrôleur (160). Le contrôleur est apte à commander une fourniture d'un premier signal (166) pour un premier DUT et une fourniture d'un second signal (168) pour un second DUT, pour commander le premier DUT et le second DUT de telle sorte que, dans une phase de mesure, l'effet d'une caractéristique électrique du premier DUT sur l'état en courant continu à l'entrée est apte à être distingué de l'effet d'une caractéristique électrique d'un second DUT sur l'état en courant continu à l'entrée. Une unité de mesure (144) est apte à mesurer un état en courant continu à l'entrée dans la phase de mesure. Une unité de diagnostic (150) est apte à décider si une défaillance de ligne ouverte est présente ou non par rapport au premier DUT sur la base de l'état en courant continu mesuré à l'entrée.
PCT/EP2007/007387 2007-08-22 2007-08-22 Testeur de puce, système de test de puce, configuration de test de puce, procédé d'identification d'une défaillance de ligne ouverte et programme d'ordinateur WO2009024172A1 (fr)

Priority Applications (1)

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PCT/EP2007/007387 WO2009024172A1 (fr) 2007-08-22 2007-08-22 Testeur de puce, système de test de puce, configuration de test de puce, procédé d'identification d'une défaillance de ligne ouverte et programme d'ordinateur

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PCT/EP2007/007387 WO2009024172A1 (fr) 2007-08-22 2007-08-22 Testeur de puce, système de test de puce, configuration de test de puce, procédé d'identification d'une défaillance de ligne ouverte et programme d'ordinateur

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CN103091618A (zh) * 2011-11-03 2013-05-08 创意电子股份有限公司 电子测试系统与相关方法
WO2020116236A1 (fr) * 2018-12-06 2020-06-11 日本電産リード株式会社 Dispositif d'inspection, procédé d'inspection et programme de dispositif d'inspection
CN113326168A (zh) * 2021-05-19 2021-08-31 杭州加速科技有限公司 用于芯片测试的引脚映射方法

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US4862069A (en) * 1987-08-05 1989-08-29 Genrad, Inc. Method of in-circuit testing
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103091618A (zh) * 2011-11-03 2013-05-08 创意电子股份有限公司 电子测试系统与相关方法
WO2020116236A1 (fr) * 2018-12-06 2020-06-11 日本電産リード株式会社 Dispositif d'inspection, procédé d'inspection et programme de dispositif d'inspection
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CN113326168A (zh) * 2021-05-19 2021-08-31 杭州加速科技有限公司 用于芯片测试的引脚映射方法
CN113326168B (zh) * 2021-05-19 2022-06-28 杭州加速科技有限公司 用于芯片测试的引脚映射方法

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