WO2008153185A1 - プリント配線板製造用の埋設銅めっき方法及びその埋設銅めっき方法を用いて得られるプリント配線板 - Google Patents

プリント配線板製造用の埋設銅めっき方法及びその埋設銅めっき方法を用いて得られるプリント配線板 Download PDF

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Publication number
WO2008153185A1
WO2008153185A1 PCT/JP2008/061010 JP2008061010W WO2008153185A1 WO 2008153185 A1 WO2008153185 A1 WO 2008153185A1 JP 2008061010 W JP2008061010 W JP 2008061010W WO 2008153185 A1 WO2008153185 A1 WO 2008153185A1
Authority
WO
WIPO (PCT)
Prior art keywords
copper plating
printed wiring
embedding copper
wiring board
plating method
Prior art date
Application number
PCT/JP2008/061010
Other languages
English (en)
French (fr)
Inventor
Isao Wada
Takeshi Ohnishi
Original Assignee
Meltex Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Meltex Inc. filed Critical Meltex Inc.
Priority to CN2008800200212A priority Critical patent/CN103444275A/zh
Publication of WO2008153185A1 publication Critical patent/WO2008153185A1/ja

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/423—Plated through-holes or plated via connections characterised by electroplating method
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/02—Electroplating of selected surface areas
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/10—Electroplating with more than one layer of the same or of different metals
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09563—Metal filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14—Related to the order of processing steps
    • H05K2203/1476—Same or similar kind of process performed in phases, e.g. coarse patterning followed by fine patterning
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/421—Blind plated via connections

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrochemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

　電解法を用いてスルーホール及びビアホールの内部を埋設するめっき方法であって、生産コストに優れ、埋設金属めっき層の表面とプリント配線の外層表面の位置とのズレの少ない埋設めっき方法を提供することを目的とする。この目的を達成するため、導電性皮膜を備えるビアホール又はスルーホールの内部を電気めっき法で埋設する埋設銅めっき方法において、第１埋設銅めっき工程と第２埋設銅めっき工程とからなる２段階のめっき工程を備え、当該第１埋設銅めっき工程と第２埋設銅めっき工程とで同一組成の銅めっき液を用いることを特徴とするプリント配線板製造用の埋設銅めっき方法を採用する。
PCT/JP2008/061010 2007-06-15 2008-06-16 プリント配線板製造用の埋設銅めっき方法及びその埋設銅めっき方法を用いて得られるプリント配線板 WO2008153185A1 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN2008800200212A CN103444275A (zh) 2007-06-15 2008-06-16 印刷电路板制造用的镀铜填充方法以及使用该镀铜填充方法得到的印刷电路板

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007159577 2007-06-15
JP2007-159577 2007-06-15

Publications (1)

Publication Number Publication Date
WO2008153185A1 true WO2008153185A1 (ja) 2008-12-18

Family

ID=40129785

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/061010 WO2008153185A1 (ja) 2007-06-15 2008-06-16 プリント配線板製造用の埋設銅めっき方法及びその埋設銅めっき方法を用いて得られるプリント配線板

Country Status (3)

Country Link
JP (1) JP5247252B2 (ja)
CN (1) CN103444275A (ja)
WO (1) WO2008153185A1 (ja)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009021581A (ja) * 2007-06-15 2009-01-29 Meltex Inc プリント配線板製造用の埋設銅めっき方法及びその埋設銅めっき方法を用いて得られるプリント配線板
CN105612819A (zh) * 2013-10-09 2016-05-25 日立化成株式会社 多层配线基板的制造方法
US10076044B2 (en) 2013-10-09 2018-09-11 Hitachi Chemical Company, Ltd. Method for manufacturing multilayer wiring substrate
EP3439441A1 (en) * 2017-07-31 2019-02-06 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Method and plater arrangement for failure-free copper filling of a hole in a component carrier
EP4063533A1 (en) * 2021-03-25 2022-09-28 Atotech Deutschland GmbH & Co. KG A process for electrochemical deposition of copper with different current densities

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6241641B2 (ja) * 2013-03-28 2017-12-06 日立化成株式会社 多層配線基板の製造方法
CN103533776A (zh) * 2013-09-18 2014-01-22 金悦通电子（翁源）有限公司 一种嵌入式pcb的制作方法
JP6350063B2 (ja) * 2013-10-09 2018-07-04 日立化成株式会社 多層配線基板
CN104661446A (zh) * 2015-02-10 2015-05-27 深圳市五株科技股份有限公司 电路板加工方法
JP6641717B2 (ja) 2015-04-08 2020-02-05 日立化成株式会社 多層配線基板の製造方法
US10508357B2 (en) 2016-02-15 2019-12-17 Rohm And Haas Electronic Materials Llc Method of filling through-holes to reduce voids and other defects
US10512174B2 (en) * 2016-02-15 2019-12-17 Rohm And Haas Electronic Materials Llc Method of filling through-holes to reduce voids and other defects

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003060330A (ja) * 2001-08-08 2003-02-28 Toyota Industries Corp ビアホールのスミア除去方法
JP2003060349A (ja) * 2001-08-08 2003-02-28 Toyota Industries Corp ビアホールの銅メッキ方法
JP2003318544A (ja) * 2002-04-22 2003-11-07 Toppan Printing Co Ltd 多層配線基板およびその製造方法
JP2004128177A (ja) * 2002-10-02 2004-04-22 Hitachi Cable Ltd 配線板の製造方法及び配線板、ならびに半導体装置
JP2004128053A (ja) * 2002-09-30 2004-04-22 Sumitomo Bakelite Co Ltd 多層プリント配線板の製造方法
JP2006114787A (ja) * 2004-10-15 2006-04-27 Sumitomo Bakelite Co Ltd 回路基板の製造方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1132500A3 (en) * 2000-03-08 2002-01-23 Applied Materials, Inc. Method for electrochemical deposition of metal using modulated waveforms
JP3780302B2 (ja) * 2002-02-27 2006-05-31 株式会社関東学院大学表面工学研究所 ビアホール及びスルーホールを有する基板のめっき方法
JP5247252B2 (ja) * 2007-06-15 2013-07-24 メルテックス株式会社 プリント配線板製造用の埋設銅めっき方法及びその埋設銅めっき方法を用いて得られるプリント配線板

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003060330A (ja) * 2001-08-08 2003-02-28 Toyota Industries Corp ビアホールのスミア除去方法
JP2003060349A (ja) * 2001-08-08 2003-02-28 Toyota Industries Corp ビアホールの銅メッキ方法
JP2003318544A (ja) * 2002-04-22 2003-11-07 Toppan Printing Co Ltd 多層配線基板およびその製造方法
JP2004128053A (ja) * 2002-09-30 2004-04-22 Sumitomo Bakelite Co Ltd 多層プリント配線板の製造方法
JP2004128177A (ja) * 2002-10-02 2004-04-22 Hitachi Cable Ltd 配線板の製造方法及び配線板、ならびに半導体装置
JP2006114787A (ja) * 2004-10-15 2006-04-27 Sumitomo Bakelite Co Ltd 回路基板の製造方法

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009021581A (ja) * 2007-06-15 2009-01-29 Meltex Inc プリント配線板製造用の埋設銅めっき方法及びその埋設銅めっき方法を用いて得られるプリント配線板
CN105612819A (zh) * 2013-10-09 2016-05-25 日立化成株式会社 多层配线基板的制造方法
US10076044B2 (en) 2013-10-09 2018-09-11 Hitachi Chemical Company, Ltd. Method for manufacturing multilayer wiring substrate
US10165691B2 (en) 2013-10-09 2018-12-25 Hitachi Chemical Company, Ltd. Method for manufacturing multilayer wiring substrate
EP3439441A1 (en) * 2017-07-31 2019-02-06 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Method and plater arrangement for failure-free copper filling of a hole in a component carrier
US10455704B2 (en) 2017-07-31 2019-10-22 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Method for copper filling of a hole in a component carrier
EP4063533A1 (en) * 2021-03-25 2022-09-28 Atotech Deutschland GmbH & Co. KG A process for electrochemical deposition of copper with different current densities

Also Published As

Publication number Publication date
JP5247252B2 (ja) 2013-07-24
JP2009021581A (ja) 2009-01-29
CN103444275A (zh) 2013-12-11

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