WO2008149833A1 - 薄膜トランジスタ製造方法、液晶表示装置製造方法、電極形成方法 - Google Patents

薄膜トランジスタ製造方法、液晶表示装置製造方法、電極形成方法 Download PDF

Info

Publication number
WO2008149833A1
WO2008149833A1 PCT/JP2008/060125 JP2008060125W WO2008149833A1 WO 2008149833 A1 WO2008149833 A1 WO 2008149833A1 JP 2008060125 W JP2008060125 W JP 2008060125W WO 2008149833 A1 WO2008149833 A1 WO 2008149833A1
Authority
WO
WIPO (PCT)
Prior art keywords
thin film
manufacturing
liquid crystal
crystal display
film transistor
Prior art date
Application number
PCT/JP2008/060125
Other languages
English (en)
French (fr)
Inventor
Satoru Takasawa
Yuuichi Oishi
Miho Shimizu
Tooru Kikuchi
Satoru Ishibashi
Original Assignee
Ulvac, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ulvac, Inc. filed Critical Ulvac, Inc.
Priority to CN200880018891.6A priority Critical patent/CN101681932B/zh
Priority to JP2009517855A priority patent/JP5424876B2/ja
Priority to KR1020097025429A priority patent/KR101101733B1/ko
Priority to DE112008001523T priority patent/DE112008001523T5/de
Publication of WO2008149833A1 publication Critical patent/WO2008149833A1/ja
Priority to US12/630,245 priority patent/US20100075475A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Optics & Photonics (AREA)
  • Thin Film Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

基板やシリコン層から電極が剥離するのを防止する。銅を主成分とする第一の銅薄膜１３を、アンモニアガスに曝して表面処理を行ってから、処理対象物１０が配置された雰囲気に、シランガスとアンモニアガスとを含む原料ガスのプラズマを発生させ、第一の銅薄膜１３の表面に窒化ケイ素膜を形成する。アンモニアガスで予め表面処理されることで、第一の銅薄膜１３にシランガスが拡散するのが防止されるから、表面処理された第一の銅薄膜１３で構成される電極は、ガラス基板１１やシリコン層から剥離せず、しかも、電気抵抗値も高くならない。
PCT/JP2008/060125 2007-06-05 2008-06-02 薄膜トランジスタ製造方法、液晶表示装置製造方法、電極形成方法 WO2008149833A1 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
CN200880018891.6A CN101681932B (zh) 2007-06-05 2008-06-02 薄膜晶体管制造方法、液晶显示装置制造方法、电极形成方法
JP2009517855A JP5424876B2 (ja) 2007-06-05 2008-06-02 薄膜トランジスタ製造方法、液晶表示装置製造方法、電極形成方法
KR1020097025429A KR101101733B1 (ko) 2007-06-05 2008-06-02 박막 트랜지스터 제조 방법, 액정 표시 장치 제조 방법, 전극 형성 방법
DE112008001523T DE112008001523T5 (de) 2007-06-05 2008-06-02 Verfahren zur Herstellung eines Dünnschichttransistors, Verfahren zur Herstellung einer Flüssigkristallanzeigevorrichtung und Verfahren zur Bildung einer Elektrode
US12/630,245 US20100075475A1 (en) 2007-06-05 2009-12-03 Method for producing a thin film transistor and method for forming an electrode

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007148787 2007-06-05
JP2007-148787 2007-06-05

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/630,245 Continuation US20100075475A1 (en) 2007-06-05 2009-12-03 Method for producing a thin film transistor and method for forming an electrode

Publications (1)

Publication Number Publication Date
WO2008149833A1 true WO2008149833A1 (ja) 2008-12-11

Family

ID=40093649

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/060125 WO2008149833A1 (ja) 2007-06-05 2008-06-02 薄膜トランジスタ製造方法、液晶表示装置製造方法、電極形成方法

Country Status (7)

Country Link
US (1) US20100075475A1 (ja)
JP (1) JP5424876B2 (ja)
KR (1) KR101101733B1 (ja)
CN (1) CN101681932B (ja)
DE (1) DE112008001523T5 (ja)
TW (1) TW200915399A (ja)
WO (1) WO2008149833A1 (ja)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102097313B (zh) * 2010-11-23 2012-12-12 深圳市华星光电技术有限公司 保护层及薄膜晶体管矩阵基板的制造方法
CN102386237A (zh) * 2011-11-23 2012-03-21 深圳市华星光电技术有限公司 一种薄膜晶体管、阵列基板及装置和一种制备方法
CN103700667B (zh) * 2013-12-18 2017-02-01 北京京东方光电科技有限公司 一种像素阵列结构及其制作方法、阵列基板和显示装置

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001176878A (ja) * 1999-12-21 2001-06-29 Furontekku:Kk 銅配線基板およびその製造方法ならびに液晶表示装置
JP2006178445A (ja) * 2004-12-20 2006-07-06 Samsung Electronics Co Ltd 薄膜トランジスタ表示板及びその製造方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6464338A (en) * 1987-09-04 1989-03-10 Hitachi Ltd Wiring for semiconductor device
JPH06333925A (ja) * 1993-05-20 1994-12-02 Nippon Steel Corp 半導体集積回路及びその製造方法
JPH07326756A (ja) * 1994-05-30 1995-12-12 Kyocera Corp 薄膜トランジスタおよびその製造方法
JPH0826889A (ja) * 1994-07-15 1996-01-30 Fujitsu Ltd 金属膜の形成方法および配線用金属膜
JP3417751B2 (ja) * 1995-02-13 2003-06-16 株式会社東芝 半導体装置の製造方法
JP3403918B2 (ja) * 1997-06-02 2003-05-06 株式会社ジャパンエナジー 高純度銅スパッタリングタ−ゲットおよび薄膜
US6777331B2 (en) * 2000-03-07 2004-08-17 Simplus Systems Corporation Multilayered copper structure for improving adhesion property
JP2002353222A (ja) 2001-05-29 2002-12-06 Sharp Corp 金属配線、それを備えた薄膜トランジスタおよび表示装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001176878A (ja) * 1999-12-21 2001-06-29 Furontekku:Kk 銅配線基板およびその製造方法ならびに液晶表示装置
JP2006178445A (ja) * 2004-12-20 2006-07-06 Samsung Electronics Co Ltd 薄膜トランジスタ表示板及びその製造方法

Also Published As

Publication number Publication date
CN101681932A (zh) 2010-03-24
JP5424876B2 (ja) 2014-02-26
CN101681932B (zh) 2012-11-14
US20100075475A1 (en) 2010-03-25
JPWO2008149833A1 (ja) 2010-08-26
DE112008001523T5 (de) 2010-04-29
KR20100003370A (ko) 2010-01-08
KR101101733B1 (ko) 2012-01-05
TW200915399A (en) 2009-04-01

Similar Documents

Publication Publication Date Title
TW200712251A (en) Protection film structure for a metal member, metal parts using the protection film structure, and semiconductor of flat display production apparatus using the protection film structure
WO2008073926A3 (en) Formation of epitaxial layers containing silicon
WO2011028349A3 (en) Remote hydrogen plasma source of silicon containing film deposition
TW200636822A (en) Structure and method for manufacturing strained silicon directly-on insulator substrate with hybrid crystalling orientation and different stress levels
EP1998369A3 (en) Semiconductor substrate and manufacturing method of semiconductor device
TW200509183A (en) Semiconductor device and process for fabricating the same
TW200717611A (en) Film formation method and apparatus for semiconductor process
TW200510883A (en) Low temperature process for TFTfabrication
WO2012024114A3 (en) Methods for forming a hydrogen free silicon containing dielectric film
WO2009019837A1 (ja) 炭化珪素半導体素子およびその製造方法
DE60223662D1 (de) Abscheidungsverfahren auf mischsubstraten mittels trisilan
WO2008117739A1 (ja) 半導体デバイス、多結晶半導体薄膜、多結晶半導体薄膜の製造方法、電界効果型トランジスタ、及び、電界効果型トランジスタの製造方法
TW200636827A (en) Silicon oxide cap over high dielectric constant films
TW200704819A (en) Method for silicon based dielectric chemical vapor deposition
SG157304A1 (en) High shrinkage stress silicon nitride (sin) layer for nfet improvement
SG130146A1 (en) Source/drain electrodes, thin-film transistor substrates, manufacture methods thereof, and display devices
TW200703469A (en) Method to increase the compressive stress of PECVD silicon nitride films
TW200943389A (en) Selective formation of silicon carbon epitaxial layer
TW200709309A (en) Semiconductor device and manufacturing method thereof
TW200715380A (en) Process for lateral disjonting of a semiconductor wafer and opto-electronic element
JP2009010351A5 (ja)
WO2011050015A3 (en) Three-stage formation of thin-films for photovoltaic devices
TW200746354A (en) Multi-step anneal of thin films for film densification and improved gap-fill
TW200634927A (en) Method of manufacturing semiconductor device
TW200640283A (en) Method of manufacturing an organic electronic device

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 200880018891.6

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 08777076

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2009517855

Country of ref document: JP

Kind code of ref document: A

ENP Entry into the national phase

Ref document number: 20097025429

Country of ref document: KR

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: 1120080015236

Country of ref document: DE

RET De translation (de og part 6b)

Ref document number: 112008001523

Country of ref document: DE

Date of ref document: 20100429

Kind code of ref document: P

122 Ep: pct application non-entry in european phase

Ref document number: 08777076

Country of ref document: EP

Kind code of ref document: A1