WO2008149446A1 - 半導体製造装置および方法 - Google Patents

半導体製造装置および方法 Download PDF

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Publication number
WO2008149446A1
WO2008149446A1 PCT/JP2007/061570 JP2007061570W WO2008149446A1 WO 2008149446 A1 WO2008149446 A1 WO 2008149446A1 JP 2007061570 W JP2007061570 W JP 2007061570W WO 2008149446 A1 WO2008149446 A1 WO 2008149446A1
Authority
WO
WIPO (PCT)
Prior art keywords
treating chamber
film
chamber
dielectric constant
high dielectric
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2007/061570
Other languages
English (en)
French (fr)
Inventor
Naomu Kitano
Takashi Minami
Motomu Kosuda
Heiji Watanabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Anelva Corp
Original Assignee
Canon Anelva Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Anelva Corp filed Critical Canon Anelva Corp
Priority to PCT/JP2007/061570 priority Critical patent/WO2008149446A1/ja
Priority to TW097112008A priority patent/TWI392022B/zh
Publication of WO2008149446A1 publication Critical patent/WO2008149446A1/ja
Priority to US12/631,286 priority patent/US8088678B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/04—Apparatus for manufacture or treatment
    • H10P72/0451—Apparatus for manufacturing or treating in a plurality of work-stations
    • H10P72/0468—Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01332—Making the insulator
    • H10D64/0135—Making the insulator by deposition of a layer, e.g. metal, metal compound or polysilicon, followed by transformation thereof into the insulator
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
    • H10D64/685—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered being perpendicular to the channel plane
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302—Non-deposition formation processes
    • H10P14/6304—Formation by oxidation, e.g. oxidation of the substrate
    • H10P14/6314—Formation by oxidation, e.g. oxidation of the substrate of a metallic layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302—Non-deposition formation processes
    • H10P14/6322—Formation by thermal treatments
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/6928—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides
    • H10P14/693—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides the material containing hafnium, e.g. HfSiOx or HfSiON

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Formation Of Insulating Films (AREA)
  • Chemical Vapour Deposition (AREA)
  • Physical Vapour Deposition (AREA)

Abstract

本発明の第１の側面は、ロードロック室と搬送室とプラズマを用いた処理を行う処理室1と処理室2を有し、処理室2においては、排気手段に、酸素分圧が1×10-5[Pa]以下にするための制御手段が取り付けられていることを特徴とする半導体製造装置である。本発明の第２の側面は、高誘電率膜と金属電極を連続で形成する方法であって、処理室1で、シリコン酸化膜または、シリコン酸窒化膜上に金属膜を堆積させるステップ1と処理室2において処理室1で形成した金属膜を用いて高誘電率膜に形成するステップ2と処理室1もしくは、増設した処理室3において処理室2で形成した高誘電膜上に金属電極材料を堆積させるステップ3を含む方法において、大気に晒すことなく、各ステップが連続的に行われることを特徴とする。
PCT/JP2007/061570 2007-06-07 2007-06-07 半導体製造装置および方法 Ceased WO2008149446A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
PCT/JP2007/061570 WO2008149446A1 (ja) 2007-06-07 2007-06-07 半導体製造装置および方法
TW097112008A TWI392022B (zh) 2007-06-07 2008-04-02 Semiconductor device manufacturing apparatus and method
US12/631,286 US8088678B2 (en) 2007-06-07 2009-12-04 Semiconductor manufacturing apparatus and method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/061570 WO2008149446A1 (ja) 2007-06-07 2007-06-07 半導体製造装置および方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/631,286 Continuation US8088678B2 (en) 2007-06-07 2009-12-04 Semiconductor manufacturing apparatus and method

Publications (1)

Publication Number Publication Date
WO2008149446A1 true WO2008149446A1 (ja) 2008-12-11

Family

ID=40093281

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/061570 Ceased WO2008149446A1 (ja) 2007-06-07 2007-06-07 半導体製造装置および方法

Country Status (3)

Country Link
US (1) US8088678B2 (ja)
TW (1) TWI392022B (ja)
WO (1) WO2008149446A1 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019515490A (ja) * 2016-04-20 2019-06-06 トルンプフ フォトニクス インコーポレイテッドＴｒｕｍｐｆ Ｐｈｏｔｏｎｉｃｓ Ｉｎｃ． レーザ切子面のパッシベーションおよび当該パッシベーションを実施するためのシステム

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110042209A1 (en) 2008-06-25 2011-02-24 Canon Anelva Corporation Sputtering apparatus and recording medium for recording control program thereof
WO2010008021A1 (ja) * 2008-07-15 2010-01-21 キヤノンアネルバ株式会社 プラズマ処理方法及びプラズマ処理装置
WO2010050292A1 (ja) * 2008-10-31 2010-05-06 キヤノンアネルバ株式会社 誘電体膜ならびに半導体装置の製造方法、誘電体膜、および、記録媒体
WO2010050291A1 (ja) 2008-10-31 2010-05-06 キヤノンアネルバ株式会社 誘電体膜、誘電体膜の製造方法、半導体装置、および、記録媒体
JP5247619B2 (ja) * 2009-07-28 2013-07-24 キヤノンアネルバ株式会社 誘電体膜、誘電体膜を用いた半導体装置の製造方法及び半導体製造装置
JP2011151366A (ja) 2009-12-26 2011-08-04 Canon Anelva Corp 誘電体膜の製造方法
JP5937297B2 (ja) * 2010-03-01 2016-06-22 キヤノンアネルバ株式会社 金属窒化膜、該金属窒化膜を用いた半導体装置、および半導体装置の製造方法
JP5458177B2 (ja) 2010-12-28 2014-04-02 キヤノンアネルバ株式会社 半導体装置の製造方法および装置
US9305998B2 (en) * 2013-02-11 2016-04-05 Texas Instruments Incorporated Adhesion of ferroelectric material to underlying conductive capacitor plate
TWI635539B (zh) * 2017-09-15 2018-09-11 Corremax International Co., Ltd. 高介電常數介電層、其製造方法及執行該方法之多功能設備
US10998209B2 (en) 2019-05-31 2021-05-04 Applied Materials, Inc. Substrate processing platforms including multiple processing chambers
WO2021132010A1 (ja) * 2019-12-24 2021-07-01 東京エレクトロン株式会社 成膜方法及び成膜システム
US12080571B2 (en) 2020-07-08 2024-09-03 Applied Materials, Inc. Substrate processing module and method of moving a workpiece
US11749542B2 (en) 2020-07-27 2023-09-05 Applied Materials, Inc. Apparatus, system, and method for non-contact temperature monitoring of substrate supports
US11817331B2 (en) 2020-07-27 2023-11-14 Applied Materials, Inc. Substrate holder replacement with protective disk during pasting process
US11600507B2 (en) 2020-09-09 2023-03-07 Applied Materials, Inc. Pedestal assembly for a substrate processing chamber
US11610799B2 (en) 2020-09-18 2023-03-21 Applied Materials, Inc. Electrostatic chuck having a heating and chucking capabilities
US12195314B2 (en) 2021-02-02 2025-01-14 Applied Materials, Inc. Cathode exchange mechanism to improve preventative maintenance time for cluster system
US11674227B2 (en) 2021-02-03 2023-06-13 Applied Materials, Inc. Symmetric pump down mini-volume with laminar flow cavity gas injection for high and low pressure
US12002668B2 (en) 2021-06-25 2024-06-04 Applied Materials, Inc. Thermal management hardware for uniform temperature control for enhanced bake-out for cluster tool
US20230323524A1 (en) * 2022-04-07 2023-10-12 Cantech Inc. Quartz crystal sensor coated with gold-aluminum by magnetron sputtering

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002184773A (ja) * 2000-12-19 2002-06-28 Nec Corp 高誘電率薄膜の成膜方法及び高誘電率薄膜を用いた半導体装置の製造方法
JP2003249497A (ja) * 2001-12-18 2003-09-05 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
WO2004008544A1 (ja) * 2002-07-16 2004-01-22 Nec Corporation 半導体装置、その製造方法およびその製造装置
JP2006237371A (ja) * 2005-02-25 2006-09-07 Canon Anelva Corp ｈｉｇｈ−Ｋ誘電膜上に金属ゲートを蒸着する方法及び、ｈｉｇｈ−Ｋ誘電膜と金属ゲートとの界面を向上させる方法、並びに、基板処理システム

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5882165A (en) * 1986-12-19 1999-03-16 Applied Materials, Inc. Multiple chamber integrated process system
US6440261B1 (en) * 1999-05-25 2002-08-27 Applied Materials, Inc. Dual buffer chamber cluster tool for semiconductor wafer processing
JP3944367B2 (ja) * 2001-02-06 2007-07-11 松下電器産業株式会社 絶縁膜の形成方法及び半導体装置の製造方法
US20030029715A1 (en) * 2001-07-25 2003-02-13 Applied Materials, Inc. An Apparatus For Annealing Substrates In Physical Vapor Deposition Systems
US20030124873A1 (en) * 2001-12-28 2003-07-03 Guangcai Xing Method of annealing an oxide film
US7824990B2 (en) * 2005-12-05 2010-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-metal-oxide high-K gate dielectrics

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002184773A (ja) * 2000-12-19 2002-06-28 Nec Corp 高誘電率薄膜の成膜方法及び高誘電率薄膜を用いた半導体装置の製造方法
JP2003249497A (ja) * 2001-12-18 2003-09-05 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
WO2004008544A1 (ja) * 2002-07-16 2004-01-22 Nec Corporation 半導体装置、その製造方法およびその製造装置
JP2006237371A (ja) * 2005-02-25 2006-09-07 Canon Anelva Corp ｈｉｇｈ−Ｋ誘電膜上に金属ゲートを蒸着する方法及び、ｈｉｇｈ−Ｋ誘電膜と金属ゲートとの界面を向上させる方法、並びに、基板処理システム

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019515490A (ja) * 2016-04-20 2019-06-06 トルンプフ フォトニクス インコーポレイテッドＴｒｕｍｐｆ Ｐｈｏｔｏｎｉｃｓ Ｉｎｃ． レーザ切子面のパッシベーションおよび当該パッシベーションを実施するためのシステム

Also Published As

Publication number Publication date
US8088678B2 (en) 2012-01-03
TWI392022B (zh) 2013-04-01
TW200903639A (en) 2009-01-16
US20100120238A1 (en) 2010-05-13

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