WO2008139509A1 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
WO2008139509A1
WO2008139509A1 PCT/JP2007/000514 JP2007000514W WO2008139509A1 WO 2008139509 A1 WO2008139509 A1 WO 2008139509A1 JP 2007000514 W JP2007000514 W JP 2007000514W WO 2008139509 A1 WO2008139509 A1 WO 2008139509A1
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WO
WIPO (PCT)
Prior art keywords
silicon substrate
side wall
insulating film
wall spacer
semiconductor device
Prior art date
Application number
PCT/JP2007/000514
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English (en)
French (fr)
Inventor
Naoyoshi Tamura
Original Assignee
Fujitsu Microelectronics Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Microelectronics Limited filed Critical Fujitsu Microelectronics Limited
Priority to PCT/JP2007/000514 priority Critical patent/WO2008139509A1/ja
Priority to JP2009513855A priority patent/JP5168274B2/ja
Publication of WO2008139509A1 publication Critical patent/WO2008139509A1/ja
Priority to US12/606,720 priority patent/US8071435B2/en
Priority to US13/283,331 priority patent/US8247284B2/en
Priority to US13/283,312 priority patent/US8247283B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/933—Germanium or silicon or Ge-Si on III-V

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

　チャネルに有効に応力を印加でき、製造工程が安定な半導体装置の製造方法を提供する。 　半導体装置の製造方法は、（ａ）シリコン基板上にゲート絶縁膜を介してゲート電極を形成する工程と、（ｂ）ゲート電極およびゲート絶縁膜の側壁上に、エッチング特性の異なる絶縁膜と犠牲膜とを含む積層を形成し、異方性エッチングを行なってサイドウォールスペーサを形成する工程と、（ｃ）サイドウォールスペーサの両側のシリコン基板に不純物を注入する工程と、（ｄ）シリコン基板をエッチングすると共に、犠牲膜をエッチングし、シリコン基板にリセスを形成すると共に、サイドウォールスペーサの断面を略Ｌ字状に加工する工程と、（ｅ）リセスにＳｉ－Ｇｅを含む結晶をエピタキシャルに成長する工程と、（ｆ）サイドウォールスペーサを覆って応力を内蔵した絶縁膜を堆積する工程と、を含む。
PCT/JP2007/000514 2007-05-14 2007-05-14 半導体装置の製造方法 WO2008139509A1 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
PCT/JP2007/000514 WO2008139509A1 (ja) 2007-05-14 2007-05-14 半導体装置の製造方法
JP2009513855A JP5168274B2 (ja) 2007-05-14 2007-05-14 半導体装置の製造方法
US12/606,720 US8071435B2 (en) 2007-05-14 2009-10-27 Manufacture of semiconductor device with stress structure
US13/283,331 US8247284B2 (en) 2007-05-14 2011-10-27 Manufacture of semiconductor device with stress structure
US13/283,312 US8247283B2 (en) 2007-05-14 2011-10-27 Manufacture of semiconductor device with stress structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/000514 WO2008139509A1 (ja) 2007-05-14 2007-05-14 半導体装置の製造方法

Related Child Applications (1)

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US12/606,720 Continuation US8071435B2 (en) 2007-05-14 2009-10-27 Manufacture of semiconductor device with stress structure

Publications (1)

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WO2008139509A1 true WO2008139509A1 (ja) 2008-11-20

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US (3) US8071435B2 (ja)
JP (1) JP5168274B2 (ja)
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2005013374A1 (ja) * 2003-08-05 2006-09-28 富士通株式会社 半導体装置および半導体装置の製造方法
JP2009026795A (ja) * 2007-07-17 2009-02-05 Renesas Technology Corp 半導体装置およびその製造方法
JP2009088069A (ja) * 2007-09-28 2009-04-23 Panasonic Corp 半導体装置及びその製造方法

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DE102009031114B4 (de) * 2009-06-30 2011-07-07 Globalfoundries Dresden Module One LLC & CO. KG, 01109 Halbleiterelement, das in einem kristallinen Substratmaterial hergestellt ist und ein eingebettetes in-situ n-dotiertes Halbleitermaterial aufweist, und Verfahren zur Herstellung desselben
JP5159828B2 (ja) 2010-05-21 2013-03-13 パナソニック株式会社 半導体装置
KR101776926B1 (ko) 2010-09-07 2017-09-08 삼성전자주식회사 반도체 소자 및 그 제조 방법
US8460981B2 (en) * 2010-09-28 2013-06-11 International Business Machines Corporation Use of contacts to create differential stresses on devices
US8815671B2 (en) 2010-09-28 2014-08-26 International Business Machines Corporation Use of contacts to create differential stresses on devices
US20120086068A1 (en) * 2010-10-06 2012-04-12 Synopsys Inc. Method for depositing a dielectric onto a floating gate for strained semiconductor devices
DE102010063772B4 (de) * 2010-12-21 2016-02-04 GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG Verfahren zum Einbetten einer sigma-förmigen Halbleiterlegierung in Transistoren durch Anwenden einer gleichmäßigen Oxidschicht vor dem Ätzen der Aussparungen
CN103681846B (zh) * 2012-09-20 2017-02-08 中芯国际集成电路制造(上海)有限公司 半导体装置及其制造方法
KR102059526B1 (ko) 2012-11-22 2019-12-26 삼성전자주식회사 내장 스트레서를 갖는 반도체 소자 형성 방법 및 관련된 소자
TWI605592B (zh) 2012-11-22 2017-11-11 三星電子股份有限公司 在凹處包括一應力件的半導體裝置及其形成方法（二）
DE102013212054A1 (de) 2013-06-25 2015-01-08 Robert Bosch Gmbh Verfahren und Vorrichtung zum Betreiben einer Asynchronmaschine, Asynchronmaschine
US9978833B2 (en) * 2016-03-11 2018-05-22 Samsung Electronics Co., Ltd. Methods for varied strain on nano-scale field effect transistor devices
US9960084B1 (en) * 2016-11-01 2018-05-01 United Microelectronics Corp. Method for forming semiconductor device
US10079290B2 (en) * 2016-12-30 2018-09-18 United Microelectronics Corp. Semiconductor device having asymmetric spacer structures
US10741497B2 (en) * 2018-02-15 2020-08-11 Globalfoundries Inc. Contact and interconnect structures

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US20030080361A1 (en) * 2001-11-01 2003-05-01 Anand Murthy Semiconductor transistor having a stressed channel
US20060014354A1 (en) * 2004-07-14 2006-01-19 Yun-Hsiu Chen Method of making transistor with strained source/drain
JP2006202951A (ja) * 2005-01-20 2006-08-03 Fujitsu Ltd Ｍｏｓ型電界効果トランジスタ及びその製造方法
JP2006303501A (ja) * 2005-04-18 2006-11-02 Toshiba Corp ＰＦＥＴの移動度を強化したステップ埋め込みＳｉＧｅ構造
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2005013374A1 (ja) * 2003-08-05 2006-09-28 富士通株式会社 半導体装置および半導体装置の製造方法
JP2009026795A (ja) * 2007-07-17 2009-02-05 Renesas Technology Corp 半導体装置およびその製造方法
JP2009088069A (ja) * 2007-09-28 2009-04-23 Panasonic Corp 半導体装置及びその製造方法

Also Published As

Publication number Publication date
JP5168274B2 (ja) 2013-03-21
US20120040502A1 (en) 2012-02-16
JPWO2008139509A1 (ja) 2010-07-29
US8071435B2 (en) 2011-12-06
US8247284B2 (en) 2012-08-21
US20100047978A1 (en) 2010-02-25
US8247283B2 (en) 2012-08-21
US20120045878A1 (en) 2012-02-23

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