WO2008126891A1 - ドライエッチング方法 - Google Patents

ドライエッチング方法 Download PDF

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Publication number
WO2008126891A1
WO2008126891A1 PCT/JP2008/057066 JP2008057066W WO2008126891A1 WO 2008126891 A1 WO2008126891 A1 WO 2008126891A1 JP 2008057066 W JP2008057066 W JP 2008057066W WO 2008126891 A1 WO2008126891 A1 WO 2008126891A1
Authority
WO
WIPO (PCT)
Prior art keywords
side wall
hole
recess
insulating layer
dry etching
Prior art date
Application number
PCT/JP2008/057066
Other languages
English (en)
French (fr)
Inventor
Yasuhiro Morikawa
Koukou Suu
Original Assignee
Ulvac, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ulvac, Inc. filed Critical Ulvac, Inc.
Priority to JP2009509366A priority Critical patent/JP5268112B2/ja
Priority to US12/594,966 priority patent/US20100062606A1/en
Priority to EP08740167A priority patent/EP2136391A4/en
Priority to AU2008239010A priority patent/AU2008239010B2/en
Priority to CN2008800116513A priority patent/CN101652841B/zh
Publication of WO2008126891A1 publication Critical patent/WO2008126891A1/ja

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Inorganic Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

【課題】絶縁層へのノッチの発生を抑制できるとともに、高精度な微細加工を実現できるドライエッチング方法を提供する。 【解決手段】本発明に係るドライエッチング方法は、シリコン酸化物からなる絶縁層２３の上に半導体層２１が形成された基板を準備し、半導体層２１に貫通孔２５を形成し、貫通孔２５を介して露出する絶縁層２３の領域をエッチングすることで絶縁層２３に凹所２６を形成しながら、貫通孔２５および凹所２６の側壁に樹脂膜２７を形成する。凹所２６の側壁に樹脂膜２７が形成されることにより、凹所２６の側壁がプラズマ中のイオンの衝突から保護され、凹所側壁へのノッチの発生が抑制される。また、貫通孔２５の側壁に樹脂膜２７が形成されることにより、貫通孔２５の側壁がプラズマ中のイオンの衝突から保護され、貫通孔２５の孔形状の変動が防止される。
PCT/JP2008/057066 2007-04-11 2008-04-10 ドライエッチング方法 WO2008126891A1 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2009509366A JP5268112B2 (ja) 2007-04-11 2008-04-10 ドライエッチング方法
US12/594,966 US20100062606A1 (en) 2007-04-11 2008-04-10 Dry etching method
EP08740167A EP2136391A4 (en) 2007-04-11 2008-04-10 dry
AU2008239010A AU2008239010B2 (en) 2007-04-11 2008-04-10 Dry etching method
CN2008800116513A CN101652841B (zh) 2007-04-11 2008-04-10 干蚀刻方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-103512 2007-04-11
JP2007103512 2007-04-11

Publications (1)

Publication Number Publication Date
WO2008126891A1 true WO2008126891A1 (ja) 2008-10-23

Family

ID=39863986

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/057066 WO2008126891A1 (ja) 2007-04-11 2008-04-10 ドライエッチング方法

Country Status (8)

Country Link
US (1) US20100062606A1 (ja)
EP (1) EP2136391A4 (ja)
JP (1) JP5268112B2 (ja)
KR (1) KR101097821B1 (ja)
CN (1) CN101652841B (ja)
AU (1) AU2008239010B2 (ja)
TW (1) TW200901312A (ja)
WO (1) WO2008126891A1 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012146700A (ja) * 2011-01-06 2012-08-02 Ulvac Japan Ltd プラズマエッチング方法、及びプラズマエッチング装置

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US8158522B2 (en) * 2009-09-25 2012-04-17 Applied Materials, Inc. Method of forming a deep trench in a substrate
US8946076B2 (en) * 2013-03-15 2015-02-03 Micron Technology, Inc. Methods of fabricating integrated structures, and methods of forming vertically-stacked memory cells
KR102235443B1 (ko) 2014-01-10 2021-04-02 삼성디스플레이 주식회사 박막 트랜지스터 표시판 및 그 제조 방법
CN105448697B (zh) * 2014-07-18 2018-05-01 中微半导体设备(上海)有限公司 高深宽比结构的刻蚀方法及mems器件的制作方法
KR101539197B1 (ko) * 2015-02-05 2015-07-24 주식회사 스탠딩에그 Ｚ축 움직임 성능을 개선하고 구조물 깊이 편차를 최소화하는 마이크로머시닝 방법 및 이를 이용한 가속도 센서
US10569071B2 (en) 2015-08-31 2020-02-25 Ethicon Llc Medicant eluting adjuncts and methods of using medicant eluting adjuncts
US10285692B2 (en) * 2015-08-31 2019-05-14 Ethicon Llc Adjuncts for surgical devices including agonists and antagonists
TWI812762B (zh) * 2018-07-30 2023-08-21 日商東京威力科創股份有限公司 處理被處理體之方法、處理裝置及處理系統
JP7478059B2 (ja) * 2020-08-05 2024-05-02 株式会社アルバック シリコンのドライエッチング方法

Citations (7)

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Publication number Priority date Publication date Assignee Title
JPH11219938A (ja) 1998-02-02 1999-08-10 Matsushita Electron Corp プラズマエッチング方法
JP2001313337A (ja) * 2000-02-23 2001-11-09 Sanyo Electric Co Ltd 半導体装置及びその製造方法
JP2002062246A (ja) * 2000-08-17 2002-02-28 Mitsutoyo Corp カンチレバーの製造方法
JP2003100641A (ja) * 2001-09-26 2003-04-04 Toshiba Corp 半導体装置用基板を製造する方法および半導体装置用基板
JP2003203967A (ja) 2001-12-28 2003-07-18 Toshiba Corp 部分ｓｏｉウェーハの製造方法、半導体装置及びその製造方法
WO2006003962A1 (ja) * 2004-07-02 2006-01-12 Ulvac, Inc. エッチング方法及び装置
JP2007059696A (ja) * 2005-08-25 2007-03-08 Hitachi High-Technologies Corp エッチング方法およびエッチング装置

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Publication number Priority date Publication date Assignee Title
JPH11219938A (ja) 1998-02-02 1999-08-10 Matsushita Electron Corp プラズマエッチング方法
JP2001313337A (ja) * 2000-02-23 2001-11-09 Sanyo Electric Co Ltd 半導体装置及びその製造方法
JP2002062246A (ja) * 2000-08-17 2002-02-28 Mitsutoyo Corp カンチレバーの製造方法
JP2003100641A (ja) * 2001-09-26 2003-04-04 Toshiba Corp 半導体装置用基板を製造する方法および半導体装置用基板
JP2003203967A (ja) 2001-12-28 2003-07-18 Toshiba Corp 部分ｓｏｉウェーハの製造方法、半導体装置及びその製造方法
WO2006003962A1 (ja) * 2004-07-02 2006-01-12 Ulvac, Inc. エッチング方法及び装置
JP2007059696A (ja) * 2005-08-25 2007-03-08 Hitachi High-Technologies Corp エッチング方法およびエッチング装置

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Title
See also references of EP2136391A4

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012146700A (ja) * 2011-01-06 2012-08-02 Ulvac Japan Ltd プラズマエッチング方法、及びプラズマエッチング装置

Also Published As

Publication number Publication date
AU2008239010A1 (en) 2008-10-23
KR20090125174A (ko) 2009-12-03
US20100062606A1 (en) 2010-03-11
JPWO2008126891A1 (ja) 2010-07-22
EP2136391A4 (en) 2012-12-19
CN101652841A (zh) 2010-02-17
EP2136391A1 (en) 2009-12-23
KR101097821B1 (ko) 2011-12-22
TW200901312A (en) 2009-01-01
JP5268112B2 (ja) 2013-08-21
AU2008239010B2 (en) 2011-09-15
CN101652841B (zh) 2012-01-18

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