TWI484550B - Semiconductor device manufacturing method - Google Patents
Semiconductor device manufacturing method Download PDFInfo
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- TWI484550B TWI484550B TW098103679A TW98103679A TWI484550B TW I484550 B TWI484550 B TW I484550B TW 098103679 A TW098103679 A TW 098103679A TW 98103679 A TW98103679 A TW 98103679A TW I484550 B TWI484550 B TW I484550B
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- 239000004065 semiconductor Substances 0.000 title claims description 28
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 229910052751 metal Inorganic materials 0.000 claims description 66
- 239000002184 metal Substances 0.000 claims description 64
- 238000005530 etching Methods 0.000 claims description 19
- 239000011229 interlayer Substances 0.000 claims description 13
- 238000000034 method Methods 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 11
- 229910052782 aluminium Inorganic materials 0.000 claims description 10
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical group [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 229910000838 Al alloy Inorganic materials 0.000 claims description 2
- 229910052715 tantalum Inorganic materials 0.000 claims 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims 1
- 230000001681 protective effect Effects 0.000 description 19
- 238000000354 decomposition reaction Methods 0.000 description 8
- 238000001312 dry etching Methods 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000000059 patterning Methods 0.000 description 5
- 238000010276 construction Methods 0.000 description 4
- 239000000460 chlorine Substances 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
Description
本發明是有關半導體裝置的製造方法,特別是金屬配線的乾蝕刻方法。
在鋁的乾蝕刻加工中,可知從阻劑供給的阻劑分解物有助於側壁保護膜的形成,可藉由側壁保護膜來進行異方性的微細加工。蝕刻的代表性的氣體種類為Cl2
、BCl3
、HCl等的氯系。鋁是反應性高的金屬,與Cl2
分子激烈反應,蝕刻高速進行。因此,為了壓制底切(undercut),需要在圖案側壁形成保護膜。可是,一旦圖案形成微細,阻劑開口率變高,則阻劑分解物不足,側壁保護膜的形成會形成不夠充分,在蝕刻中發生底切,不能保持所被蝕刻之鋁的異方性。其結果,擔心配線的可靠度降低或斷線。其對策,如揭示於專利文獻1那樣,裝置的圖案以外,另在同一晶圓上形成虛擬的阻劑圖案,在增加阻劑量之下,補充阻劑分解物,保持鋁的異方性之方法為人所知。又,如揭示於專利文獻2那樣,在鋁蝕刻中,在鋁膜中預先導入形成側壁保護膜的雜質之例如硼元素的方法為人所知。
[專利文獻1]特開昭63-250823號公報
[專利文獻2]特開平7-45590號公報
在半導體裝置或IC的特性上,當然有阻劑開口率變高的情形。一旦晶片縮小,則可預料配線佈局的自由度變窄,難以形成被阻劑覆蓋之大的虛擬圖案。大的虛擬圖案所能夠形成的是在離開配線圖案的地方,可想像有阻劑分解物無法對側壁保護膜形成發揮效果的問題。並且,在微負載效應(micro loading effect)的影響下,在微細的配線圖案中,阻劑分解物無法供給,其結果,蝕刻時的鋁側壁的保護膜不能形成,會有鋁的異方性蝕刻困難的問題點。
本發明的目的是在於提供一種不形成大的虛擬圖案,且在配線圖案的附近配置阻劑分解物的供給源之下,鋁的異方性蝕刻可能之半導體裝置的製造方法。
為了解決上述課題,本發明的半導體裝置的製造方法,係於半導體基板上具有金屬配線的半導體裝置的製造方法,其特徵係包含:在半導體基板上形成層間絕緣膜之工程;形成供以在上述層間絕緣膜及上述半導體基板形成虛擬金屬配線之開口部的直徑為金屬膜厚與阻劑膜厚的合算膜厚的2倍以上,長寬比為1~3的溝之工程;在上述層間絕緣膜的表面及上述構的内面堆積金屬膜之工程;在上述金屬膜上形成阻劑圖案之工程;及蝕刻上述金屬膜來使上述層間絕緣膜上的金屬配線及上述溝内面及周圍的虛擬金屬配線接近形成之工程。
並且,在上述金屬膜上形成阻劑圖案的工程中,溝上的阻劑的一部份被曝光,而阻劑膜厚變薄。
而且,上述溝上的阻劑被曝光的領域係平面視為圓形或方形。
藉由利用以上的半導體裝置的製造方法,在乾蝕刻的金屬配線形成中,對於藉由蝕刻來露出的配線側面而言,因為位於接近的溝(trench)上的阻劑的表面積大,所以會從接近的溝上的阻劑來供給有機成分而形成側壁保護膜,因此可確保無側面蝕刻的異方性蝕刻,進而能夠形成具有良好的剖面形狀之金屬配線。
以下,根據圖1及圖2來說明本發明的實施形態。
圖1式表示本發明的第一實施例的工程剖面圖。
圖1(a)是表示在半導體基板102上形成半導體元件的途中的工程者,在半導體元件的接觸孔形成後形成溝100的工程的剖面圖。在半導體基板102上形成層間絕緣膜103,在層間絕緣膜上塗佈阻劑101。阻劑101會被圖案化,予以作為光罩,在下層的層間絕緣膜103及半導體基板102藉由蝕刻來形成開孔的溝100。半導體元件不具溝構造時,是如本實施例那樣在接觸孔形成後追加一片光罩來形成溝100,但若為具有溝構造的半導體元件,則可不追加光罩圖案來形成溝100。
圖1(b)是表示剝離阻劑,在層間絕緣膜103上及溝100内堆積金屬膜104的狀態之工程剖面圖。此金屬膜104是之後形成金屬配線或虛擬金屬配線者,例如純鋁中含有矽或銅的鋁合金。
圖1(c)是使乾蝕刻金屬膜時作為光罩使用的阻劑圖案化時的工程剖面圖。在金屬膜104上形成阻劑105。雖在溝100中亦有阻劑106進入,但其上部表面是形成凹陷的輪廓,相較於形成平面的阻劑圖案,可擴大每單位面積的表面積。雖溝部的阻劑106的凹狀態是依溝的形狀或阻劑的塗佈條件而有所不同,但較理想是其表面積廣。最好溝的開口部的徑(直徑)是金屬膜厚與阻劑膜厚的合算膜厚的2倍以上,長寬比是1~3。又,最好阻劑是共形的塗佈於溝內的金屬膜104。此情況,比起旋轉塗佈法,藉由噴霧式塗佈法來進行阻劑塗佈較能夠取得反映溝内的形狀之阻劑形狀。
圖1(d)是表示乾蝕刻金屬膜後的工程剖面圖。以阻劑105、106作為光罩來蝕刻金屬膜104,使金屬配線108及虛擬金屬配線109接近形成。金屬配線108、虛擬金屬配線109的側面是藉由側壁保護膜107所被覆。側壁保護膜107是在金屬膜104的蝕刻中阻劑105、106被分解而生成的有機成分附著形成者。在以往的構造中因為無溝100所以沒有來自具有凹陷輪廓的阻劑106之有機成分的供給,因此一旦金屬配線108疏散,則側壁保護膜107的厚度不夠充分,發生側面蝕刻。然而,本發明是在金屬配線疏散的情況時因為在其附近配置溝,所以可由此供給有機成分來被覆具有充分厚度的側壁保護膜107,因此不會發生側面蝕刻,可形成具有良好的剖面形狀之金屬配線108。另外,在上述實施例是以阻劑106覆蓋溝100的形狀來說明,其次則說明有關變形例。
圖2是表示本發明的第二實施例的工程剖面圖。經圖1(a)及圖1(b)後移至圖2(a)的工程。與圖1(c)相異的點是在形成於溝100上的阻劑110中設有小的穴。在阻劑圖案化時將比溝内金屬膜開口部面積更小的穴設於阻劑110的中央部,藉此形成具有更大表面積的阻劑110。該小的穴是在使阻劑105、106圖案化時同時曝光形成即可。較佳是調整曝光量來使阻劑能夠殘留於阻劑106的中心的開口底面。如此,在為了配線形成的阻劑圖案化時藉由對溝上的阻劑實施各種的圖案化,可更為擴大阻劑的表面積。雖未圖示,但若由上面來看形成於阻劑110的小穴時,可為圓形或方形,或由複數的圓形及複數的方形所構成的形狀。另外、若利用以上那樣的方法、則即使以旋轉塗佈法來進行阻劑塗佈、照樣可形成具有充分的表面積之阻劑。
圖2(b)是表示乾蝕刻金屬膜後的工程剖面圖。以阻劑105、110作為光罩來蝕刻金屬膜104,使金屬配線108及虛擬金屬配線109接近形成。金屬配線108、虛擬金屬配線109的側面是藉由側壁保護膜107來被覆。側壁保護膜107是在金屬膜104的蝕刻中阻劑105、110被分解而生成的有機成分附著形成者。在以往的構造中因為無溝100所以沒有來自阻劑110之有機成分的供給,因此一旦金屬配線108疏散,則側壁保護膜107的厚度不夠充分,發生側面蝕刻。然而,本發明是在金屬配線疏散的情況時因為在其附近配置溝,所以可由此供給有機成分來被覆具有充分厚度的側壁保護膜107,因此不會發生側面蝕刻,可形成具有良好的剖面形狀之金屬配線108。
如以上說明,若利用本發明的製造方法,則可確保充分厚的側壁保護膜,抑制蝕刻中的側面蝕刻,能夠形成無可靠度降低的疑慮之金屬配線。
100...溝
101、105、110...阻劑
102...半導體基板
103...層間絕緣膜
104...金屬膜
106...具有凹陷的輪廓之阻劑
107...側壁保護膜
108...金屬配線
109...虛擬金屬配線
圖1式表示本發明的第一實施例的工程剖面圖,
(a)溝蝕刻後的剖面圖
(b)堆積金屬膜後的剖面圖
(c)阻劑圖案化後的剖面圖
(d)金屬膜的乾蝕刻後的剖面圖。
圖2式表示本發明的第二實施例的工程剖面圖,
(a)阻劑圖案化後的剖面圖
(b)金屬膜的乾蝕刻後的剖面圖
100...溝
101、105...阻劑
102...半導體基板
103...層間絕緣膜
104...金屬膜
106...具有凹陷的輪廓之阻劑
107...側壁保護膜
108...金屬配線
109...虛擬金屬配線
Claims (5)
- 一種半導體裝置的製造方法,係於半導體基板上具有金屬配線的半導體裝置的製造方法,其特徵係包含:在上述半導體基板上形成層間絕緣膜之工程;形成供以在上述層間絕緣膜及上述半導體基板形成虛擬金屬配線之開口部的直徑為金屬膜厚與阻劑膜厚的合算膜厚的2倍以上,長寬比為1~3的溝之工程;在上述層間絕緣膜的表面及上述溝的內面堆積成為上述金屬配線或上述虛擬金屬配線的金屬膜之工程;在堆積上述金屬膜的上述溝上形成具有表面凹陷的輪廓之阻劑的圖案之工程;及蝕刻上述金屬膜來使上述層間絕緣膜上的金屬配線及上述溝內面及周圍的虛擬金屬配線接近形成之工程。
- 如申請專利範圍第1項之半導體裝置的製造方法,其中,在上述金屬膜上形成阻劑的圖案的工程中,上述溝上之具有表面凹陷的輪廓的阻劑的一部份的領域被曝光,而阻劑膜厚變薄。
- 如申請專利範圍第2項之半導體裝置的製造方法,其中,上述領域係平面視為圓形或方形。
- 如申請專利範圍第2或3項之半導體裝置的製造方法,其中,上述領域係於一個的溝上有複數個。
- 如申請專利範圍第1~3項中的任一項所記載之半導體裝置的製造方法,其中,上述金屬膜為鋁、或含有矽或銅的鋁合金。
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JP (1) | JP5265939B2 (zh) |
KR (1) | KR101513734B1 (zh) |
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- 2008-02-08 JP JP2008028703A patent/JP5265939B2/ja not_active Expired - Fee Related
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2009
- 2009-02-03 US US12/364,908 patent/US7981804B2/en not_active Expired - Fee Related
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- 2009-02-05 TW TW098103679A patent/TWI484550B/zh not_active IP Right Cessation
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TW200945437A (en) | 2009-11-01 |
KR20090086330A (ko) | 2009-08-12 |
US20090203210A1 (en) | 2009-08-13 |
CN101504931B (zh) | 2013-09-18 |
CN101504931A (zh) | 2009-08-12 |
US7981804B2 (en) | 2011-07-19 |
JP2009188300A (ja) | 2009-08-20 |
JP5265939B2 (ja) | 2013-08-14 |
KR101513734B1 (ko) | 2015-04-20 |
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