TW548526B - Method for controlling the topography of energy sensitive layer - Google Patents

Abstract

A method for controlling the topography of energy sensitive layer. First, a substrate covered by a dielectric layer, which has at least one isolated hole and a plurality of dense ones, is provided. Next, an energy sensitive layer is formed on the dielectric layer and fills in these holes. Thereafter, an energy treatment with various energy doses is performed on the energy sensitive layer and development is then performed to leave a patterned energy sensitive layer with a uniform surface in these holes. Finally, the dielectric layer is etched using the patterned energy sensitive layer as a sacrificial layer to form trenches over these holes and the remaining patterned energy sensitive layer is removed.

Description

548526 V. Description of the invention α) Field of the invention: The present invention relates to a semiconductor process, and in particular to a method for controlling the thickness distribution of an energy sensitive layer to form a generally flat energy sensitive pattern layer. To facilitate the subsequent etching process. Prior technology: In the traditional interconnection process, 'viah ο 1 e' structure and wire pattern are made separately, so it requires separate deposition and definition pattern procedures, making the whole process steps extremely complicated. Increasingly complicated circuit design trends will increase production time and costs. In order to overcome the above-mentioned difficulties, a damasa interconnect structure has been developed, which simultaneously produces a contact plug and an interconnect wire structure to achieve the effect of simplifying the process steps. The manufacturing method of the conventional dual mosaic structure will be described below with reference to Figs. 1a to 1d. First, please refer to FIG. 1 a, a semiconductor substrate is provided, on which a metal wire layer 1 1 is formed, such as copper or aluminum, and then a contact stop layer 12 is formed according to a conventional deposition technique to isolate the interconnects. 'Secondly, a dielectric layer 14 and an anti-reflection coating (ARC) 16 are formed, which prevents the standing wave effect and the optical proximity effect (OPE) from occurring when the trench is subsequently defined. Then, a patterned photoresist layer 18 is formed on the anti-reflection layer 16 by a conventional lithography process, which has a plurality of openings 13 and 15 to define an isolated pattern 'region and a dense pattern. Area of the mesothele hole.

Page 5 548526 V. Description of the invention (2) Next, please ask Mai Zhaodi 1b 'to use the patterned photoresist layer 18 as a mask, and etch the anti-reflection layer 16 under the openings 1 3 and 15 and The dielectric layer 14 is used to form dense vias 21 and detached vias 23. Subsequently, the patterned photoresist layer 18 is removed. Next, a photoresist layer 20 for defining a trench is coated on the anti-reflection layer 16 and the via holes 21 and 23. However, the photoresist layer 20 located above the separated vias 23 and the dense vias 21 forms recesses 17 and 19, which results in different surface heights. Therefore, for critical pattern dimensions (cr iti ca 1 dimens ion, CD) Control is quite difficult. Next, referring to FIG. 1c, a patterned photoresist layer 20 having a plurality of openings 25 and 27 is formed by a lithography process to define a trench. However, since there is no photoresist remaining after development, it is easy to damage the inner walls of the dense vias 21 and the detached vias 2 3 during subsequent etching to make trenches, and even money will pass through. (Punch-through) Terminate the layer 12 and damage the interconnect (not shown). Finally, referring to Figure 1d, the patterned photoresist layer 20 is used as a mask to engrav the anti-reflection layer 16 and the dielectric layer 14 under the opening 19a to form a plurality of trenches 2 9 and 3. 1. As described above, problems such as poor contours and money wear occur. The following is a description of the dreaming method of this conventional double-inlaid structure with figures 2a to 2e. Here, the same material or structure as in Fig. 1 is marked with the same & In addition, the steps in FIG. 2a are the same as those in FIG. 1a, and descriptions thereof are omitted here. Next, referring to FIG. 2b, using the patterned photoresist layer 18 as a mask, the anti-reflection layer 16 and the dielectric layer 14 under the openings 13 and 15 are etched to form a dense interlayer hole 2 1 And alienated mesogenetic holes 2 3. Subsequently, the patterned photoresist layer 18 is removed. Next, an organic anti-reflection layer is coated on the anti-reflection layer 16

IF

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548526 V. Description of the invention (3) (organic BARC) 22 and filled in the interstitial holes 21 and 23. Similarly, the depressions 24 and 26 formed by the organic bottom anti-reflection layer (organic B ARC) 22 located above the detached via 23 and the dense via 21 will cause the surface height to be different. Next, please refer to Figure 2c, due to the difference in depth between the recesses 2 4 and 26 ^ When the back chain is engraved with the organic bottom anti-reflection layer 22 to leave a part of the organic bottom anti-reflection in the via holes 21 and 23, respectively When the layers 22a and 2213 are used as a sacrificial protection layer in a subsequent etching process, the thickness of the sacrificial protection layer 22b will sacrifice the protection layer 22a. Next, referring to Fig. 2d, the anti-reflection layer 16 is coated with a photoresist layer 20 for defining a trench and filled with via holes 21 and 23. The existence of sacrifices and 22b can avoid the problem of poor contours and #wearing, and say 2a: the centering and the depth difference between 9 and 9 can be reduced to improve the size of key graphics. The patterned photoresist layer 20 (not shown) in the lithography process is used to define the trench J = photoresist layer 2. As a mask, the underside of the opening is etched; the electrical layer 14 forms a plurality of trenches 29 and 31. Unfortunately, the thickness of the sacrificial protective layer m is greater than the thickness of the sacrificial protective layer 22a and the inner metal conductor layer i is damaged by money penetration in the second and the second layer: J: the second layer: J = the thicker sacrificial protection layer m, And it ’s easy to be at heart: t ”# (fence) effect, shown as 22c in the figure. The electrical characteristics of the micro-response elements are caused when the #etch stop layer 12 is removed after the sixth houbin. 6 ^ G dye and shadow

0503-8968TWF (Nl); TSMC2002-0670, spin.ptd Page 7 548526 V. Description of the invention (4) In order to improve the uniformity of the thickness distribution of the sacrificial protective layer, it has been suggested to adopt a two-stage etch-back or double-layer resist method However, this method will increase manufacturing time and cost and cause other process problems. In addition, U.S. Patent No. 5,7 5 6, 2 56 proposes an improved double layer resist method, which forms a flat surface by petrifying a specific photoresist layer surface to form a flat surface, and then forms it on it. A conventional photoresist mask curtain layer is used for pattern transfer. However, this method can only improve the problem of CD offset and cannot avoid the phenomenon of over-etching, and its process is more complicated. Since the dual damascene process is one of the most important technologies in the current semiconductor industry, it is necessary to improve and solve its problems. SUMMARY OF THE INVENTION In view of this, an object of the present invention is to provide a method for controlling the thickness distribution of an energy-sensitive layer. The method is capable of forming an energy-sensitive pattern layer having a flat surface to facilitate subsequent etching processes and control of key pattern dimensions (CD). . Another object of the present invention is to provide a method for controlling the thickness distribution of an energy-sensitive layer, which is suitable for a dual-inlaying process: by forming highly uniform energy-sensitive pattern layers in vacant vias and dense vias, In order to prevent over-etching from damaging the underlying metal layer during the dual damascene process. In accordance with the above object, the present invention provides a method for controlling the thickness distribution of an energy sensitive layer. First, a substrate is provided having an uneven surface shape. Then, an energy-sensitive layer is coated on the surface of the substrate. After that, an energy treatment with different energy dose distribution is performed on the energy-sensitive layer, and then a development process is performed on the energy-sensitive layer to form a desired thickness distribution.

05〇3-8968TWF (Nl); TSMC2002-0670; spm_ptd page 8 548526 5. Description of the invention (5) In the energy-sensitive pattern layer 〃, the above-mentioned desired thickness distribution is uniformly thick, and it is uneven thickness depending on the shape of the substrate surface distributed. The X-knives are either non-reciprocal. The substrate is a semiconductor substrate and can be a resist layer or a spontaneously developed photoresist layer. The inner sensory layer is a light, and the energy treatment is an exposure process and the amount is ▲. Among them, the exposure process is performed by using a photomask to calibrate and expose a summer exposure agent (all§ner), a stepper, or = (PrOXimity). The exposure process is performed by a scanner. Distribution of exposure dose with different transmittances. Among them, it is controlled by a photomask to form different resolutions above the density of the pattern at the exposure site, and it is processed by a developing solution, baking treatment I, and light transmission. (Ab 1 ati on) to form the energy-sensitive pattern layer 3. Laser ablation according to the above-mentioned another purpose of the present invention, the thickness distribution method of the sun and the moon, is suitable for dual-type control of energy-sensitive bottom. Then, Formation of -media d on the substrate. First 'provide a base via and a plurality of dense vias. Then, there is at least one alienation sensitive layer in it and the alienation via and the denser are filled in the dielectric layer. An energy-sensing layer is formed on top of it-with different energy doses: layer :: after, yes, volume-sensitivity-a development program to deal with the holes in the alienation layer and = target summer. Next, the energy-sensitivity distribution of the Shi-Jun sentence thickness distribution Pattern; ': left in t-hole-with case layer as sacrifice After the dielectric layer is etched by the protective layer, a plurality of trenches are formed over the holes of the sensitive layer to connect the two layers to remove the energy-sensitive pattern layer from the separated hole and the dense.

0503-896871 \ rF (Nl); TSMC2002-0670; spm.ptcl 9th tribute 548526 5. Invention description (6) Wherein, the above substrate is a semiconductor substrate and the energy sensitive layer is a photoresist layer or a spontaneous development method. Photoresist layer. Furthermore, the energy dose above the dense vias is lower than the energy dose above the evacuated vias. Furthermore, the energy treatment is an exposure treatment and the energy dose is an exposure dose. Among them, the exposure process is performed by using a photomask to calibrate the exposure meter, stepper, or scanner. Furthermore, the exposure dose distribution of the exposure process is controlled by a mask having a different transmittance distribution. Among them, the light transmittance distribution is controlled by forming different secondary analysis pattern densities on the photomask. Furthermore, the energy-sensitive pattern layer is formed by a developing solution, a baking process, or a laser ablation. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, preferred embodiments are described below in conjunction with the accompanying drawings, and are described in detail as follows: Embodiment: The following description is given with reference to Figures 3a to 3g. The method for controlling the thickness distribution of the energy-sensitive layer according to the embodiment of the present invention is applicable to a dual damascene process. First, please refer to FIG. 3a, and provide a semiconductor substrate 100, such as a silicon wafer, on which any desired semiconductor element can be formed, such as a metal oxide semiconductor (MOS) transistor, a resistor, a logic element, and the like. In the description of the present invention, " substrate π-the word system includes the components formed on the semiconductor wafer and various coatings covering the wafer; π substrate surface π-the word system includes

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The uppermost layer exposed by the semiconductor wafer, such as the metal wire of Shixi wafer. However, in order to simplify the diagram here, only the insulating layer, 100, and the metal wire layer formed on the surface of the substrate. The table is a complete substrate. Then, by the conventional deposition technology, such as chemical conversion. (CVD) sequentially forming an etched phase / phase and a French interlayer dielectric layer (IMD) 106 and an anti-reflection layer Ur / 104 at the substrate 100 surface, and an etching stop layer 104 It is used to isolate the internal wiring, and its material is ^ 108 silicon, and the anti-reflection layer 10 is used to prevent subsequent lithography = can be nitrogen = political response and optical proximity effects, and its material can occur ^ ^ ^ Sand. Furthermore, the material of the interlayer dielectric layer 〇06 may include: Shi Xi Nitrogen ^ silicon, low dielectric constant spin-on glass, tetraethoxy silicon. Plasma emulsification, doped silicon oxide, fluorine Silicon oxide (F-S102), silicon oxynitride: glass j (FSG), phosphate rock glass (PSG), undoped stone rock slope (HDP-USG) deposited by high-density plasma , Oxidative emission deposited by high-density plasma " (Ι ^ Ρ-δι〇2), oxidized stone deposited by secondary pressure chemical vapor deposition (SACVD), and ozone-tetraethoxysilane (Os -TEOS) deposited ^ oxygen + chemical sentence 7. After that, an anti-reflection layer 108 is coated with an energy-sensitive layer, such as a photoresist layer, and a patterned energy-sensitive layer 1 1 0 is formed on the anti-reflection layer 108 by a conventional lithography process, and a plurality of layers are formed. Openings 10 9 and 1 1 1 are used to define the interstitial holes in the detached pattern area and the dense pattern area. Next, referring to Fig. 3b, using the energy-sensitive pattern layer 1 1 0 as a mask and anisotropic etching, such as the conventional reactive ion | insect etching (RIE), sequentially etch the openings 1 0 9 And the anti-reflection layer below 1 1 1 8 and gold

0503-8968TWF (Nl); TSMC2002-0670, spin.ptd Page 11 548526 V. Description of the invention (8) It is an interlayer dielectric layer (丨 dense interlayer holes 1 丨 3 and * 1 0 6 to form a detached dielectric layer Holes 1 1 5 and multiple conventional photoresist stripping methods terminate the money-cut termination layer 1 04. Then, the energy-sensitive pattern layer 110 is removed at night by the next step. Formation of the detachable via 115 and the layer 108—energy-sensitive The layer 112 is filled with the sensing layer U2 as described above, and this energy sensitive groove is used to avoid the introduction of ', = s for subsequent etching processes (manufacturing [: two-resistance materials, organic anti-reflection layers; inside crack The sensing layer 112 can be a photoresist material in the general order; the shadow ^ is an example of the yoke and further, the following is to learn the next, please refer to. Energy sensitive layer U2 implementation-with different energy I The key step of the present invention is 116 'Example implementation-energy treatment with different exposure agents :: volume distribution. Actual example: Example 10' The exposure equipment used can be a knife cloth. The exposure process is: In addition, the use of: reticle calibration exposure beam, (deep) ultraviolet light, laser, electrical The exposure source used may be ions in the exposure processing 116, in order to achieve, or light, etc. In addition, during the exposure 116, a purpose having a quantity distribution of ^ ^ = can be used, in addition to having a design on the mask 114者 之 光 114。 = 图 巧: Generally as optics = II ::: Γ According to the needs of the designer, change the sub-analysis diagram; up to the knife cloth, wrong to control the light distribution of the mask 114 in the non-M region 隹The exposure dose of 1 to 6 in the current and high-level exposure processing.

0503-8968TWF (Nl); TSMC2002-0670; spin ptd 548526 V. Description of the invention C9) Compared with the detached mesopore 1 1 5, the energy sensitive layer 1 1 3 required in the dense meso hole 1 1 3 The total amount is large, so the depression formed by the energy-sensitive layer 1 12 above the dense via 1 1 3 is deeper than the sparse via 1 1 5, as shown in FIG. 3 b. After the above phenomenon is developed, energy-sensitive pattern layers of different heights remain in the dense vias 1 1 3 and the evacuated vias 115 (the height of the energy-sensitive pattern layer remains in the evacuated vias 1 1 5 1 1 3), which may easily cause over-etching in subsequent etching processes and damage the metal wires 112. In this embodiment, in order to solve the above-mentioned problem, the exposure procedure 116 is implemented by using the mask 114. The density of the secondary analysis pattern located on the dense pattern on the mask 114 needs to be higher than that of the alienated pattern, so the transmittance at the alienated pattern can be improved. And reduce the light transmittance of the dense pattern, so that the exposure dose 1 1 6a located above the dense via 1 1 3 is lower than the exposure dose 11 6b located above the separated via 1 1 5. Moreover, in a given exposure dose range, it has a linear relationship with the development and removal thickness of the energy-sensitive layer. Therefore, the energy to be removed in the dense vias 1 1 3 and the evacuated vias 115 can be calculated. The thickness of the sensitive layer determines the required exposure dose in two places. Next, referring to FIG. 3d, a development process is performed on the energy-sensitive layer 1 12 to leave an energy-sensitive pattern with a desired thickness distribution in the separated vias 1 1 5 and the dense vias 11 3 Floor. Here, the energy-sensitive pattern layer located in the dense interstitial hole 1 1 3 is represented by 1 1 2 a, and the energy-sensitive pattern layer located in the sparse interstitial hole 115 is represented by 1 1 2b, both thicknesses Roughly the same (ie, forming an energy-sensitive pattern layer with a uniform thickness distribution). In this embodiment, the developer, baking treatment, or laser peeling can be used.

0503-8% 8TWF (Nl); TSMC2002-0670, spm.ptd page 13 548526 V. Description of the invention (10) The development process is performed by division. Next, please refer to FIG. 3e, and apply an energy-sensitive layer 1 1 8 on the anti-reflection layer 108, such as a photoresist layer, and fill the dense interlayer holes 1 1 3 and vacant; ι layer holes 1 1 5. It should be noted that the energy-sensitive layer 丨 8 needs to be different from the energy-sensitive pattern layer 12a and 12b as the sacrificial protective layer to avoid losing its protective effect in the subsequent micro-shirt awareness.Because the energy-sensitive layer 1 The energy-sensitive pattern layer 112a & 112b is formed below 丄 8, so the difference in the depressions formed above the dense vias 1 1 3 and the evacuated vias 丨 5 is small (that is, the energy-sensitive layer with a flat car body) 118 surface), and can improve the key pattern size bias (CD bias) generated in two places. Next, referring to FIG. 3f, a lithography process is performed to pattern the energy sensitive layer 1 1 8 and form a plurality of openings (not shown) for defining the trenches. Next, the patterned energy-sensitive layer 8 is used as a mask and the energy-sensitive patterned layers 112a and 112b are used as a sacrificial protective layer. Then, the openings are sequentially etched by anisotropic etching, such as the conventional reactive ion etching. The lower anti-reflection layer 108 and the interlayer dielectric layer 1 10β form trenches 21 and 119 above the evacuated vias 丨 15 and the dense vias 1 13 respectively, and the evacuated vias 1 1 5 and dense interlayer holes 1 1 3 have residual energy-sensitive pattern layers 2a and 112b. Here, since the thicknesses of the energy-sensitive pattern layers 112a and 11 2b have been controlled within a predetermined range and are substantially the same before making the trenches 121 and 119, the present invention is relatively easy to control the subsequent etching process. Avoid the phenomenon of fence effect and over-etching in the technology to damage the underlying metal layer. Finally, please refer to Figure 3g, using the conventional photoresist stripping method or appropriate solvent

548526 V. Description of the invention (11) ----- The patterned energy-sensitive layer 丨 8 and the remaining energy-sensitive patterns 1 1 2a and 1 1 2b are removed by liquid to complete the double mosaic structure of the present invention. Then ^ \ Zhizhi's last method to remove the trench 丨 2 1 and 1 1 9 exposed etching is finally $ Xi 104. Next, in accordance with the conventional metal deposition technology and chemical mechanical research / technology, a metal interconnect layer i 2 containing a metal barrier layer (not shown) such as titanium nitride or nitride nitride is formed in the dual damascene structure i 2 0, for example, find thin genus. ”To the above energy-sensitive processes or the ability to shape shapes on other half-surfaces, although the present invention is limited, the scope of the pattern layer is formed as a homogeneous conductor according to the description, which is sensitive to different amounts of the invention. As an example, the uniform thickness division or lithography (uneven pattern layer, has been better familiar with this can be changed. The scope of the patent can be changed. However, the thickness of the cloth (in the large process) can also be defined by the embodiment of the technology and finishing of the invention Unconstrained by the energy-sensitive layer of the double inlay body). The method of the present invention is used if it is required to distribute on an uneven substrate and is not dependent on the surface of the substrate. The disclosure is as above, but it is not intended to be used without departing from the present invention, so the protection scope of the present invention shall prevail. solid

〇5〇3-8968TWF (Nl); TSMC2002-0670; spin.ptd page 15 548526 diagrams briefly explain Figures 1 a to 1 d show the manufacturing method of the conventional dual-mosaic structure. Section + intention, 2 Figures a to 2e are schematic cross-sectional views showing another conventional method for manufacturing a dual-mosaic structure; Figures 3a to 3g are schematic cross-sectional views illustrating a method for manufacturing a dual-mosaic structure according to an embodiment of the present invention. Explanation of symbols: Conventional 1 0 ~ substrate; 1 1 ~ metal wire layer; 1 2 ~ etch stop layer; 1 3, 1 2 5 5 2 2 7 ~ opening; 1 4 ~ dielectric layer; 1 6 ~ anti-reflection Layer; 17, 19, 24, 26 ~ recess; 18, 20 ~ photoresist layer; 21 ~ dense via hole; 22 ~ bottom anti-reflection layer; 22a, 22b ~ sacrificial protective layer; 2 2 c ~ fence; 2 3 ~ isolated via hole; 2 9, 3 1 ~ trench. The present invention has a substrate of 10 to 10, a metal wire layer of 102 to 104, an etching stop layer to 104, an interlayer dielectric layer of 106 to 108, an anti-reflection layer, 10 to 11 and 11 to an opening. 110, 112, 118 ~ energy sensitive layer; 1 1 3 ~ dense interstitial hole; 1 1 4 ~ photomask;

0503-8968TWF (Nl); TSMC2002-0670, spin.ptd page 16 548526 Brief description of the drawings 1 1 5 ~ Dissociate mesopores; 1 1 6 ~ Exposure procedures; 1 1 6a, 1 16b ~ Exposure dose; 1 1 2a, 1 12b ~ sacrificial protection layer; 1 1 9, 1 2 1 ~ trench; 1 2 0 ~ metal interconnect layer.

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Claims (1)

48526 ^ History VI. Scope of patent application 1. A method for controlling the thickness distribution of an energy-sensitive layer, suitable for a dual damascene process, including the following steps: providing a substrate; forming a dielectric layer on the substrate, which has at least one detached dielectric Layer holes and multiple dense vias; forming an energy sensitive layer on the dielectric layer and filling the evacuated vias and the dense vias; implementing an energy with a different energy dose distribution to the energy sensitive layer Processing; and performing a development process on the energy-sensitive layer to leave an energy-sensitive pattern layer with a uniform thickness distribution in the vacant vias and the dense vias. 2. The method for controlling the thickness distribution of the energy-sensitive layer as described in item 1 of the scope of the patent application, further comprising the following steps: using the energy-sensitive pattern layer as a sacrificial protection layer to #etch the dielectric layer so as to etch the dielectric layer Forming a plurality of trenches above the holes and the dense vias; and removing the energy-sensitive pattern layer. 3. The method for controlling the thickness distribution of the energy-sensitive layer as described in item 1 of the scope of the patent application, wherein the substrate is a semiconductor substrate. 4. The method for controlling the thickness distribution of an energy-sensitive layer as described in item 1 of the scope of patent application, wherein the energy-sensitive layer is a photoresist layer or a spontaneously developed photoresist layer. 5. Control the thickness of the energy-sensitive layer as described in item 1 of the scope of patent application 0503-8968TWF (Nl) > TSMC2002-0670, spm.ptd page 18 548526 6. Method of patent application distribution, wherein the energy treatment is an exposure treatment and the energy dose is an exposure dose. 6. The method for controlling the thickness distribution of the energy-sensitive layer as described in item 5 of the scope of the patent application, wherein the exposure process is carried out by using a photomask to calibrate the exposure meter, stepper, or scanner. 7. The method for controlling the thickness distribution of the energy-sensitive layer as described in item 5 of the scope of the patent application, wherein the exposure dose distribution of the exposure process is controlled by a mask having a different transmittance distribution. 8. The method for controlling the thickness distribution of the energy-sensitive layer as described in item 7 of the scope of the patent application, wherein the transmittance distribution is controlled by forming different sub-resolution pattern densities on the photomask. 9. The method for controlling the thickness distribution of an energy-sensitive layer as described in item 1 of the scope of the patent application, wherein the energy dose above the dense vias is lower than the energy dose above the alienated vias. 10. The method for controlling the thickness distribution of an energy-sensitive layer as described in item 1 of the scope of the patent application, wherein the energy-sensitive pattern layer is formed by a developing solution. 1 1. The method for controlling the thickness distribution of an energy-sensitive layer as described in item 1 of the scope of the patent application, wherein the energy-sensitive pattern layer is formed by a baking process. 12. The method for controlling the thickness distribution of an energy-sensitive layer as described in item 1 of the scope of the patent application, wherein the energy-sensitive pattern layer is formed by laser ablation. 1 3. A method for controlling the thickness distribution of an energy-sensitive layer, including the following steps: providing a substrate having an uneven surface shape; coating an energy-sensitive layer on the surface of the substrate; 0503-8968TWF (Nl); TSMC2002-0670, spm.ptd page 19 548526 6. Apply for a patent to implement an energy treatment with different energy dose distributions on the energy-sensitive layer; and implement a development procedure on the energy-sensitive layer, To form an energy-sensitive pattern layer with a desired thickness distribution. 14. The method for controlling the thickness distribution of the energy-sensitive layer as described in item 13 of the scope of the patent application, wherein the substrate is a semiconductor substrate. 15. The method for controlling the thickness distribution of an energy-sensitive layer as described in item 13 of the scope of the patent application, wherein the energy-sensitive layer is a photoresist layer or a spontaneously developed photoresist layer. 16. The method for controlling the thickness distribution of an energy-sensitive layer as described in item 13 of the scope of the patent application, wherein the energy treatment is an exposure treatment and the energy dose is an exposure dose. 17. The method for controlling the thickness distribution of an energy-sensitive layer as described in item 16 of the scope of the patent application, wherein the exposure process is performed by a photomask calibrated exposure meter, stepper, or scanner. 1 8. The method for controlling the thickness distribution of an energy-sensitive layer as described in item 16 of the scope of the patent application, wherein the exposure dose distribution of the exposure process is controlled by a mask having a different transmittance distribution. 19. The method for controlling the thickness distribution of the energy-sensitive layer as described in item 18 of the scope of the patent application, wherein the transmittance distribution is controlled by forming different sub-analysis pattern densities on the photomask. 20. The method for controlling the thickness distribution of an energy-sensitive layer as described in item 13 of the scope of the patent application, wherein the energy-sensitive pattern layer is formed by a developing solution. 2 1. Control the thickness of the energy-sensitive layer as described in item 13 of the scope of patent application 0503-8968T \ VF (Nl); TSMC2002-0670, spm.ptd page 20 548526 6. Method of patent application range distribution, in which the energy-sensitive pattern is formed by baking. 〇 2 2 13. The method for controlling the thickness distribution of an energy-sensitive layer according to item 13, wherein the energy-sensitive pattern is formed by laser ablation. 02. The method for controlling the thickness-distribution of an energy-sensitive layer as described in item 13 of the scope of patent application, The desired thickness distribution is a uniform thickness distribution. 24. The method for controlling the thickness distribution of the energy-sensitive layer as described in item 13 of the scope of the patent application, wherein the desired thickness distribution is an uneven thickness distribution that does not depend on the shape of the substrate surface. 0503-8968TVi / F (Nl); TSMC2002-0670, spin.ptd page 21