JP2009188300A - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
- Publication number
- JP2009188300A JP2009188300A JP2008028703A JP2008028703A JP2009188300A JP 2009188300 A JP2009188300 A JP 2009188300A JP 2008028703 A JP2008028703 A JP 2008028703A JP 2008028703 A JP2008028703 A JP 2008028703A JP 2009188300 A JP2009188300 A JP 2009188300A
- Authority
- JP
- Japan
- Prior art keywords
- resist
- trench
- metal wiring
- semiconductor device
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 28
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 229910052751 metal Inorganic materials 0.000 claims abstract description 65
- 239000002184 metal Substances 0.000 claims abstract description 65
- 238000005530 etching Methods 0.000 claims abstract description 24
- 238000000034 method Methods 0.000 claims abstract description 21
- 239000011229 interlayer Substances 0.000 claims description 12
- 229910052782 aluminium Inorganic materials 0.000 claims description 10
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical group [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 3
- 229910000838 Al alloy Inorganic materials 0.000 claims description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 2
- 229910052802 copper Inorganic materials 0.000 claims description 2
- 239000010949 copper Substances 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 238000001312 dry etching Methods 0.000 abstract description 7
- 230000015572 biosynthetic process Effects 0.000 abstract description 6
- 230000001681 protective effect Effects 0.000 description 18
- 238000000354 decomposition reaction Methods 0.000 description 6
- 238000000059 patterning Methods 0.000 description 5
- 239000000460 chlorine Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
Abstract
【解決手段】金属配線を形成する領域の近傍にダミー金属配線を配置する領域を設ける。ダミー金属配線領域にはトレンチ100を形成し、次いで、金属配線のためのレジストパターン105を形成すると、トレンチ上のレジストは単位面積当り表面積を大きくすることができる。そして、ドライエッチングによる金属配線形成を行うと、このトレンチ上のレジストからの有機成分が強固な側壁保護膜107を作り、異方性エッチングが行われるため、良好な断面形状の金属配線108となる。
【選択図】図1−2
Description
101、105、110 レジスト
102 半導体基板
103 層間絶縁膜
104 金属膜
106 凹んだプロファイルを有するレジスト
107 側壁保護膜
108 金属配線
109 ダミー金属配線
Claims (7)
- 半導体基板上に金属配線を有する半導体装置の製造方法であって、
半導体基板上に層間絶縁膜を形成する工程と、
前記層間絶縁膜および前記半導体基板にダミー金属配線を形成するための開口部の径が金属膜厚とレジスト膜厚の合算膜厚の2倍以上であって、アスペクト比が1〜3であるトレンチを形成する工程と、
前記層間絶縁膜の表面と前記トレンチの内面に金属膜を堆積する工程と、
前記金属膜の上にレジストパターンを形成する工程と、
前記金属膜をエッチングして前記層間絶縁膜上の金属配線および前記トレンチ内面および周囲のダミー金属配線を近接して形成する工程と、を含むことを特徴とする半導体装置の製造方法。 - 前記金属膜の上にレジストパターンを形成する工程において、トレンチ上のレジストの一部が露光されて、レジスト膜厚が薄くなっていることを特徴とする請求項1記載の半導体装置の製造方法。
- 前記トレンチ上のレジストが露光された領域は、平面視にて円形であることを特徴とする請求項2記載の半導体装置の製造方法。
- 前記円形の露光領域は、一つのトレンチ上に複数個あることを特徴とする請求項3記載の半導体装置の製造方法。
- 前記トレンチ上のレジストが露光された領域は、平面視にて方形であることを特徴とする請求項2記載の半導体装置の製造方法。
- 前記円形の露光領域は、一つのトレンチ上に複数個あることを特徴とする請求項5記載の半導体装置の製造方法。
- 前記金属膜は、アルミニウム、またはシリコンや銅を含有するアルミニウム合金であることを特徴とする請求項1乃至請求項6のいずれか1項に記載の半導体装置の製造方法。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008028703A JP5265939B2 (ja) | 2008-02-08 | 2008-02-08 | 半導体装置の製造方法 |
US12/364,908 US7981804B2 (en) | 2008-02-08 | 2009-02-03 | Manufacturing method of semiconductor device |
TW098103679A TWI484550B (zh) | 2008-02-08 | 2009-02-05 | Semiconductor device manufacturing method |
KR1020090009291A KR101513734B1 (ko) | 2008-02-08 | 2009-02-05 | 반도체 장치의 제조 방법 |
CN200910007495XA CN101504931B (zh) | 2008-02-08 | 2009-02-09 | 半导体装置的制造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008028703A JP5265939B2 (ja) | 2008-02-08 | 2008-02-08 | 半導体装置の製造方法 |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2009188300A true JP2009188300A (ja) | 2009-08-20 |
JP2009188300A5 JP2009188300A5 (ja) | 2011-01-27 |
JP5265939B2 JP5265939B2 (ja) | 2013-08-14 |
Family
ID=40939246
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008028703A Expired - Fee Related JP5265939B2 (ja) | 2008-02-08 | 2008-02-08 | 半導体装置の製造方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US7981804B2 (ja) |
JP (1) | JP5265939B2 (ja) |
KR (1) | KR101513734B1 (ja) |
CN (1) | CN101504931B (ja) |
TW (1) | TWI484550B (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9296013B2 (en) * | 2013-02-28 | 2016-03-29 | Eastman Kodak Company | Making multi-layer micro-wire structure |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02189922A (ja) * | 1989-01-18 | 1990-07-25 | Nec Corp | 半導体装置の製造方法 |
JPH05267461A (ja) * | 1991-07-19 | 1993-10-15 | Lsi Logic Corp | 処理のための改良された回路配置の方法及び構造 |
JPH07106327A (ja) * | 1993-10-06 | 1995-04-21 | Toshiba Corp | 半導体装置及びその製造方法 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63250823A (ja) | 1987-04-07 | 1988-10-18 | Nec Kansai Ltd | 半導体装置の製造方法 |
JP3412173B2 (ja) * | 1991-10-21 | 2003-06-03 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
JPH0745590A (ja) | 1993-07-28 | 1995-02-14 | Seiko Epson Corp | 半導体装置の製造方法 |
JP2004158802A (ja) * | 2002-11-08 | 2004-06-03 | Renesas Technology Corp | 半導体記憶装置 |
KR100577562B1 (ko) * | 2004-02-05 | 2006-05-08 | 삼성전자주식회사 | 핀 트랜지스터 형성방법 및 그에 따른 구조 |
US7279407B2 (en) * | 2004-09-02 | 2007-10-09 | Micron Technology, Inc. | Selective nickel plating of aluminum, copper, and tungsten structures |
US7829965B2 (en) * | 2005-05-18 | 2010-11-09 | International Business Machines Corporation | Touching microlens structure for a pixel sensor and method of fabrication |
JP4783169B2 (ja) * | 2006-02-13 | 2011-09-28 | パナソニック株式会社 | ドライエッチング方法、微細構造形成方法、モールド及びその製造方法 |
US20090085120A1 (en) * | 2007-09-28 | 2009-04-02 | Texas Instruments Incorporated | Method for Reduction of Resist Poisoning in Via-First Trench-Last Dual Damascene Process |
-
2008
- 2008-02-08 JP JP2008028703A patent/JP5265939B2/ja not_active Expired - Fee Related
-
2009
- 2009-02-03 US US12/364,908 patent/US7981804B2/en not_active Expired - Fee Related
- 2009-02-05 TW TW098103679A patent/TWI484550B/zh not_active IP Right Cessation
- 2009-02-05 KR KR1020090009291A patent/KR101513734B1/ko active IP Right Grant
- 2009-02-09 CN CN200910007495XA patent/CN101504931B/zh not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02189922A (ja) * | 1989-01-18 | 1990-07-25 | Nec Corp | 半導体装置の製造方法 |
JPH05267461A (ja) * | 1991-07-19 | 1993-10-15 | Lsi Logic Corp | 処理のための改良された回路配置の方法及び構造 |
JPH07106327A (ja) * | 1993-10-06 | 1995-04-21 | Toshiba Corp | 半導体装置及びその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
KR101513734B1 (ko) | 2015-04-20 |
TWI484550B (zh) | 2015-05-11 |
TW200945437A (en) | 2009-11-01 |
CN101504931A (zh) | 2009-08-12 |
KR20090086330A (ko) | 2009-08-12 |
CN101504931B (zh) | 2013-09-18 |
US7981804B2 (en) | 2011-07-19 |
US20090203210A1 (en) | 2009-08-13 |
JP5265939B2 (ja) | 2013-08-14 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8319336B2 (en) | Reduction of etch microloading for through silicon vias | |
US10777480B2 (en) | Systems and methods to enhance passivation integrity | |
JP2009152243A (ja) | 半導体装置の製造方法 | |
US8124537B2 (en) | Method for etching integrated circuit structure | |
JP5265939B2 (ja) | 半導体装置の製造方法 | |
JP2006228792A (ja) | 半導体装置及びその製造方法 | |
US7262120B2 (en) | Method for fabricating metal line in semiconductor device | |
JP2011243639A (ja) | 半導体装置の製造方法 | |
JP2005079200A (ja) | 半導体装置およびその製造方法 | |
JP2005197707A (ja) | 半導体素子のダミー層及びその製造方法 | |
US9349635B2 (en) | Integrated circuits and methods of forming the same with multi-level electrical connection | |
KR101099515B1 (ko) | 반도체 소자의 콘택홀 형성 방법 | |
JP2008218553A (ja) | 半導体装置及びその製造方法 | |
JP2006049401A (ja) | 半導体装置およびその製造方法 | |
CN115410986A (zh) | 形成半导体结构的方法 | |
TWI532096B (zh) | 於基底中形成狹縫的製程 | |
KR20050067829A (ko) | 반도체소자의 인덕터 형성방법 | |
JP2005005733A (ja) | 半導体素子のコンタクト電極形成方法 | |
JP2009231372A (ja) | パターン形成方法 | |
KR20030097410A (ko) | 화학적기계연마 공정에서의 손상 방지방법 | |
KR20050062943A (ko) | 개구부의 경사진 측벽을 보상할 수 있는 반도체 소자의제조방법 | |
KR20040058956A (ko) | 반도체 소자의 제조 방법 | |
JP2005317771A (ja) | 半導体装置の製造方法 | |
JP2006253356A (ja) | 半導体装置及びその製造方法 | |
KR20060079285A (ko) | 반도체 소자의 제조방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
RD01 | Notification of change of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7421 Effective date: 20091108 |
|
RD01 | Notification of change of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7421 Effective date: 20091113 |
|
RD01 | Notification of change of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7421 Effective date: 20091117 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20101208 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20101208 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20130122 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20130123 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130321 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20130416 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20130502 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 Ref document number: 5265939 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313113 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
S533 | Written request for registration of change of name |
Free format text: JAPANESE INTERMEDIATE CODE: R313533 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |