WO2008102451A1 - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

Info

Publication number
WO2008102451A1
WO2008102451A1 PCT/JP2007/053309 JP2007053309W WO2008102451A1 WO 2008102451 A1 WO2008102451 A1 WO 2008102451A1 JP 2007053309 W JP2007053309 W JP 2007053309W WO 2008102451 A1 WO2008102451 A1 WO 2008102451A1
Authority
WO
WIPO (PCT)
Prior art keywords
silicon substrate
channel region
semiconductor device
embedded
apply
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2007/053309
Other languages
English (en)
French (fr)
Inventor
Naoyoshi Tamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Ltd
Fujitsu Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Fujitsu Semiconductor Ltd filed Critical Fujitsu Ltd
Priority to JP2009500046A priority Critical patent/JP5359863B2/ja
Priority to CN2007800510854A priority patent/CN101641792B/zh
Priority to PCT/JP2007/053309 priority patent/WO2008102451A1/ja
Priority to KR1020097013783A priority patent/KR101007242B1/ko
Publication of WO2008102451A1 publication Critical patent/WO2008102451A1/ja
Priority to US12/495,235 priority patent/US8502284B2/en
Anticipated expiration legal-status Critical
Priority to US13/610,529 priority patent/US8703596B2/en
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0167—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/792—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions comprising applied insulating layers, e.g. stress liners
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/797—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in source or drain regions, e.g. SiGe source or drain
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/01—Manufacture or treatment
    • H10D62/021—Forming source or drain recesses by etching e.g. recessing by etching and then refilling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/40—Crystalline structures
    • H10D62/405—Orientations of crystalline planes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/021—Manufacture or treatment using multiple gate spacer layers, e.g. bilayered sidewall spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

　チャネル領域を有するシリコン基板１０と、シリコン基板１０のチャネル領域上に、ゲート絶縁膜２６を介して形成されたゲート電極３２と、ゲート電極３２の両側のシリコン基板１０の表面側にそれぞれ埋め込まれ、シリコン基板１０に、シリコン基板１０の表面に平行な第１の方向の応力を印加する一対の埋め込み半導体領域５８と、チャネル領域と一対の埋め込み半導体領域５８との間のシリコン基板１０上に、シリコン基板１０に接してそれぞれ形成され、シリコン基板１０に、第１の方向とは反対方向の第２の方向の応力を印加するストレッサ膜４８とを有する。これにより、ＭＩＳトランジスタの動作速度に大きく影響するチャネル領域端部におけるキャリアの注入速度が大幅に増加し、ＭＩＳトランジスタの動作速度を向上することができる。
PCT/JP2007/053309 2007-02-22 2007-02-22 半導体装置及びその製造方法 Ceased WO2008102451A1 (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP2009500046A JP5359863B2 (ja) 2007-02-22 2007-02-22 半導体装置及びその製造方法
CN2007800510854A CN101641792B (zh) 2007-02-22 2007-02-22 半导体器件及其制造方法
PCT/JP2007/053309 WO2008102451A1 (ja) 2007-02-22 2007-02-22 半導体装置及びその製造方法
KR1020097013783A KR101007242B1 (ko) 2007-02-22 2007-02-22 반도체 장치 및 그 제조 방법
US12/495,235 US8502284B2 (en) 2007-02-22 2009-06-30 Semiconductor device and method of manufacturing semiconductor device
US13/610,529 US8703596B2 (en) 2007-02-22 2012-09-11 Semiconductor device and method of manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/053309 WO2008102451A1 (ja) 2007-02-22 2007-02-22 半導体装置及びその製造方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/495,235 Continuation US8502284B2 (en) 2007-02-22 2009-06-30 Semiconductor device and method of manufacturing semiconductor device

Publications (1)

Publication Number Publication Date
WO2008102451A1 true WO2008102451A1 (ja) 2008-08-28

Family

ID=39709737

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/053309 Ceased WO2008102451A1 (ja) 2007-02-22 2007-02-22 半導体装置及びその製造方法

Country Status (5)

Country Link
US (2) US8502284B2 (ja)
JP (1) JP5359863B2 (ja)
KR (1) KR101007242B1 (ja)
CN (1) CN101641792B (ja)
WO (1) WO2008102451A1 (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010085757A1 (en) * 2009-01-26 2010-07-29 Globalfoundries Inc. Methods for fabricating mos devices having epitaxially grown stress-inducing source and drain regions
WO2011083523A1 (ja) * 2010-01-07 2011-07-14 パナソニック株式会社 半導体装置及びその製造方法
WO2023135953A1 (ja) * 2022-01-11 2023-07-20 パナソニックＩｐマネジメント株式会社 撮像装置

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101130005B1 (ko) 2009-12-21 2012-03-26 주식회사 하이닉스반도체 반도체 소자 및 그의 형성 방법
KR101734207B1 (ko) * 2010-10-13 2017-05-11 삼성전자주식회사 반도체 소자 및 그 제조 방법
US8618554B2 (en) * 2010-11-08 2013-12-31 International Business Machines Corporation Method to reduce ground-plane poisoning of extremely-thin SOI (ETSOI) layer with thin buried oxide
JP6065366B2 (ja) * 2012-01-30 2017-01-25 富士通セミコンダクター株式会社 半導体装置の製造方法
CN103295965B (zh) * 2012-03-02 2015-11-25 中芯国际集成电路制造(上海)有限公司 半导体结构的制作方法
US9178058B2 (en) * 2013-03-13 2015-11-03 Taiwan Semiconductor Manufacturing Company, Ltd. RF switch on high resistive substrate
CN103178014B (zh) * 2013-03-14 2016-01-27 上海华力微电子有限公司 一种u型沟槽的制造方法
US9368543B2 (en) 2014-01-15 2016-06-14 Taiwan Semiconductor Manufacturing Co., Ltd. Image sensor device
US9941388B2 (en) * 2014-06-19 2018-04-10 Globalfoundries Inc. Method and structure for protecting gates during epitaxial growth
US9455195B2 (en) 2014-12-05 2016-09-27 International Business Machines Corporation Method of forming performance optimized gate structures by silicidizing lowered source and drain regions
US9716165B1 (en) 2016-06-21 2017-07-25 United Microelectronics Corporation Field-effect transistor and method of making the same
KR102039582B1 (ko) 2018-12-12 2019-11-01 주식회사 라파스 인장 공정으로 제조하기에 적합한 마이크로니들 재료의 적합성 시험 방법 및 이를 포함하는 마이크로니들 제조 방법
US10985254B2 (en) 2019-06-28 2021-04-20 Nanya Technology Corporation Semiconductor device and method of manufacturing the same

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004193166A (ja) * 2002-12-06 2004-07-08 Toshiba Corp 半導体装置
WO2005027192A2 (en) * 2003-09-10 2005-03-24 International Business Machines Corporation Structure and method of making strained channel cmos transistors having lattice-mismatched epitaxial extension and source and drain regions
JP2006253317A (ja) * 2005-03-09 2006-09-21 Fujitsu Ltd 半導体集積回路装置およびｐチャネルＭＯＳトランジスタ
JP2006253318A (ja) * 2005-03-09 2006-09-21 Fujitsu Ltd ｐチャネルＭＯＳトランジスタおよびその製造方法
JP2006261283A (ja) * 2005-03-16 2006-09-28 Sony Corp 半導体装置およびその製造方法

Family Cites Families (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5557122A (en) * 1995-05-12 1996-09-17 Alliance Semiconductors Corporation Semiconductor electrode having improved grain structure and oxide growth properties
US6403975B1 (en) * 1996-04-09 2002-06-11 Max-Planck Gesellschaft Zur Forderung Der Wissenschafteneev Semiconductor components, in particular photodetectors, light emitting diodes, optical modulators and waveguides with multilayer structures grown on silicon substrates
KR100332108B1 (ko) * 1999-06-29 2002-04-10 박종섭 반도체 소자의 트랜지스터 및 그 제조 방법
US6730551B2 (en) * 2001-08-06 2004-05-04 Massachusetts Institute Of Technology Formation of planar strained layers
US6621131B2 (en) 2001-11-01 2003-09-16 Intel Corporation Semiconductor transistor having a stressed channel
CN1311009C (zh) 2001-11-15 2007-04-18 三星电子株式会社 添加剂组合物、含有该添加剂组合物的淤浆组合物及使用该淤浆组合物抛光物体的方法
US7335545B2 (en) * 2002-06-07 2008-02-26 Amberwave Systems Corporation Control of strain in device layers by prevention of relaxation
US7307273B2 (en) * 2002-06-07 2007-12-11 Amberwave Systems Corporation Control of strain in device layers by selective relaxation
US6927414B2 (en) * 2003-06-17 2005-08-09 International Business Machines Corporation High speed lateral heterojunction MISFETs realized by 2-dimensional bandgap engineering and methods thereof
US7112495B2 (en) * 2003-08-15 2006-09-26 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method of a strained channel transistor and a second semiconductor component in an integrated circuit
US7037770B2 (en) * 2003-10-20 2006-05-02 International Business Machines Corporation Method of manufacturing strained dislocation-free channels for CMOS
US7053400B2 (en) * 2004-05-05 2006-05-30 Advanced Micro Devices, Inc. Semiconductor device based on Si-Ge with high stress liner for enhanced channel carrier mobility
TWI463526B (zh) * 2004-06-24 2014-12-01 萬國商業機器公司 改良具應力矽之ｃｍｏｓ元件的方法及以該方法製備而成的元件
JP4444027B2 (ja) * 2004-07-08 2010-03-31 富士通マイクロエレクトロニクス株式会社 ｎチャネルＭＯＳトランジスタおよびＣＭＯＳ集積回路装置
US7102205B2 (en) * 2004-09-01 2006-09-05 International Business Machines Corporation Bipolar transistor with extrinsic stress layer
US7335929B2 (en) * 2004-10-18 2008-02-26 Taiwan Semiconductor Manufacturing Company, Ltd. Transistor with a strained region and method of manufacture
JP4369359B2 (ja) * 2004-12-28 2009-11-18 富士通マイクロエレクトロニクス株式会社 半導体装置
JP4369379B2 (ja) * 2005-02-18 2009-11-18 富士通マイクロエレクトロニクス株式会社 半導体装置
JP4984665B2 (ja) * 2005-06-22 2012-07-25 富士通セミコンダクター株式会社 半導体装置およびその製造方法
US7579617B2 (en) * 2005-06-22 2009-08-25 Fujitsu Microelectronics Limited Semiconductor device and production method thereof
US7238555B2 (en) * 2005-06-30 2007-07-03 Freescale Semiconductor, Inc. Single transistor memory cell with reduced programming voltages
US20090045466A1 (en) * 2005-09-21 2009-02-19 Nec Corporation Semiconductor device
US20090179254A1 (en) * 2005-09-23 2009-07-16 Nxp B.V. Memory Device With Improved Performance And Method Of Manufacturing Such A Memory Device
JP2007157924A (ja) * 2005-12-02 2007-06-21 Fujitsu Ltd 半導体装置および半導体装置の製造方法
US7696019B2 (en) * 2006-03-09 2010-04-13 Infineon Technologies Ag Semiconductor devices and methods of manufacturing thereof
US7781277B2 (en) * 2006-05-12 2010-08-24 Freescale Semiconductor, Inc. Selective uniaxial stress relaxation by layout optimization in strained silicon on insulator integrated circuit
US7618866B2 (en) * 2006-06-09 2009-11-17 International Business Machines Corporation Structure and method to form multilayer embedded stressors
US7612364B2 (en) * 2006-08-30 2009-11-03 Taiwan Semiconductor Manufacturing Company, Ltd. MOS devices with source/drain regions having stressed regions and non-stressed regions
US7675118B2 (en) * 2006-08-31 2010-03-09 International Business Machines Corporation Semiconductor structure with enhanced performance using a simplified dual stress liner configuration
JP5092340B2 (ja) * 2006-10-12 2012-12-05 富士通セミコンダクター株式会社 半導体装置及びその製造方法
JP5040286B2 (ja) * 2006-12-13 2012-10-03 富士通セミコンダクター株式会社 半導体装置および半導体装置の製造方法
US7525161B2 (en) * 2007-01-31 2009-04-28 International Business Machines Corporation Strained MOS devices using source/drain epitaxy
US7736957B2 (en) * 2007-05-31 2010-06-15 Freescale Semiconductor, Inc. Method of making a semiconductor device with embedded stressor
US20090014807A1 (en) * 2007-07-13 2009-01-15 Chartered Semiconductor Manufacturing, Ltd. Dual stress liners for integrated circuits
JP5223285B2 (ja) * 2007-10-09 2013-06-26 富士通セミコンダクター株式会社 半導体装置の製造方法
US7687354B2 (en) * 2008-02-29 2010-03-30 Freescale Semiconductor, Inc. Fabrication of a semiconductor device with stressor
JP2010118621A (ja) * 2008-11-14 2010-05-27 Nec Electronics Corp 半導体装置及びその製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004193166A (ja) * 2002-12-06 2004-07-08 Toshiba Corp 半導体装置
WO2005027192A2 (en) * 2003-09-10 2005-03-24 International Business Machines Corporation Structure and method of making strained channel cmos transistors having lattice-mismatched epitaxial extension and source and drain regions
JP2006253317A (ja) * 2005-03-09 2006-09-21 Fujitsu Ltd 半導体集積回路装置およびｐチャネルＭＯＳトランジスタ
JP2006253318A (ja) * 2005-03-09 2006-09-21 Fujitsu Ltd ｐチャネルＭＯＳトランジスタおよびその製造方法
JP2006261283A (ja) * 2005-03-16 2006-09-28 Sony Corp 半導体装置およびその製造方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010085757A1 (en) * 2009-01-26 2010-07-29 Globalfoundries Inc. Methods for fabricating mos devices having epitaxially grown stress-inducing source and drain regions
CN102292811B (zh) * 2009-01-26 2016-01-20 格罗方德半导体公司 具有外延成长的应力引发源极与漏极区的金氧半导体装置的制造方法
WO2011083523A1 (ja) * 2010-01-07 2011-07-14 パナソニック株式会社 半導体装置及びその製造方法
WO2023135953A1 (ja) * 2022-01-11 2023-07-20 パナソニックＩｐマネジメント株式会社 撮像装置

Also Published As

Publication number Publication date
JP5359863B2 (ja) 2013-12-04
US20130005134A1 (en) 2013-01-03
US8703596B2 (en) 2014-04-22
US8502284B2 (en) 2013-08-06
US20090267119A1 (en) 2009-10-29
KR101007242B1 (ko) 2011-01-13
CN101641792B (zh) 2012-03-21
CN101641792A (zh) 2010-02-03
KR20090094018A (ko) 2009-09-02
JPWO2008102451A1 (ja) 2010-05-27

Similar Documents

Publication Publication Date Title
WO2008102451A1 (ja) 半導体装置及びその製造方法
WO2008126490A1 (ja) 半導体装置およびその製造方法
WO2009063588A1 (ja) 半導体装置及びその製造方法
SG139657A1 (en) Structure and method to implement dual stressor layers with improved silicide control
TW200501411A (en) Structure and method for forming the gate electrode in a multiple-gate transistor
WO2008099528A1 (ja) 表示装置、表示装置の製造方法
TWI373142B (en) Manufacturing method of thin film transistor using oxide semiconductor
WO2005124871A3 (en) Hybrid substrate technology for high-mobility planar and multiple-gate mosfets
TW200644224A (en) Semiconductor device and method for manufacturing the same
EP2302668A3 (en) Semiconductor device having tipless epitaxial source/drain regions
WO2008120335A1 (ja) 半導体装置およびその製造方法
WO2009129391A3 (en) Low temperature thin film transistor process, device property, and device stability improvement
WO2010051133A3 (en) Semiconductor devices having faceted silicide contacts, and related fabrication methods
WO2009011084A1 (ja) 薄膜トランジスタを備えた半導体装置およびその製造方法
TW200731530A (en) Semiconductor devices and methods for fabricating the same
WO2008105077A1 (ja) 化合物半導体装置とその製造方法
GB2484030A (en) Multiple orientation manowires with gate stack stressors
TW200742045A (en) Semiconductor device having a recess channel transistor
TW200631065A (en) Strained transistor with hybrid-strain inducing layer
TW200625640A (en) Field effect transistor
TW200625633A (en) High-mobility bulk silicon PFET
WO2009063606A1 (ja) 薄膜トランジスタ、薄膜トランジスタの作製方法、及び表示装置
WO2009058695A3 (en) Cool impact-ionization transistor and method for making same
TW200603233A (en) Method for manufacturing thin film transistor, electro-optical device and electronic apparatus
TW200707756A (en) Semiconductor device with thin-film transistors and method of fabricating the same

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 200780051085.4

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 07714806

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 2009500046

Country of ref document: JP

WWE Wipo information: entry into national phase

Ref document number: 1020097013783

Country of ref document: KR

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 07714806

Country of ref document: EP

Kind code of ref document: A1