WO2008087692A1 - 半導体メモリ、それを用いた半導体メモリシステム、および半導体メモリに用いられる量子ドットの製造方法 - Google Patents

半導体メモリ、それを用いた半導体メモリシステム、および半導体メモリに用いられる量子ドットの製造方法 Download PDF

Info

Publication number
WO2008087692A1
WO2008087692A1 PCT/JP2007/001361 JP2007001361W WO2008087692A1 WO 2008087692 A1 WO2008087692 A1 WO 2008087692A1 JP 2007001361 W JP2007001361 W JP 2007001361W WO 2008087692 A1 WO2008087692 A1 WO 2008087692A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor memory
quantum dots
memory
laminating
covered
Prior art date
Application number
PCT/JP2007/001361
Other languages
English (en)
French (fr)
Inventor
Katsunori Makihara
Seiichi Miyazaki
Seiichiro Higashi
Original Assignee
Hiroshima University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2007236635A external-priority patent/JP4594971B2/ja
Application filed by Hiroshima University filed Critical Hiroshima University
Priority to US12/523,682 priority Critical patent/US7898020B2/en
Publication of WO2008087692A1 publication Critical patent/WO2008087692A1/ja

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H01L29/42332—Gate electrodes for transistors with a floating gate with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Manufacturing & Machinery (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Non-Volatile Memory (AREA)

Abstract

　半導体メモリ（１１０）は、半導体基板（１０１）上に形成した絶縁膜（１０５）上に、極薄Ｓｉ酸化膜により被膜したＳｉ系量子ドット（３１１）を積層し、その上に高誘電率絶縁膜（３２２）で被膜したシリサイド量子ドット（３２１）を積層し、さらに高誘電率絶縁膜（４１２）で被膜したＳｉ系量子ドット（４１１）を積層した複合フローティング構造を有する。ゲート電極（１０４）に所定の正電圧を印加することで電子をシリサイド量子ドット（３２１）に蓄積し、ゲート電極（１０４）に所定の負電圧を印加および微弱な光を照射することにより当該電子を放出することで多値メモリ動作を高速かつ安定的に実行する。
PCT/JP2007/001361 2007-01-19 2007-12-06 半導体メモリ、それを用いた半導体メモリシステム、および半導体メモリに用いられる量子ドットの製造方法 WO2008087692A1 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US12/523,682 US7898020B2 (en) 2007-01-19 2007-12-06 Semiconductor memory, semiconductor memory system using the same, and method for producing quantum dots applied to semiconductor memory

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
JP2007-009772 2007-01-19
JP2007009772 2007-01-19
JP2007075803 2007-03-23
JP2007-075803 2007-03-23
JP2007236635A JP4594971B2 (ja) 2007-01-19 2007-09-12 半導体メモリ、それを用いた半導体メモリシステム、および半導体メモリに用いられる量子ドットの製造方法
JP2007-236635 2007-09-12

Publications (1)

Publication Number Publication Date
WO2008087692A1 true WO2008087692A1 (ja) 2008-07-24

Family

ID=39635701

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/001361 WO2008087692A1 (ja) 2007-01-19 2007-12-06 半導体メモリ、それを用いた半導体メモリシステム、および半導体メモリに用いられる量子ドットの製造方法

Country Status (1)

Country Link
WO (1) WO2008087692A1 (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010153612A (ja) * 2008-12-25 2010-07-08 Hiroshima Univ 金属ドットの製造方法およびそれを用いた半導体メモリの製造方法
CN114122117A (zh) * 2020-08-25 2022-03-01 爱思开海力士有限公司 半导体存储器装置及其制造和操作方法

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000040753A (ja) * 1998-07-24 2000-02-08 Sony Corp メモリ素子
JP2000091451A (ja) * 1998-09-16 2000-03-31 Toshiba Corp 半導体素子
JP2000150862A (ja) * 1998-08-31 2000-05-30 Toshiba Corp 半導体素子
JP2000164735A (ja) * 1998-11-27 2000-06-16 Toshiba Corp 半導体装置及びその製造方法
JP2003078050A (ja) * 2001-06-22 2003-03-14 Toshiba Corp 半導体装置及びその製造方法
JP2003258240A (ja) * 2002-02-28 2003-09-12 Toshiba Corp 乱数発生素子
JP2003347434A (ja) * 2002-05-22 2003-12-05 Sharp Corp メモリ膜構造、メモリ素子、半導体装置および電子機器
JP2004259986A (ja) * 2003-02-26 2004-09-16 Sharp Corp メモリ膜およびメモリ素子
JP2005079186A (ja) * 2003-08-28 2005-03-24 Sharp Corp 微粒子含有体およびその製造方法、メモリ機能体、メモリ素子並びに電子機器
JP2005268531A (ja) * 2004-03-18 2005-09-29 Nara Institute Of Science & Technology 超分子構造物質の改質方法
JP2005277263A (ja) * 2004-03-26 2005-10-06 Hiroshima Univ 量子ドット電界効果トランジスタ、それを用いたメモリ素子及び光センサ及びそれらの集積回路

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000040753A (ja) * 1998-07-24 2000-02-08 Sony Corp メモリ素子
JP2000150862A (ja) * 1998-08-31 2000-05-30 Toshiba Corp 半導体素子
JP2000091451A (ja) * 1998-09-16 2000-03-31 Toshiba Corp 半導体素子
JP2000164735A (ja) * 1998-11-27 2000-06-16 Toshiba Corp 半導体装置及びその製造方法
JP2003078050A (ja) * 2001-06-22 2003-03-14 Toshiba Corp 半導体装置及びその製造方法
JP2003258240A (ja) * 2002-02-28 2003-09-12 Toshiba Corp 乱数発生素子
JP2003347434A (ja) * 2002-05-22 2003-12-05 Sharp Corp メモリ膜構造、メモリ素子、半導体装置および電子機器
JP2004259986A (ja) * 2003-02-26 2004-09-16 Sharp Corp メモリ膜およびメモリ素子
JP2005079186A (ja) * 2003-08-28 2005-03-24 Sharp Corp 微粒子含有体およびその製造方法、メモリ機能体、メモリ素子並びに電子機器
JP2005268531A (ja) * 2004-03-18 2005-09-29 Nara Institute Of Science & Technology 超分子構造物質の改質方法
JP2005277263A (ja) * 2004-03-26 2005-10-06 Hiroshima Univ 量子ドット電界効果トランジスタ、それを用いたメモリ素子及び光センサ及びそれらの集積回路

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
MAKIHARA K. ET AL.: "Fabrication of Multiply-Stacked Structures of Si Quantum-Dots Embedded in SiO2 by Combination of Low-Pressure CVD and Remote Plasma Treatments", 2004 INTERNATIONAL MICROPROCESSES AND NANOTECHNOLOGY CONFERENCE 2004. DIGEST OF PAPERS, 27 October 2004 (2004-10-27), pages 216 - 217, XP002469059 *
OHBA R. ET AL.: "Nonvolatile Si Quantum Memory With Self-Aligned Double-Stacked Dots", IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 49, no. 8, August 2002 (2002-08-01), pages 1392 - 1398, XP001123235 *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010153612A (ja) * 2008-12-25 2010-07-08 Hiroshima Univ 金属ドットの製造方法およびそれを用いた半導体メモリの製造方法
CN114122117A (zh) * 2020-08-25 2022-03-01 爱思开海力士有限公司 半导体存储器装置及其制造和操作方法
US11723206B2 (en) 2020-08-25 2023-08-08 SK Hynix Inc. Semiconductor memory device and methods of manufacturing and operating the same
CN114122117B (zh) * 2020-08-25 2024-03-22 爱思开海力士有限公司 半导体存储器装置及其制造和操作方法
US11943930B2 (en) 2020-08-25 2024-03-26 SK Hynix Inc. Semiconductor memory device and methods of manufacturing and operating the same

Similar Documents

Publication Publication Date Title
Fukuda et al. A 4 V operation, flexible braille display using organic transistors, carbon nanotube actuators, and organic static random‐access memory
WO2008112062A3 (en) Quantum dot light emitting device
DE602008003796D1 (de) Tors mit einem oxidhalbleiter
WO2009099425A3 (en) Flexible devices including semiconductor nanocrystals, arrays, and methods
CN105453292B (zh) 光电子器件基板以及包括该光电子器件基板的光电子器件
CN104485351A (zh) 一种柔性有机发光显示器及其制作方法
TW200733309A (en) Semiconductor device having electrode and manufacturing method thereof
WO2009102617A3 (en) Device having power generating black mask and method of fabricating the same
WO2007130729A3 (en) Method of forming a semiconductor device and structure thereof
WO2008054994A3 (en) Deep ultraviolet light emitting device and method for fabricating same
WO2008142739A1 (ja) 半導体素子
ATE486370T1 (de) Herstellung eines hochwertigen rückseitigen kontakts mit lokaler rückseitiger siebdruckfläche
WO2009052354A3 (en) Droplet actuator structures
JP2010123936A5 (ja)
WO2008097365A3 (en) Photoconductive devices with enhanced efficiency from group iv nanoparticle materials and methods thereof
WO2008143721A3 (en) Photovoltaic cell with reduced hot-carrier cooling
EP1995787A3 (en) Semiconductor device having oxide semiconductor layer and manufacturing method therof
WO2009005894A3 (en) Non-polar ultraviolet light emitting device and method for fabricating same
WO2008114564A1 (ja) 薄膜トランジスタ及び薄膜トランジスタの製造方法
JP2010153828A5 (ja) 半導体装置
JP2008211191A5 (ja)
WO2009075281A1 (ja) 酸化物半導体を用いた電界効果型トランジスタ及びその製造方法
EP2080231A1 (en) Thin film solar cell and method for manufacturing thin film solar cell
WO2009044614A1 (ja) 有機半導体装置
WO2011025631A3 (en) Semiconductor crystal based radiation detector and method of producing the same

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 07859648

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 12523682

Country of ref document: US

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 07859648

Country of ref document: EP

Kind code of ref document: A1