WO2008081824A1 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
- Publication number
- WO2008081824A1 WO2008081824A1 PCT/JP2007/074979 JP2007074979W WO2008081824A1 WO 2008081824 A1 WO2008081824 A1 WO 2008081824A1 JP 2007074979 W JP2007074979 W JP 2007074979W WO 2008081824 A1 WO2008081824 A1 WO 2008081824A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- semiconductor device
- copper
- film formed
- manufacturing
- same
- Prior art date
Links
- 238000000034 method Methods 0.000 title abstract 2
- 239000004065 semiconductor Substances 0.000 title abstract 2
- 238000004519 manufacturing process Methods 0.000 title 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract 3
- 229910052802 copper Inorganic materials 0.000 abstract 3
- 239000010949 copper Substances 0.000 abstract 3
- 230000004888 barrier function Effects 0.000 abstract 2
- 238000009792 diffusion process Methods 0.000 abstract 2
- 239000000758 substrate Substances 0.000 abstract 2
- 239000004215 Carbon black (E152) Substances 0.000 abstract 1
- 229910000881 Cu alloy Inorganic materials 0.000 abstract 1
- 229910003481 amorphous carbon Inorganic materials 0.000 abstract 1
- 229930195733 hydrocarbon Natural products 0.000 abstract 1
- 150000002430 hydrocarbons Chemical class 0.000 abstract 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
- H01L21/02074—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a planarization of conductive layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02115—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material being carbon, e.g. alpha-C, diamond or hydrogen doped carbon
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
- H01L21/02304—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/3146—Carbon layers, e.g. diamond-like layers
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76867—Barrier, adhesion or liner layers characterized by methods of formation other than PVD, CVD or deposition from a liquids
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Plasma & Fusion (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/521,397 US8017519B2 (en) | 2006-12-28 | 2007-12-26 | Semiconductor device and manufacturing method thereof |
EP07860208A EP2112685A4 (en) | 2006-12-28 | 2007-12-26 | SEMICONDUCTOR COMPONENT AND METHOD FOR THE PRODUCTION THEREOF |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006355132 | 2006-12-28 | ||
JP2006-355132 | 2006-12-28 | ||
JP2007-130142 | 2007-05-16 | ||
JP2007130142A JP5154140B2 (ja) | 2006-12-28 | 2007-05-16 | 半導体装置およびその製造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2008081824A1 true WO2008081824A1 (ja) | 2008-07-10 |
Family
ID=39588506
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2007/074979 WO2008081824A1 (ja) | 2006-12-28 | 2007-12-26 | 半導体装置およびその製造方法 |
Country Status (6)
Country | Link |
---|---|
US (1) | US8017519B2 (ja) |
EP (1) | EP2112685A4 (ja) |
JP (1) | JP5154140B2 (ja) |
KR (1) | KR101076470B1 (ja) |
TW (1) | TW200834733A (ja) |
WO (1) | WO2008081824A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2012107162A1 (de) | 2011-02-10 | 2012-08-16 | Trw Automotive Gmbh | Gurtaufroller für einen fahrzeug-sicherheitsgurt |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5133852B2 (ja) * | 2008-11-13 | 2013-01-30 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法及び半導体装置 |
JP2011014872A (ja) * | 2009-06-04 | 2011-01-20 | Tokyo Electron Ltd | アモルファスカーボン膜の形成方法および形成装置 |
JP5351948B2 (ja) * | 2009-06-04 | 2013-11-27 | 東京エレクトロン株式会社 | アモルファスカーボン膜の形成方法および形成装置 |
US8461683B2 (en) * | 2011-04-01 | 2013-06-11 | Intel Corporation | Self-forming, self-aligned barriers for back-end interconnects and methods of making same |
US8524329B2 (en) | 2011-12-13 | 2013-09-03 | Lam Research Corporation | Electroless copper deposition |
US9142456B2 (en) * | 2013-07-30 | 2015-09-22 | Lam Research Corporation | Method for capping copper interconnect lines |
JP6469435B2 (ja) * | 2014-10-30 | 2019-02-13 | 太陽誘電ケミカルテクノロジー株式会社 | 構造体及び構造体製造方法 |
US20160276156A1 (en) * | 2015-03-16 | 2016-09-22 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device and manufacturing process thereof |
WO2018047988A1 (ko) * | 2016-09-06 | 2018-03-15 | 주식회사 더굿시스템 | 고출력 소자용 방열판재 |
US10276505B2 (en) | 2017-03-08 | 2019-04-30 | Samsung Electronics Co., Ltd. | Integrated circuit device and method of manufacturing the same |
KR102217242B1 (ko) | 2017-03-08 | 2021-02-18 | 삼성전자주식회사 | 집적회로 소자 및 그 제조 방법 |
JP2018159102A (ja) * | 2017-03-22 | 2018-10-11 | 株式会社東芝 | 金属パターンの形成方法 |
TWI723282B (zh) * | 2017-09-16 | 2021-04-01 | 美商應用材料股份有限公司 | 藉由矽化法之含金屬薄膜體積膨脹 |
WO2019212592A1 (en) * | 2018-05-03 | 2019-11-07 | Applied Materials, Inc. | Pulsed plasma (dc/rf) deposition of high quality c films for patterning |
JP2024512894A (ja) * | 2021-12-14 | 2024-03-21 | エルジー・ケム・リミテッド | 遠隔チャンバ及びそれを用いたdart-msシステム |
Citations (8)
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JPH09321045A (ja) * | 1996-05-30 | 1997-12-12 | Nec Corp | 半導体装置およびその製造方法 |
JP2001319928A (ja) * | 2000-05-08 | 2001-11-16 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
JP2004193544A (ja) * | 2002-05-08 | 2004-07-08 | Nec Electronics Corp | 半導体装置、および半導体装置の製造方法 |
JP2005050859A (ja) * | 2003-07-29 | 2005-02-24 | Renesas Technology Corp | 半導体装置の製造方法 |
WO2005087974A2 (en) * | 2004-03-05 | 2005-09-22 | Applied Materials, Inc. | Cvd processes for the deposition of amorphous carbon films |
JP2006253504A (ja) * | 2005-03-11 | 2006-09-21 | Nec Electronics Corp | 半導体装置およびその製造方法 |
JP2006294941A (ja) * | 2005-04-12 | 2006-10-26 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2006324584A (ja) * | 2005-05-20 | 2006-11-30 | Sharp Corp | 半導体装置およびその製造方法 |
Family Cites Families (16)
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JP2997371B2 (ja) * | 1992-10-27 | 2000-01-11 | 川崎製鉄株式会社 | 集積回路装置 |
US5559367A (en) * | 1994-07-12 | 1996-09-24 | International Business Machines Corporation | Diamond-like carbon for use in VLSI and ULSI interconnect systems |
JP3228183B2 (ja) * | 1996-12-02 | 2001-11-12 | 日本電気株式会社 | 絶縁膜ならびにその絶縁膜を有する半導体装置とその製造方法 |
US6492266B1 (en) * | 1998-07-09 | 2002-12-10 | Advanced Micro Devices, Inc. | Method of forming reliable capped copper interconnects |
US6331481B1 (en) * | 1999-01-04 | 2001-12-18 | International Business Machines Corporation | Damascene etchback for low ε dielectric |
US6342733B1 (en) * | 1999-07-27 | 2002-01-29 | International Business Machines Corporation | Reduced electromigration and stressed induced migration of Cu wires by surface coating |
JP2001062605A (ja) * | 1999-08-30 | 2001-03-13 | Sumitomo Electric Ind Ltd | 非晶質カーボン被覆工具 |
US6153935A (en) * | 1999-09-30 | 2000-11-28 | International Business Machines Corporation | Dual etch stop/diffusion barrier for damascene interconnects |
JP2001144090A (ja) * | 1999-11-11 | 2001-05-25 | Nec Corp | 半導体装置の製造方法 |
US6815329B2 (en) * | 2000-02-08 | 2004-11-09 | International Business Machines Corporation | Multilayer interconnect structure containing air gaps and method for making |
US6417092B1 (en) * | 2000-04-05 | 2002-07-09 | Novellus Systems, Inc. | Low dielectric constant etch stop films |
JP2002194547A (ja) * | 2000-06-08 | 2002-07-10 | Applied Materials Inc | アモルファスカーボン層の堆積方法 |
JP4535629B2 (ja) * | 2001-02-21 | 2010-09-01 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
US6905964B2 (en) * | 2003-01-09 | 2005-06-14 | Chartered Semiconductor Manufacturing Ltd. | Method of fabricating self-aligned metal barriers by atomic layer deposition on the copper layer |
US6977218B2 (en) * | 2003-07-17 | 2005-12-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for fabricating copper interconnects |
US7064078B2 (en) * | 2004-01-30 | 2006-06-20 | Applied Materials | Techniques for the use of amorphous carbon (APF) for various etch and litho integration scheme |
-
2007
- 2007-05-16 JP JP2007130142A patent/JP5154140B2/ja not_active Expired - Fee Related
- 2007-12-26 WO PCT/JP2007/074979 patent/WO2008081824A1/ja active Application Filing
- 2007-12-26 KR KR1020097014781A patent/KR101076470B1/ko not_active IP Right Cessation
- 2007-12-26 EP EP07860208A patent/EP2112685A4/en not_active Withdrawn
- 2007-12-26 US US12/521,397 patent/US8017519B2/en not_active Expired - Fee Related
- 2007-12-28 TW TW096150902A patent/TW200834733A/zh unknown
Patent Citations (8)
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Also Published As
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US8017519B2 (en) | 2011-09-13 |
JP5154140B2 (ja) | 2013-02-27 |
KR101076470B1 (ko) | 2011-10-25 |
JP2008182174A (ja) | 2008-08-07 |
EP2112685A1 (en) | 2009-10-28 |
EP2112685A4 (en) | 2012-01-04 |
TW200834733A (en) | 2008-08-16 |
US20100323516A1 (en) | 2010-12-23 |
KR20090088963A (ko) | 2009-08-20 |
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