WO2008065771A1 - Commutateur d'échantillonnage et convertisseur a/n de type pipeline - Google Patents

Commutateur d'échantillonnage et convertisseur a/n de type pipeline Download PDF

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Publication number
WO2008065771A1
WO2008065771A1 PCT/JP2007/062529 JP2007062529W WO2008065771A1 WO 2008065771 A1 WO2008065771 A1 WO 2008065771A1 JP 2007062529 W JP2007062529 W JP 2007062529W WO 2008065771 A1 WO2008065771 A1 WO 2008065771A1
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WO
WIPO (PCT)
Prior art keywords
capacitor
switch
sampling
voltage
sampling switch
Prior art date
Application number
PCT/JP2007/062529
Other languages
English (en)
Japanese (ja)
Inventor
Koji Oka
Daisuke Nomasaki
Toshiaki Ozeki
Junji Nakatsuka
Original Assignee
Panasonic Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corporation filed Critical Panasonic Corporation
Publication of WO2008065771A1 publication Critical patent/WO2008065771A1/fr

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
    • G11C27/02—Sample-and-hold arrangements
    • G11C27/024—Sample-and-hold arrangements using a capacitive memory element
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/06—Modifications for ensuring a fully conducting state
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/06—Modifications for ensuring a fully conducting state
    • H03K17/063—Modifications for ensuring a fully conducting state in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0036—Means reducing energy consumption
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/002—Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
    • H03M1/1245—Details of sampling arrangements or methods
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/44—Sequential comparisons in series-connected stages with change in value of analogue signal

Definitions

  • the present invention relates to an analog / digital converter, a sample / hold circuit, a bootstrap sampling switch and a pipeline AZD converter used for a sampling device.
  • FIG. 6 shows a sampling switch described in the non-patent document.
  • the conventional bootstrap switch has an electric control switch Ml.
  • the analog input signal Vin is input to the input terminal 11, and the control signal Vg is given to the electrical control switch control terminal 13 to control the electrical control switch Ml to be on or off, and the analog output signal Vout is Output to output terminal 12.
  • This bootstrap switch also includes a capacitor C1, a switch SW2 that connects the first terminal of the capacitor C1 to the low-potential power supply VSS, and a switch SW3 that connects the first terminal of the capacitor C1 and the input terminal 11.
  • the electric control switch Ml and the sampling capacitor C2 constitute a sampling circuit 15.
  • the electric control switch Ml is usually formed of an M0S transistor, and the input terminal is a source, the output terminal is a drain, and the control signal is a gate.
  • the electric control switch Ml is composed of an N-channel MOS transistor, and becomes conductive when the control terminal 13 is high (VDD potential or higher) and non-conductive when the control terminal 13 is low (VSS potential).
  • the switches SW1 to SW5 are also usually formed by MOS transistors, and their conduction and non-passage are controlled by a control signal.
  • Vin is an analog signal input to the input terminal 11
  • CLK1 is a clock signal that controls the switches SW1, SW2, and SW3
  • CLK2b is a clock signal that controls the switches SW3 and SW4
  • Vg is ,
  • the control signal of the electric control switch Ml, Vout represents the sampled analog signal output to the output terminal 12.
  • Clock signals CLK1, CLK2b Force When the switch is S high, the switch controlled by this signal is turned on, and when it is low, it is turned off.
  • FIG. 8 shows conduction and non-conduction states of the switches during the hold period of FIG. 7
  • FIG. 9 shows conduction and non-conduction states of the switches during the sample period of FIG.
  • FIG. 9 shows a state where the hold period has shifted to the next sample period.
  • the capacitor C1 is connected between the input terminal 11 and the electrical control switch control terminal 13, and the switches SW1, SW2, and SW5 are turned off.
  • both the clock signal CLK1 and the clock signal CLK2b are low, and all the switches are non-conductive. Since the Sampnore period starts after this period, the charge Q1 stored in the capacitor C1 is also retained during the Sampnore period. Due to the held charge Q1, the voltage of VDD-VSS is held at both ends of the capacitor C1, and the voltage between the input terminal 11 and the electrical control switch control terminal 13 is related to the voltage of the analog input signal Vin. A constant voltage (VDD— V SS) is applied.
  • a bootstrap switch is used in such a circuit configuration, and the voltage (Vg_Vin) between the electric control switch control terminal 13 and the input terminal 11 is a predetermined voltage (VDD-VSS). Because it is constant, the electric control switch Ml formed by the M ⁇ S transistor The voltage between the gate and gate is constant, the on-resistance is almost constant regardless of the input voltage, and a low-distortion sampling switch can be formed.
  • the electric control switch control terminal 13 is normally fixed to the high potential power supply VDD, and when the input voltage Vin changes, the voltage (Vg Since -Vin) is not constant, the on-resistance of the switch also changes with the input voltage, which causes distortion in the sampling output.
  • Patents ffl ⁇ l Bootstrapped low-voltage analog switches ⁇ Jesper Steensgaard, ireu its and Systems ⁇ 1999, ISCAS '99. Proceedings of the 1999 IEEE International Symp osium on Volume2,30 May-2 June 1999 Page (s ): 29_32 vol.2 ( Figure 3)
  • the voltage applied to the capacitor C1 is made lower than the voltage (VDD—VSS). In this case, however, the voltage is lower than the high potential power supply voltage VDD. It is necessary to make a circuit that generates a voltage higher than the low potential power supply voltage VSS. In addition, since these circuits need to be fully charged within the hold period, it is necessary to lower the output impedance, which leads to an increase in power consumption and an increase in the number of device elements.
  • the present invention has been made to solve the above-mentioned problems, and its object is to provide a control signal generation circuit for an electric control switch so as not to exceed the gate oxide film breakdown voltage.
  • a circuit that adds new power consumption is added while maintaining a substantially constant on-resistance regardless of the input signal level, which is a characteristic of the conventional bootstrap sampling switch.
  • Vg electrical control switch control signal
  • the present invention that achieves the above object is configured to generate an electric control switch control signal with high voltage accuracy only by adding a capacity and a switch that do not increase power consumption.
  • the sampling switch of the present invention is a boost strap type sampling switch having a substantially constant on-resistance regardless of the level of the input signal input to the input terminal, and the input signal
  • a sampling circuit having an electrical control switch for propagating the signal, and a sampling capacity for charging the charge of the input signal propagated from the electrical control switch, a first capacitor, and a second capacitor,
  • both ends of the first capacitor are charged with a stored charge corresponding to a voltage difference between a high potential power source and a low potential power source, and the second capacitor
  • the first capacitor and the second capacitor are connected in parallel during a sampling period in which zero charge is charged at both ends of the capacitor and the electrical control switch is turned on. , Connect the voltage at the terminals of one that the parallel connection to said input terminal, characterized in that the voltage of the other terminal and a switch group for the control signal of the electric control switch.
  • the present invention is characterized in that, in the sampling switch, both ends of the second capacitor are connected to a low potential power source during the hold period.
  • the present invention is characterized in that, in the sampling switch, both ends of the second capacitor are connected to a high potential power source during the hold period.
  • the present invention is characterized in that, in the sampling switch, both ends of the second capacitor are connected to the input terminal during the hold period.
  • the present invention of [0018] is characterized in that, in the sampling switch, a capacitance value of the first capacitor and the second capacitor is formed at a ratio of n: m (n and m are integers).
  • the present invention provides the first capacitor and the second capacitor. Are each formed using an integer number of unit capacities.
  • the electrical control switch includes a source electrode connected to the input terminal, a drain electrode connected to the sampling capacitor, and a gate electrode to which the control signal is applied. It is composed of transistors.
  • the pipeline A / D converter of the present invention is arranged continuously after the sampling switch and the sampling switch, and converts a plurality of output signals of the sampling switch into a multi-bit digital signal. And a digital correction circuit for correcting the digital output value of each of the stages.
  • control voltage of the electrical control switch of the sampling circuit can be set to the breakdown voltage of the gate oxide film only by appropriately setting the capacitance value and the capacitance ratio of the first capacitor and the second capacitor. It can be set not to exceed. Therefore, it is possible to obtain a boost strap type sampling switch that does not increase power consumption or increase the number of device elements.
  • the first capacitor C1 and the newly added second capacitor each have an integral number of unit capacitors, a control signal with high voltage accuracy can be generated. The variation in the characteristics of the sampling switch is effectively suppressed.
  • the gate oxide film can be formed without increasing the power consumption and by adding only the capacitance with a large increase in the number of device elements or by adding only this capacitance and the switch. Electric control switch control voltage can be generated without exceeding the breakdown voltage.
  • the sampling switch of the present invention since the first capacitor C1 and the second capacitor to be newly added are each configured with an integer number of unit capacitors, a control signal with high voltage accuracy is provided. This produces an effect of effectively suppressing variation in the characteristics of the sampling switch.
  • FIG. 1 is a circuit diagram according to Embodiment 1 of the present invention.
  • FIG. 2 is a diagram related to Embodiment 1 of the present invention
  • FIG. 2 is a diagram illustrating a switch state during a hold period.
  • FIG. 3 is a diagram showing a switch state during a sampling period of the sampling switch according to the first embodiment of the present invention.
  • FIG. 4 shows an embodiment of the present invention.
  • FIG. 5 is a circuit diagram according to Embodiment 3 of the present invention: [FIG. 6]
  • Fig. 8 is a diagram showing the state of the switch during the hold period of the conventional sampling switch.
  • Fig. 9 is a diagram showing the state of the switch during the Sampnore period of the conventional sampling switch.
  • FIG. 10 is related to Embodiment 5 of the present invention.
  • FIG. 10 is a block diagram of the used pipeline A / D converter.
  • FIG. 1 shows a sampling switch according to Embodiment 1 of the present invention.
  • a second capacitance C3 is additionally inserted.
  • the number and configuration of the switch group SW0 consisting of five switches SW1 to SW5 is There is no change.
  • the first terminal of the capacitor C3 is connected to the terminal to which the switch SW2 and the switch SW3 are connected, and the second terminal of the capacitor C3 is connected to the control terminal 13 of the electric control switch Ml. Connected.
  • the operation timing at which SW1 to SW5 of this embodiment are turned on and off is the same as that in FIG. 7 of the conventional example.
  • Fig. 3 shows the connection of each switch when the next sample period starts.
  • Capacitor C1 and capacitor C3 are connected in parallel by switch SW3 and switch SW4, and both terminals thereof are connected to input terminal 11 and control terminal (gate terminal of the MOS transistor) 13 of electric control switch Ml.
  • the voltage Vg applied to the control terminal 13 becomes Vin + (VDD ⁇ VSS) ⁇ C1 / (C1 + C3). This is because when moving from the hold period to the sample period, the charge Q1 stored in the capacitor C1 is held, and the charge is redistributed to the capacitors C1 and C3 connected in parallel.
  • VDD—VSS VDD—VSS
  • X Cl V3sa X (CI + C3)
  • V3sa This is because (VDD-VSS) XC 1 / (CI + C3).
  • C1 / (C1 + C3) ⁇
  • the voltage Vg applied to the control terminal 13 is Vin + ⁇ X (VDD ⁇ VSS) (0 ⁇ 1).
  • the switch Ml is formed of MOS transistors.
  • the force and voltage (Vg_Vin) between the control terminal 13 and the input terminal 11 is ⁇ X (VDD ⁇ VSS)
  • the bootstrap has a constant on-resistance regardless of the input signal. Keep the characteristics of the switch. ⁇ can be freely set by determining the capacitance C1 and the capacitance C3 so as not to exceed the gate oxide breakdown voltage.
  • the problem of reliability due to the gate oxide film breakdown voltage can be prevented only by adding the capacitor C3, and an effect of hardly increasing the power consumption can be obtained. It is done.
  • FIG. 4 shows a sampling switch according to Embodiment 2 of the present invention.
  • the capacity (second capacity) C4, the switch SW6, and the switch SW7 are arranged in comparison with the conventional example.
  • the switch SW6 is connected between the first terminal of the capacitor C4 and the high potential power supply VDD, and the switch SW7 is a terminal connecting the first terminal of the capacitor C4, the switch SW2 and the switch SW3.
  • the second terminal of the capacitor C4 is connected to the terminal connected to the switch SW1 and the switch SW4.
  • the switch SW6 operates at the timing of the clock signal CLK1 in Fig. 7, the switch SW7 operates at the timing of the clock signal CLK2b, and during the hold period, the switch SW6 is conductive and the switch SW7 is nonconductive, while the sample period Then, switch SW6 is non-conductive and switch SW7 is conductive.
  • both terminals of the capacitor C4 are connected to the high-potential power supply VDD, and there is no potential difference between the quantity terminals, so that the stored charge is zero as in the first embodiment.
  • the configuration in which the capacitor C1 and the capacitor C4 are connected in parallel and connected between the input terminal 11 and the electric control switch control terminal 13 is the same as in the first embodiment, and the voltage of Vg is Vin + (VDD ⁇ VSS) ⁇ C1 / (C1 + C4), and the same effect as in the first embodiment can be obtained. There are two more switches than in the first embodiment. It is not a problem.
  • FIG. 5 shows a sampling switch according to Embodiment 3 of the present invention.
  • a capacitor (second capacitor) C5, a switch SW8, and a switch SW9 are added to the conventional example.
  • the switch SW8 is connected between both terminals of the capacitor C5, and the first terminal of the capacitor C5 is connected to the input terminal 11.
  • the switch SW9 is connected to the second terminal of the capacitor C5 and a terminal connecting the switch SW1 and the switch SW4.
  • the switch SW8 operates at the timing of the clock signal CLK1 in FIG. 7, the switch SW9 operates at the timing of the clock signal CLK2b, and during the hold period, the switch SW8 is conductive and the switch SW9 is nonconductive. In the sample period, the switch SW8 is non-conductive and the switch SW9 is conductive.
  • the voltage Vg applied to pin 13 is Vin + (VDD -VSS) X nZ (n + m).
  • this capacitance ratio is 1% or less, the control voltage variation of the electric control switch Ml can be suppressed to 1% or less, and the on-resistance variation in manufacturing of the electric control switch Ml is almost 1%.
  • the following can be kept small.
  • a sampling switch characteristic variation due to on-resistance variation, In addition, variations in distortion characteristics can be reduced, and a sampling switch with good characteristics can be provided.
  • the electric control switch Ml is composed of an n-channel MOS transistor, but it goes without saying that the same effect can be obtained by using a p-channel MOS transistor.
  • a detailed description of the configuration of switches SW1 to SW9 is omitted. Usually, MOS switches are used.
  • FIG. 10 shows a fourth embodiment of the present invention. This embodiment shows the application of the sampling switch described above.
  • This figure shows a pipeline A / D converter.
  • the first stage is a sample-no-hold circuit 20 composed of the sampling switches described above, and a plurality of consecutively arranged downstream stages.
  • a plurality of stages 211 to 21n comprising the above arithmetic circuits.
  • the plurality of stages 211 to 21n convert the output signal of the sampling switch, that is, the charge amount of the sampling capacitor C2 shown in FIG. 1, into a predetermined multi-bit digital signal.
  • These digital signals are input to the digital correction circuit 22 and corrected, and the corrected output becomes a multi-bit digital output value from the pipeline A / D converter.
  • the sampling switch of the present invention has the bootstrap circuit that effectively reduces the control voltage of the MOS transistor that constitutes the switch. It is useful as a hold circuit, etc., and can also be applied to pipeline / analog / digital conversion circuit applications.

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Abstract

La présente invention concerne un commutateur d'échantillonnage d'amorçage qui a un condensateur C1 pour charger une tension VDD-VSS et un condensateur C3 pour charger des charges nulles pendant une période de maintien. Pendant une période d'échantillonnage, le condensateur C1 et le condensateur C3 sont raccordés en parallèle et ce circuit en parallèle est raccordé entre une borne d'entrée analogique Vin et la borne de commande d'un commutateur de commande électrique (M1) constitué d'un transistor MOS. Un rapport de capacité entre le condensateur C1 et le condensateur C3 est fixé à un rapport de capacité de telle sorte que la tension de commande du commutateur de commande électrique (M1) est réduite à une tension qui ne dépasse pas la tension de tenue d'un film d'oxyde de grille. En conséquence, on peut empêcher que la tension de tenue du film d'oxyde de grille dans le commutateur de commande électrique (M1) soit dépassée en ajoutant simplement le condensateur C3 sans provoquer une augmentation de la consommation de puissance ou du nombre d'éléments, et le commutateur de commande électrique (M1) peut être protégé de manière efficace.
PCT/JP2007/062529 2006-11-30 2007-06-21 Commutateur d'échantillonnage et convertisseur a/n de type pipeline WO2008065771A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2006-323816 2006-11-30
JP2006323816 2006-11-30

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010199841A (ja) * 2009-02-24 2010-09-09 Fujitsu Semiconductor Ltd アナログスイッチ回路
FR2979173A1 (fr) * 2011-08-19 2013-02-22 St Microelectronics Grenoble 2 Commutateur analogique basse tension
JP2014064434A (ja) * 2012-09-24 2014-04-10 Sharp Corp サンプルホールド回路およびスイッチング電源回路
JP2016032292A (ja) * 2014-07-25 2016-03-07 アイメック・ヴェーゼットウェーＩｍｅｃ Ｖｚｗ インターリーブ型アナログ・ディジタル変換器のためのサンプルホールド回路
JP2016143918A (ja) * 2015-01-29 2016-08-08 株式会社ソシオネクスト スイッチ回路、ａｄ変換回路および集積回路
CN107241088A (zh) * 2017-06-07 2017-10-10 中国电子科技集团公司第二十四研究所 一种消除衬偏效应的深亚微米cmos自举开关

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56104532A (en) * 1980-01-25 1981-08-20 Toshin Prod Kk Digital-analog converting circuit
JPH05235766A (ja) * 1991-10-07 1993-09-10 Nec Corp Ａ／ｄ変換器
JP2004228988A (ja) * 2003-01-23 2004-08-12 Renesas Technology Corp ブートストラップ回路

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56104532A (en) * 1980-01-25 1981-08-20 Toshin Prod Kk Digital-analog converting circuit
JPH05235766A (ja) * 1991-10-07 1993-09-10 Nec Corp Ａ／ｄ変換器
JP2004228988A (ja) * 2003-01-23 2004-08-12 Renesas Technology Corp ブートストラップ回路

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010199841A (ja) * 2009-02-24 2010-09-09 Fujitsu Semiconductor Ltd アナログスイッチ回路
FR2979173A1 (fr) * 2011-08-19 2013-02-22 St Microelectronics Grenoble 2 Commutateur analogique basse tension
US8648642B2 (en) 2011-08-19 2014-02-11 Stmicroelectronics (Grenoble 2) Sas Low voltage analog switch
JP2014064434A (ja) * 2012-09-24 2014-04-10 Sharp Corp サンプルホールド回路およびスイッチング電源回路
JP2016032292A (ja) * 2014-07-25 2016-03-07 アイメック・ヴェーゼットウェーＩｍｅｃ Ｖｚｗ インターリーブ型アナログ・ディジタル変換器のためのサンプルホールド回路
JP2016143918A (ja) * 2015-01-29 2016-08-08 株式会社ソシオネクスト スイッチ回路、ａｄ変換回路および集積回路
CN107241088A (zh) * 2017-06-07 2017-10-10 中国电子科技集团公司第二十四研究所 一种消除衬偏效应的深亚微米cmos自举开关

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