EP1540565B1 - Systeme de condensateur commute, procede correspondant et utilisation de ce dernier - Google Patents

Systeme de condensateur commute, procede correspondant et utilisation de ce dernier Download PDF

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Publication number
EP1540565B1
EP1540565B1 EP03791719A EP03791719A EP1540565B1 EP 1540565 B1 EP1540565 B1 EP 1540565B1 EP 03791719 A EP03791719 A EP 03791719A EP 03791719 A EP03791719 A EP 03791719A EP 1540565 B1 EP1540565 B1 EP 1540565B1
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Prior art keywords
amplifier
circuit
input
signal
voltage
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EP1540565A2 (fr
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Patrick J. Quinn
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Xilinx Inc
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Xilinx Inc
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Priority claimed from US10/231,541 external-priority patent/US6784824B1/en
Priority claimed from US10/232,113 external-priority patent/US6727749B1/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06G—ANALOGUE COMPUTERS
    • G06G7/00—Devices in which the computing operation is performed by varying electric or magnetic quantities
    • G06G7/12—Arrangements for performing computing operations, e.g. operational amplifiers
    • G06G7/14—Arrangements for performing computing operations, e.g. operational amplifiers for addition or subtraction 
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06J—HYBRID COMPUTING ARRANGEMENTS
    • G06J1/00—Hybrid computing arrangements

Definitions

  • the present invention generally relates to switched capacitor circuits, and more particularly to a switched capacitor summing circuit and its use in an analog-to-digital converter.
  • Switched capacitor circuits are a class of discrete-time systems that are often used in connection with filters, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and other analog/mixed signal applications.
  • ADCs analog-to-digital converters
  • DACs digital-to-analog converters
  • Conventional switched capacitor circuits are based on creating coefficients of a transfer function by transferring charge from one input capacitor C 1 to a second capacitor C 2 in the feedback loop of an amplifier via the virtual node of that amplifier so as to create a transfer of C 1 /C 2 .
  • capacitors such as double poly or Metal-Insulator-Metal (MiM) capacitors may be used, but the capacitor mismatch problem is not eliminated.
  • circuits that employ voltage-to-charge and charge-to-voltage translations via the virtual earth node have limited immunity to extraneous noise sources, as the virtual earth node is a well known pick-up point for unwanted noise.
  • US 6 362 770 describes an example of a switched capacitor gain stage having a first and second input and an output and includes an amplifier having an output connected to the output of the gain stage and further including a first, second and third capacitor pair.
  • a switch network is operable to switch selected ones of the first second and/or third capacitor pairs to receive varying voltage from the first or second inputs and/or switch a capacitor pair across the amplifier and a reference voltage.
  • the capacitors of the capacitor pairs are connectable via switches to an inverting input of the amplifier.
  • ADCs analog-to-digital converters
  • DEC digital error correction
  • the present invention addresses these and other shortcomings of the prior art, and provides a solution to the problems exhibited by prior art switch capacitor circuits and ADCs.
  • the present invention provides a method and apparatus for summing a plurality of input voltage signals and providing optional level shifting, where the resulting transfer function is independent of capacitor mismatch and non-linearity.
  • a circuit for adding a plurality of input signals.
  • the circuit includes an amplifier having first and second input terminals and an output terminal.
  • a first capacitance is coupled to receive a first input signal and to store a corresponding first voltage in response to a first clock phase
  • a second capacitance is coupled to receive a second input signal and to store a corresponding second voltage in response to the first clock phase.
  • a first switch circuit is coupled to the first capacitance to provide the first voltage to the first input terminal of the amplifier, and to couple the output terminal of the amplifier to the first capacitance via a feedback loop.
  • a second switch circuit is coupled to the second capacitance to provide the second voltage to the second input terminal of the amplifier in response to the second clock phase. In this manner, the amplifier outputs a voltage signal corresponding to a sum of the first and second input signals that is independent of a ratio of the first and second capacitances.
  • a method for adding input voltage signals.
  • First and second input voltage signals are respectively sampled onto first and second capacitors during a first clock phase.
  • the first sampled input voltage that is held on the first capacitor is coupled to the negative input terminal of an amplifier
  • the second sampled voltage held on the second capacitor is coupled to the positive terminal of the amplifier.
  • a feedback voltage is provided from the amplifier output to the negative amplifier input via the first capacitor during the second clock phase.
  • the first and second input voltage signals are added at the amplifier during the second clock phase to output the sum in response to the sampled input voltage signals and the output feedback, whereby the resulting transfer function is independent of capacitor mismatch and non-linearity.
  • the present invention provides a method, apparatus, and system for providing accurate level shifting, residue multiplication, and sample-and-hold functions for analog-to-digital conversions, without requiring charge transfer between capacitors in a switched capacitor arrangement, thereby eliminating capacitor mismatch as a source of ADC errors.
  • an ADC stage for use in analog-to-digital conversions.
  • the ADC stage includes an amplifier having first and second input terminals, and an output terminal to provide an analog ADC residue signal.
  • First and second capacitances sample an input voltage signal and a complemented input voltage signal respectively, in response to a first clock phase.
  • a first switch circuit is coupled to the first capacitance to provide the sampled input voltage signal to the first input terminal of the amplifier, and to couple the output terminal of the amplifier to the first capacitance via a feedback loop, in response to a second clock phase.
  • a second switch circuit is coupled to the second capacitance to provide an inverted version of the sampled complemented input voltage signal to the second input terminal of the amplifier in response to the second clock phase.
  • a level shifting circuit is coupled to receive the input voltage signal, and in response, to select one of a plurality of reference voltages.
  • the amplifier adds the input signal to the inverted version of the complemented input signal as shifted by the level shifting circuit, to create the analog ADC residue signal for use in a subsequent ADC stage.
  • Differential and/or double-sampling versions are also provided in accordance with an embodiment of the present invention. Further, an embodiment of the present invention may be used in a number of ADC configurations, including algorithmic and pipelined ADC configurations.
  • a method for converting an analog input signal to a digital signal using an amplifier.
  • the method includes sampling the analog input signal onto a first capacitor, and the complement of the analog input signal onto a second capacitor.
  • the sampled analog input signal is provided to a first input terminal of the amplifier by controllably connecting the first capacitor between the amplifier output and the first input terminal in a unity gain feedback configuration.
  • An inverted version of the sampled complemented analog input signal, level shifted by one of a plurality of selectable reference voltages, is provided at a second input terminal of the amplifier by controllably coupling the second capacitor between a selected reference voltage and the second input terminal of the amplifier.
  • the sampled analog input signal is added to the inverted version of the sampled complemented analog input signal, and the selected reference voltage is subtracted therefrom to provide a residue signal available for use in subsequent conversion stages.
  • An exemplary embodiment of the present invention is directed to an apparatus and methodology that provides highly accurate, scalable addition and subtraction functions with optional output voltage level shifting, without requiring special circuit or calibration options.
  • the exemplary embodiment of the present invention can serve as a replacement for existing switched capacitor circuits that inherently exhibit capacitance mismatch and non-linearity characteristics.
  • input signals are sampled onto corresponding capacitor circuits, and the resulting voltages stored thereon are subsequently coupled to a buffering amplifier to determine the sum/difference of the input signals. No transfer of charge occurs between the capacitor circuits, which provides a transfer function that is independent of capacitor mismatch concerns.
  • a voltage level shift can also be implemented, by providing a level shifting voltage as a reference voltage to one of the capacitor circuits during the summing operation.
  • FIG. 1A illustrates a conventional switched capacitor that exhibits inherent capacitor mismatch and non-linearity problems addressed by the exemplary embodiment of the present invention.
  • a conventional manner for creating analog sampled data signal processing functions is based on the charge transfer stage 100 shown in FIG. 1A .
  • the charge transfer stage 100 is a non-inverting charge transfer stage with a half clock period delay.
  • the circuit 100 includes three input signals, labeled Vin_1 102, Vin_2 104, and Vin_3 106.
  • Vin_2 104 is the voltage to which the positive terminal of the amplifier 108 is connected, and thus is the virtual earth voltage between the positive and negative terminals of the amplifier 108.
  • Vin_2 104 at the positive terminal of the amplifier 108 is the voltage to which the top plate of capacitor C 1 110 is connected to on the first clock phase, clk1 112. If this were not the case, the negative input of the amplifier 108 would have to be returned to voltage Vin_2 on a second clock phase, clk2 114, which would considerably reduce the settling speed_of the amplifier 108.
  • Vin_2 104 is generally a fixed reference voltage.
  • the voltage Vin_3 106 does not necessarily have to be equivalent to Vin_2 104, but it generally is in conventional designs.
  • the signal voltage Vin_1 102 is sampled on to C 1 110 with respect to Vin_2 104. This occurs due to switches 116, 118 closing on the clk1 112 clock phase, thereby placing the capacitor C 1 110 between the signal voltage Vin_1 102 and the reference voltage Vin_2 104.
  • switches 116, 118, and 120 open, and switches 122, 124, and 126 close. This coupled the top plates of capacitors C 1 110 and C 2 128, and the charge on C 1 110 from the sampling phase is transferred to C 2 128 via the virtual earth node of the amplifier 108 between the positive and negative input terminals.
  • the charge stored on C 1 is must then be transferred to C 2 , producing an output voltage equal to the signal voltage Vin_1 102 times the ratio of C 1 /C 2 .
  • V out nT C 1 / C 2 ⁇ V in_ 1 ⁇ n - 1 2 ⁇ T
  • Vin_3 106 the extra voltage Vin_3 106 does not have to be the same as Vin_2 104, such that the circuit 100 would have a transfer function given by Equation 2 below:
  • V out nT C 1 / C 2 ⁇ V in _ 1 ⁇ n - 1 2 ⁇ T - V in_ 3 nT
  • FIG. 1B illustrates an inverting charge transfer stage 150 with no delay.
  • the charge transfer stage 150 is analogous to the charge transfer stage 100 of FIG. 1A , but the clock phases are switched on the top plate of the capacitor 110.
  • the amplifier 108 in FIGs. 1A and 1B has the dual function of providing charge transport via its virtual earth node (i.e., active charge redistribution), and buffering so as to allow the following stage to read the output voltage without affecting the charge on the capacitors.
  • virtual earth node i.e., active charge redistribution
  • finite amplifier DC gain and bandwidth cause incomplete charge redistribution, resulting in incomplete charge transfer from C 1 to C 2 .
  • This, together with inaccuracies in the matching of the capacitors C 1 and C 2 results in the creation of an inaccurate transfer function.
  • Many applications, such as ADCs, accurate narrowband filters including FIR and IIR filters, etc. require very high accuracies in the transfer function, such as accuracies exceeding 0.1%. This kind of accuracy is virtually impossible using the standard circuits of FIGs.
  • CMOS Complementary Metal-Oxide Semiconductor
  • FIG. 2A illustrates a representative single-sampling circuit 200 implementing the principles of an embodiment of the present invention.
  • the transfer function of circuit 200 is independent of capacitor mismatch, and can be realized in a standard digital CMOS process requiring no special options such as double poly or Metal-Insulator-Metal (MiM) capacitors, expensive trimming or calibrations, etc. It is based on delta-charge redistribution where the only charge transfer (other than to an external load capacitor) is to the parasitic capacitors at the amplifier inputs. No charge transfer takes place via the virtual earth node of the amplifier, making the circuit inherently accurate and second order independent of both the mismatch and non-linearity of the signal capacitors.
  • the circuit is faster than prior art solutions due at least in part to the buffer-type configuration used. Further, it has better immunity to extraneous noise sources due to the fact that there is primarily voltage processing with no voltage-charge-voltage translations via the virtual earth node which is a well-known pick-up point for unwanted noise.
  • the representative single-sampling circuit 200 of FIG. 2A includes two opposite phased clock signals, namely clock phases clk1 202 and clk2 204.
  • the analog sampled data input signals are shown as input signals Vin_1 206 and Vin_2 208, and may be either direct current (DC) or time varying signals.
  • the signals Vin_4 210 and Vin_5 212 may be either DC or time-varying signals.
  • the signal Vin_3 214 may be used, for example, as a variable DC shift in order to level shift the output signal Vout 216.
  • the input signal Vin_1 is sampled onto capacitance C 1 218 with respect to the reference voltage Vin_5 212 on clock phase clk1 202 by closing switches 220 and 222.
  • switches 224 and 226 are also closed to sample the input signal Vin_2 208 onto capacitance C 2 228.
  • bottom plate sampling is used, where the input signals Vin_1 206 and Vin_2 208 are sampled on to the bottom plate of capacitances C 1 218 and C 2 228 respectively.
  • the top plates of capacitances C 1 218 and C 2 228 are coupled to reference voltages Vin_5 212 and Vin_4 210 respectively during the clk1 202 phase.
  • capacitance C 2 228 may be coupled at its bottom plate to Vin_3 214 by closing switch 238 on the clk2 204 clock phase. Further, the top plate of capacitance C 2 228 may be coupled to the positive input terminal 240 of the amplifier 230 on clk2 204 by closing switch 242. In this manner, the voltage Vin_3 214 is coupled to the positive terminal 240 of the amplifier 230 through the capacitor C 2 228, in order to provide voltage level shifting at the output Vout 216.
  • the analog sampled data input signals Vin_1 and Vin_2 are sampled with respect to AC ground set at a reference voltage Vref.
  • V out nT V in_ 1 ⁇ n - 1 2 ⁇ T - V in_ 2 ⁇ n - 1 2 ⁇ T + V in_ 3 nT
  • Equations 4A, 4B, and 6 are independent of the capacitances C 1 and C 2 , illustrating that the circuits 200, 250 can provide a summing function independent of capacitor mismatch that is inherently exhibited in prior art solutions. No charge transfer takes place via the virtual earth node of the amplifier, making the design inherently accurate and second order independent of both the mismatch and non-linearity of the signal capacitors. Further, because the circuit configuration primarily utilizes voltage processing with no voltage-to-charge and charge-to-voltage translations via a virtual earth node, the circuit configuration exhibits much better noise immunity than prior art solutions. This makes the circuit configuration suitable for use in standard digital CMOS processes that are uncharacterized for analog performance and have no special analog options.
  • the representative double-sampling circuit 300 of FIG. 3 again includes two opposite phased clock signals, clkl and clk2.
  • the analog sampled data input signals are shown as input signals Vin_1 302 and Vin_2 304, and the signal Vin_3 306 may again be used as a variable DC shift in order to level shift the output signal Vout 308.
  • the data input signals Vin_1 302 and Vin_2 304 are sampled with respect to an AC ground.
  • the input signals Vin_1 302 and Vin_2 304 are sampled onto capacitances C 2 310 and C 4 312 respectively on clock phase clk1 by closing the appropriate switches 314, 316, 318, and 320.
  • the top plates of capacitances C 2 310 and C 4 312 are coupled to ground during the clk1 phase.
  • clk2, C 2 310 is coupled across the amplifier 322 due to switches 324, 326 closing, and switches 314, 316 opening.
  • the top plate of capacitance C 2 310 is coupled to the negative input 328 of the amplifier 322, and the bottom plate of capacitance C 2 310 is coupled to the output Vout 308 of the amplifier 322.
  • capacitance C 4 312 may be coupled at its bottom plate to Vin_3 306 by closing switch 330 on the clk2 clock phase. Further, the top plate of capacitance C 4 312 may be coupled to the positive input terminal 332 of the amplifier 322 on clk2 by closing switch 334. In this manner, the voltage Vin_3 306 is coupled to the positive terminal 332 of the amplifier 322 through the capacitor C 4 312, in order to provide voltage level shifting at the output Vout 308. As can be seen, the operation is analogous to that described in connection with FIGs. 2B .
  • FIG. 3 allows for the sampling of the inputs Vin_1 302 and Vin_2 304 on a first clock phase (e.g., clk1) and delivery of the output on a subsequent clock phase (e.g., clk2) as described above.
  • inputs Vin_1 302 and Vin_2 304 can also be sampled and delivered on alternate clock phases through the use of an additional set of capacitors, whereby the input signals are sampled on the second clock phase (e.g., clk2) and the output delivered on the first clock phase (e.g., clk1).
  • C 1 336 and C 3 338 perform similar functions to those described in connection with C 2 310 and C 4 312, but perform these functions on opposite phased clock signals.
  • input signal Vin_1 302 is sampled onto capacitance C 1 336 with respect to ground when switches 338 and 340 close, which will occur on the opposite clock phase as when C 2 310 is sampled.
  • Vin_2 302 is also sampled onto capacitance C 3 338 due to switches 342 and 344 being closed.
  • Vin_2 302 is sampled onto capacitors C 1 336 and C 3 338 on the clock phase opposite to that in which Vin_2 302 is sampled onto C 2 310 and C 4 312.
  • C 1 336 is connected across the amplifier 322 due to switches 346 and 348 closing.
  • the top plate of capacitance C 1 336 is coupled to the negative input 328 of the amplifier 322, and the bottom plate of capacitance C 1 336 is coupled to the output Vout 308 of the amplifier 322.
  • the bottom plate of capacitance C 3 338 is coupled at its bottom plate to Vin_3 306 by closing switch 350.
  • the top plate of capacitance C 3 338 may be coupled to the positive input terminal 332 of the amplifier 322 on this clock phase by closing switch 352. In this manner, the voltage Vin_3 306 is coupled to the positive terminal 332 of the amplifier 322 through the capacitor C 3 338, in order to provide voltage level shifting at the output Vout 308.
  • the inputs Vin_1 302 and Vin_2 304 can be processed at double the rate of a single-sampling implementation, thereby doubling the processing speed of the circuit (assuming the same amplifier hardware is being used).
  • the double-sampling circuit that can operate independent of capacitor matching has a number of advantages compared to the single-sampling version.
  • the double-sampling circuit can operate at double the speed of the single-sampling circuit for the same frequency of non-overlapping clocks (e.g., clk1 and clk2), since the input can be processed on both clk1 and clk2 phases. Even with this increased speed of operation, the double-sampling circuit consumes the same analog power as the single-sampling circuit. Further, the double-sampling circuit offers a full period delay, which is a requirement for any sampled data system operating at a sampling rate of 1/T.
  • T full period
  • the representative circuits described in connection with FIGs. 2A, 2B , and 3 present balanced impedances from the capacitors and accompanying switches at the two sensitive input terminals of the single-ended amplifier. This ensures accurate settling between clock edges.
  • the transfer functions associated with these circuits do not contain any capacitor ratios so that the processing of the signals occurs independent of the mismatch of the two signal capacitors with nominal value C. Only errors of a second order nature occur due to the presence of parasitic capacitances at the input nodes of the amplifier. Any imbalances either between the capacitors of nominal value C, or the input parasitic capacitors, will give rise to an error that is second order with respect to the absolute imbalance itself.
  • various combinations of clock phase control may be utilized.
  • two clock phases were described (e.g., clk1 and clk2).
  • any number of desired clock phases may be used.
  • This provides additional variability and flexibility in the choice of delays.
  • This may be beneficial for circuit applications benefiting from extended and/or variable clock delays.
  • delays may be required in the case of filter design, such as with Finite and Infinite Impulse Response (FIR/IIR) filters.
  • FIR/IIR Finite and Infinite Impulse Response
  • such filters may be of an nth order where a plurality of previous inputs (in the case of non-recursive filters) and/or a plurality of previous outputs (in the case of recursive filters) are utilized to perform the desired filtering function.
  • Flexibility in delay lines in the switched capacitor summer/level shifter in accordance with an embodiment of the present invention is highly advantageous. Therefore, where the transfer function requires the addition of signals separated by one or more delays, the addition of additional clock phases in accordance with an embodiment of the present invention provides this ability.
  • FIG. 4 illustrates an example of an N-path sum-delay-shift circuit 400 in accordance with one embodiment of the present invention.
  • additional clock phases may be used for circuits requiring delays.
  • the circuit of FIG. 4 operates similarly to the circuit described in connection with FIG. 3 , however additional switched capacitor circuits are provided, as well as N clock phases.
  • N switched capacitor circuits 402, 404, 406 are coupled to the negative input 408 of the amplifier 410
  • N switched capacitor circuits 412, 414, 416 are coupled to the positive input 418 of the amplifier 410.
  • the analog sampled data input signals are shown as input signals Vin_1 420 and Vin_2 422, and the signal Vin_3 424 may again be used as a variable DC shift in order to level shift the output signal Vout 426.
  • the data input signals Vin_1 420 and Vin_2 422 are sampled with respect to an AC ground.
  • the input signals Vin_1 420 and Vin_2 422 are sampled onto capacitances C within their respective N switched capacitor circuit 402, 404, 406, 412, 414, 416.
  • sampling for first switched capacitor circuits 402, 412 occurs on clk1
  • sampling for N-1 switched capacitor circuits 404, 414 occurs on clkN-1
  • sampling for N switched capacitor circuits 406, 416 occurs on clkN, and so forth.
  • each of the switched capacitor circuits can then be coupled across the amplifier 426 to perform the summing/level shifting function previously described.
  • input signals may be added at any desired delay, thereby facilitating realization of a wide variety of different circuit implementations, such as, for example, FIR and IIR filter circuits.
  • FIG. 5 is a flow diagram illustrating a method for adding at least two input voltage signals in accordance with the principles of an embodiment of the present invention.
  • a first input voltage signal is sampled 500 onto a first capacitor during a first clock phase.
  • a second input voltage signal is sampled 502 onto a second capacitor during the first clock phase.
  • the first capacitor is switched 504 in order to connect to the negative input terminal of the amplifier, and the second capacitor is switched 506 to connect to the positive input terminal of the amplifier.
  • the output voltage is fed back from the amplifier output to the negative input of the amplifier by way of the first capacitor, as shown at block 508.
  • the sum of the first and second input voltage signals is output 510 from the amplifier in response to the feedback voltage, and in response to the first and second sampled input voltages, during the second clock phase.
  • the signal processing capability of the method and architecture in accordance with an embodiment of the present invention enables its use in a wide variety of applications where accurate addition and subtraction of analog sampled data signals can be performed independent of capacitor mismatch.
  • the transfer function is also independent of non-linearity of the capacitors, since there is only voltage sampling and no charge transfer takes place from signal capacitor to signal capacitor.
  • the only significant charge transfer (other than that to the load capacitance) is to the parasitic capacitors at the amplifier inputs, which is only a small fraction of the total charge held on the signal capacitors with nominal values C. This, however, does not affect the accuracy of the transfer function. This is referred to herein as delta-charge redistribution, since the only main charge transfer is that to charge parasitic capacitance.
  • FIR and IIR filters Finite and Infinite Impulse response Filters
  • N-path filters delay lines, comb filters, integrators, differentiators, voltage multipliers to any level, accurate inverters, level shifters, voltage multipliers, single-to-differential and differential-to-single ended converters, etc.
  • any known circuit components may be used to provide the operations in accordance with an exemplary embodiment of the present invention.
  • a capacitor may be used where capacitors are indicated, however groups of series and/or parallel capacitors may also be used.
  • other components exhibiting capacitive properties and capable of storing a charge thereon may be used.
  • the switches employed may be any component capable of performing a switching function.
  • the principles of an exemplary embodiment of the present invention may be implemented using field-effect transistors (FETs) and variations such as metal-oxide-semiconductor field-effect transistor (MOSFETs), JFETs, VMOS, CMOS, etc.
  • FETs field-effect transistors
  • MOSFETs metal-oxide-semiconductor field-effect transistor
  • JFETs JFETs
  • VMOS VMOS
  • CMOS complementary metal-oxide-semiconductor field-effect transistor
  • Other transistor technologies may also be employed, such as bipolar technologies.
  • the switches may also be implemented using electrically-controlled mechanical switches and/or relays. Speed, efficiency, power consumption, and other factors will determine the type of switches to be employed, and in one particularly beneficial embodiment CMOS switches are implemented to provide the desired speed and power consumption characteristics.
  • the amplifier components may be any of a wide variety of operational amplifiers facilitating single-ended operation.
  • ADC analog-to-digital converter
  • ADC analog-to-digital converter
  • the ADC circuit in accordance with the another exemplary embodiment of the present invention provides a very accurate manner of subtracting/level shifting, residue multiplication, and sample-and-hold (S&H) functions, all within a single clock cycle.
  • S&H sample-and-hold
  • these functions are performed using a switched capacitor technique that is first order independent of capacitor matching. This enables its use in new digital technology processes, such as Complementary Metal-Oxide Semiconductor (CMOS) processes, that are uncharacterized for capacitor matching and analog performance.
  • CMOS Complementary Metal-Oxide Semiconductor
  • the another exemplary embodiment of the present invention adds capacitor voltages only, with the amplifier serving as a buffer.
  • a signal voltage may be sampled onto two capacitors on one clock cycle.
  • one of the capacitors is placed in the feedback loop of the amplifier, and the other capacitor is inverted and connected between the amplifier's negative input terminal and any one of a predetermined number of voltages used in the 1.5-bit stage (e.g., +Vref, 0, -Vref), giving rise to an effective doubling of the input sample voltage combined with subtraction of one of the predetermined voltages.
  • a predetermined number of voltages used in the 1.5-bit stage e.g., +Vref, 0, -Vref
  • the resulting voltage is held at an output on a subsequent clock cycle so that it can be, for example, sampled by a subsequent stage of a pipeline ADC, or sampled in once again by a subsequent set of capacitors in an algorithmic ADC.
  • a straightforward and fast ADC architecture is the flash architecture, where a number of parallel comparator circuits compare sampled/held analog signals with different reference levels.
  • each reference level should be no further than one least significant bit (LSB) apart, a large number of comparators may be required for such an architecture.
  • LSB least significant bit
  • an N-bit ADC requires 2 n comparators.
  • the full scale input is a relatively small voltage
  • the LSB size will be relatively small, and the offset of the comparator needs to be very small which may be difficult to achieve with technologies such as CMOS, and special circuit techniques may be required.
  • Flash ADCs are therefore generally limited to smaller resolution converters, such as 8-bit or less resolution.
  • Two-step flash architectures arose to address some of the problems of flash ADCs, where the two-step flash ADCs first performs a course quantization, the held signal is the subtracted from an analog version of the course quantization, and the residue is then more finely quantized. This significantly reduces the number of comparators required in a standard flash ADC architecture, but additional clock cycles are required to process the signal due to the extra stage.
  • Another enhancement arose, where interstage gain was used to tolerate larger comparator offset for second stage comparators, which ultimately led to the pipelined ADC architecture employing multiple stages. The sampled input at each stage of a pipelined ADC architecture is converted to a particular resolution of the stage, such as n bits.
  • An ADC architecture resolving 1 bit per stage with one-half bit overlap is referred to as a "1.5-bit" ADC architecture.
  • 1.5-bit An ADC architecture resolving 1 bit per stage with one-half bit overlap.
  • various embodiments of the description provided herein are described in terms of such a 1.5-bit architecture. Examples of such architectures are set forth below to provide an appropriate, representative context in which the principles of the another exemplary embodiment of the present invention may be described. However, it will be apparent to those skilled in the art from the description provided herein that the another exemplary embodiment of the present invention is scalable and equally applicable to other analogous ADC architectures.
  • FIG. 6 is a block diagram illustrating a typical 1.5-bit ADC stage 1100.
  • the circuit 1100 includes a sample-and-hold (S&H) circuit 1102, a 1.5-bit sub-ADC 1104, a 1.5-bit sub-DAC 1106, a subtractor 1108, and a multiplier 1110.
  • S&H sample-and-hold
  • Such an architecture is used in pipelined or algorithmic ACS to provide maximum bandwidth and low sensitivity to component mismatches. This is because each stage 1100 requires only two comparators (not shown) having an accuracy of +/-(Vref/4) for the 1.5-bit sub-ADC 1104, and one multiplier (e.g., amplifier) 1110.
  • the associated comparator and amplifier offset can easily be corrected using standard digital error correction (DEC) techniques.
  • DEC digital error correction
  • the input voltage "In” is sampled by the sample-and-hold 1102 and resolved into a 1.5-bit digital code in a course analog-to-digital sub-converter (sub-ADC) 1104.
  • sub-ADC course analog-to-digital sub-converter
  • the resulting 1.5-bit code 1112 is outputted to a digital error correction circuit.
  • the code is also converted, via a digital-to-analog sub-converter (sub-DAC) 1106, back into a course analog signal with one of three predetermined analog values, such as -Vref/2, 0, +Vref/2.
  • the result is subtracted from the sampled-and-held analog input signal "In” via subtractor 1108.
  • the resulting analog "residue” is gained up by a factor of two using the multiplier 1110 to become the input voltage for the successive conversion.
  • the analog equivalent of the sub-ADC 1104 output plus the output residue (prior to multiplication) is equal to the analog input voltage.
  • any perturbation in the residue due to non-idealities can introduce differential nonlinearity (DNL) errors.
  • DNL differential nonlinearity
  • An N-bit algorithmic ADC 200 shown in FIG. 2 is formed by sampling the input signal on the first clock cycle, and sampling the output of the 1.5-bit stage 202 on the next N-1 cycles.
  • the 1.5-bit data 204 from each rotation are added up with 1-bit overlap in the DEC 1206 circuit such that the least significant bit (LSB) from one rotation is added to the most significant bit (MSB) from the next rotation.
  • Each rotation of the ADC resolves one effective bit from the MSB level down to the LSB-1 level.
  • the final LSB bit is often resolved using a simple 1-bit flash 1208, e.g., a comparator with its threshold set to 0V. This bit 1210 is not added, but rather is concatenated to the parallel data 1212 of the DEC 1206.
  • the pipelined ADC 1300 includes a series of N-2 stages 1300, 1302,...1304, such as those described in connection with FIG. 6 , as well as an Nth stage 1306. Stages 1300, 1302,...1304 may be used to resolve N-2 bits, with the final stage 1308 being a 2-bit flash to absolutely resolve the final two bits.
  • the 1.5-bit data 1310, 1312,...1314 and 2-bit data 1316 is provided to the DEC 1318 to create the N-bit parallel output data 1320.
  • the sample rate of the pipeline is approximately N times faster than that of the algorithmic architecture, depending ultimately on what resolution flash converter is used for the final stage 1308.
  • Equation 1 An example of a residue transfer characteristic of the complete 1.5-bit ADC stage is shown in FIG. 9 .
  • the full signal range is between -Vref and +Vref.
  • Vout of Equation 1 may either be resampled into the algorithmic ADC on a subsequent rotation, or may become the input voltage for a subsequent stage of a pipelined ADC.
  • the transfer characteristic is affected by non-idealities in the analog hardware.
  • offsets in the amplifier and comparators can be corrected by the DEC.
  • the two remaining sources of error in an actual implementation include inaccuracies in the creation of the multiply-by-two (MX2) gain function (including subtraction of sub-DAC levels), and variations in the reference levels.
  • Variations in reference levels are issues only in pipelined ADCs, in which separate hardware in each 1.5-bit stage samples +Vref and -Vref, where uncorrelated errors can occur from stage to stage. Static errors in the reference levels are not an issue for algorithmic ADCs, since each rotation of the ADC samples the same references in the same way with the same hardware.
  • the absolute accuracy of the reference levels is not important in a differential implementation, as long as the reference levels are stable, within the usable dynamic range of the active circuitry, and do not vary from conversion to conversion. At most, the gain transfer is affected without affecting DNL/INL. Thus, the only two remaining sources of error that limit accuracy of the complete ADC are the accuracy of the multiply (MX2) function and the DAC levels (sub-DAC). In conventional implementations, this error is predominantly caused by capacitor mismatch.
  • the combined accuracy of the MX2 and sub-DAC functions must be better than one LSB of the remaining resolution of the ADC in order to guarantee no missing codes.
  • the first stage of the pipeline has the most stringent requirement here, as the MX2/sub-DAC functions for an N-bit ADC must be accurate to at least N-1 bits, which is the number of bits yet to be resolved after the first stage.
  • the required resolution of an N-bit algorithmic ADC is commensurate with the required resolution of the first stage of a pipeline, i.e., N-1 bits.
  • the accuracy of the MX2 amplifier with sub-DAC should be designed to be at least 0.5 LSBs of the remaining resolution, i.e., N bits accuracy.
  • FIG. 9 The effect of a gain error in the first stage of a pipeline, or the first rotation of an algorithmic, is illustrated in FIG. 9 .
  • the comparator levels of the two comparators of the 1.5-bit stage are set to -Vref/4 and +Vref/4 respectively. It can be seen that when the gain of the stage is too high, over-ranging can occur where the slope 400 of the MX2 is greater than the ideal slope 402 of the MX2. This causes the input signal to the next stage to go beyond the maximum allowable range ⁇ +Vref and -Vref ⁇ for conversion.
  • FIGs. 10A, 10B, and 10C show the effects on the complete transfer function of the ADC for gain errors and sub-DAC errors in the first stage of a pipeline or in the algorithmic ADC.
  • FIG. 10A shows the effect of a gain error greater than two in the MX2 which produces non-monotonicity and the potential for missing codes. Where the ideal gain is equal to two as shown on dashed line 1500, non-ideal gain error greater than two as shown on lines 1502A, 1502B, 1502C can result in missing digital output codes.
  • FIG. 10B shows the effect of a gain error less than two in the MX2 which produces missing codes. Where the ideal gain is again equal to two as shown on dashed line 500 of FIG.
  • FIG. 10B shows non-ideal gain error less than two as shown on lines 1504A, 1504B, 1504C can result in missing digital output codes.
  • FIG. 10C shows the effect of sub-DAC errors in the first stage of the ADC on the total transfer function.
  • the ideal transfer function is shown on dashed line 1506, and various representative DAC level shift errors are shown on lines 1508A, 1508B, and 1508C, which will result in missing codes.
  • These errors are caused by capacitor mismatch and non-linearity. In practice, all these errors will propagate from the MSB to the LSB level, eventually (and undesirably) producing a jagged transfer function for the complete ADC.
  • FIG. 11A A switched capacitor implementation of a 1.5-bit stage for a single-ended application is shown in FIG. 11A , a portion of which includes a prior art switched capacitor (SC) circuit 1600.
  • the switched capacitor circuit 1600 includes an amplifier 1602, two nominally equal capacitors C f 1604 and C s 1606, and several switches 1608, 1610, 1612, 1614, 1616, 1618, 1620. Two opposite phased clock signals, clk1 and clk2, are non-overlapping.
  • the switched capacitor circuit 1600 performs the level shifting, residue multiplication by two (MX2), and sample-and-hold buffering as is known in the art.
  • the input signal Vin is applied to the sub-ADC including comparators 1622, 1624, with voltage thresholds set at +Vref/4 and -Vref/4 respectively. Concurrently, the input signal Vin is sampled onto C s 1606 and C f 1604. At the end of the first clock phase, clk1, Vin is completely sampled onto C s 1606 and C f 1604, while the output of the sub-ADC 1622, 1624 is latched and held by latches associated with the latches and clock generator 1626. During clk2, C f 1604 is switched via switch 608 and placed across the amplifier 1602, completing its negative feedback loop 1628.
  • the reference levels can be generated accurately and is generally not a limitation on the realization of a high resolution ADC (e.g., 12-bit level).
  • the single factor that ultimately determines the maximum resolution of the ADC is the capacitor mismatch. This mismatch has two effects on the performance of current state-of-the-art designs, including 1) it affects the accuracy of the MX2 function, and 2) it affects the accuracy of the sub-DAC through the accuracy with which the DAC levels ⁇ -Vref, 0, +Vref ⁇ can be generated.
  • Such correction/calibration routines are needed to achieve a resolution better than ten bits due to the limitations of the processing technology on prior art ADC circuit architectures.
  • Complicated calibration routines exist which add area, power consumption, and latency to the conversion. Typically, many (e.g., up to seven) clock cycles per bit are needed to calibrate away capacitor mismatch errors.
  • Still a further point of issue can be capacitor linearity: any non-linearity in C s 1606 and C f 1604 of FIG. 11A will cause non-linearity in the MX2 amplifier 602 and cause differential nonlinearity (DNL) and integral non-linearity (INL) errors.
  • DNL differential nonlinearity
  • INL integral non-linearity
  • FIG. 11B illustrates a differential switched capacitor implementation of a 1.5-bit ADC stage.
  • the conventional switched capacitor implementation includes a differential amplifier 1650, as well as a differential input signal Vin 1652 and a differential output signal 1654.
  • the differential amplifier 1650 is used, charge is transferred between capacitors, and a capacitor ratio is still used to establish the gain (multiplication by 2, for example).
  • the gain multiplication by 2, for example.
  • all of the charge on one capacitor is transferred to the other capacitor, and any error in the charge transfer results in errors in the total transfer function.
  • a double-sampling ADC stage may be realized that samples the inputs on a first clock phase clk1 and delivers its output on a second clock phase clk2, and can also sample the inputs on clk2 and deliver its output on clk1 through the use of an additional set of capacitors. By doubling the capacitors in this way, it is possible to double the conversion rate of the ADC for the same analog power dissipation.
  • the another exemplary embodiment of the present invention addresses a number of shortcomings of prior art ADC technologies, including the aforementioned error situations exhibited by current ADC technologies.
  • the another exemplary embodiment of the present invention significantly reduces errors in the MX2 (or other multiplier) function, as well as errors in the generation of DAC levels, that are present in conventional ADC technologies.
  • the another exemplary embodiment of the present invention is first order independent of capacitor matching, enabling accurate, relatively high bit-width ADCs in CMOS (and other technologies) that are otherwise uncharacterized for matching of analog components.
  • the apparatus and methodology in accordance with the another exemplary embodiment of the present invention allows for use of simple metal layer capacitors as the signal capacitors, while still achieving accurate, high bit-width performance.
  • the another exemplary embodiment of the present invention is also substantially faster than prior art ADCs employing analogous hardware.
  • the another exemplary embodiment is substantially faster than the prior art systems by virtue of the fact that the feedback factor (and, consequently the gainbandwidth) for the amplifiers is substantially larger.
  • FIG. 12A a block diagram of a representative 1.5-bit ADC stage 1700 corresponding to a first half of a differential implementation is illustrated.
  • FIG. 12B illustrates a second half of the representative differential implementation.
  • Two opposite phased clock signals are used, namely clock phases clk1 and clk2.
  • In_p 1702 of the differential input signal is sampled onto capacitance C 1a 1704 with respect to ground on clock phase clk1 by closing switches 1706 and 1708.
  • switches 1706 and 1708 During clock phase clk1 of the illustrated embodiment, a number of other different switches are closed, including switches 1714 and 1716.
  • In_n 1720 of the differential input signal is also sampled onto capacitance C 3a 1722 due to switches 1714 and 1716 being closed during clock phase clk1.
  • bottom plate sampling is used, where the input signals In_p 1702 and In_n 1720 are sampled on to the bottom plate of the capacitances C 1a 1704 and C 3a 1722 respectively.
  • the top plates of capacitances C 1a 1704 and C 3a 1722 are coupled to ground during the clk1 phase.
  • C 1a 1704 is connected across the amplifier 1724 due to switches 1726 and 1728 closing, and switches 1706 and 1708 opening.
  • the top plate of capacitance C 1a 1704 is coupled to the negative input 1730 of the amplifier 1724
  • the bottom plate of capacitance C 1a 1704 is coupled to the output (Out_p 1732) of the amplifier 1724.
  • Assertion of clock phase clk2 also causes capacitance C 3a 1722 to have its bottom plate connected to any one of the voltages +Vref, 0, -Vref.
  • Such voltages are controllably selected by sub-DAC control signals labeled as the top (top_a), middle (mid_a), or bottom (bot_a).
  • the top plate of capacitance C 3a 1722 is then coupled to the positive input terminal 734 of the amplifier 1724 on clk2.
  • one of the output control signals of the sub-DAC i.e., bot_a, mid_a, top_a
  • one of the output control signals of the sub-DAC selects a corresponding +Vref, 0, or -Vref voltage, which in turn serves as a reference voltage to the capacitance C 3a 1722 during the second clock phase clk2.
  • In_p is added to an inverted version of In_n, while at the same time it is level shifted by either +Vref, 0, -Vref. This is accomplished without ever creating a transfer of charge between capacitors.
  • C 2a 1736 and C 4a 1738 perform similar functions to those described in connection with C 1a 1704 and C 3a 1722, but with opposite phased clock signals. More particularly, In_p 1702 of the differential input signal is sampled onto capacitance C 2a 1736 with respect to ground on clock phase clk2 by closing switches 1740 and 1742. During clock phase clk2 of the illustrated embodiment, In_n 720 of the differential input signal is also sampled onto capacitance C 4a 1738 due to switches 1744 and 1746 being closed during clock phase clk2.
  • bottom plate sampling is used, where the input signals In_p 1702 and In_n 1720 are sampled on to the bottom plate of the capacitances C 2a 1736,and C 4a 1738 respectively.
  • the top plates of capacitances C 2a 1736 and C 4a 1738 are coupled to ground during the clk2 phase.
  • clk1, C 2a 1736 is connected across the amplifier 1724 due to switches 1748 and 1750 closing, and switches 1740 and 1742 opening.
  • the top plate of capacitance C 2a 1736 is coupled to the negative input 1730 of the amplifier 1724
  • the bottom plate of capacitance C 2a 1736 is coupled to the output (Out_p 1732) of the amplifier 1724.
  • Assertion of clock phase clk1 also causes capacitance C 4a 1738 to have its bottom plate connected to any one of the voltages +Vref, 0, -Vref, in response to the appropriate control output from the sub-DAC.
  • Such sub-DAC control signals are labeled as the top (top_a), middle (mid_a), or bottom (bot_a).
  • the top plate of capacitance C 4a 1738 is then coupled to the positive input terminal 1734 of the amplifier 1724.
  • one of the output control signals of the sub-DAC i.e., bot_a, mid_a, top_a
  • selects the corresponding voltage +Vref, 0, or -Vref which in turn serves as a reference voltage to the capacitance C 4a 1738 during the first clock phase clk1.
  • the inputs In_p 1702 and In_n 1720 can be processed at double the rate of a single-sampling implementation, thereby doubling the conversion speed of the ADC using such circuit stages.
  • FIG. 12B illustrates a representative 1.5-bit ADC stage 1760 corresponding to the second half of the differential implementation described in connection with FIG. 12A .
  • the circuit stage 760 operates in an analogous manner as that described in connection with FIG. 12A , using another set of capacitances C 1b 1762 and C 3b 1764, as well as capacitances C 2b 1766 and C 4b 1768 for the double-sampling implementation.
  • the circuit 1760 forms a second half of a differential implementation, the input signals In_p 1702 and In_n 1720 are reversed such that the input signal In_n 1720 is ultimately coupled to the negative input 1730 of the amplifier 1724, and the input signal In_p 1702 is ultimately coupled to the positive input 1734 of the amplifier 1724.
  • the amplifier 1724 outputs the other differential signal, shown as output signal Out_n 1770 in FIG. 12B . Otherwise, the operation is analogous to that described in connection with FIG. 12A , ultimately producing differential output signals Out_p 1732 and Out_n
  • FIG. 13 illustrates an implementation of the differential ADC stage 1800 described in connection with FIGs. 12A and 12B .
  • the illustrated embodiment represents an implementation of the differential ADC stage in the context of an algorithmic ADC.
  • circuit stages 1802 and 1804 correspond respectively to the circuits 1700 and 1760 described in connection with FIGs. 12A and 12B .
  • refcm common mode voltage
  • refcm common mode voltage
  • a single supply voltage may be used (i.e., 0 to Vdd).
  • the illustrated ADC stage 1800 is applied in an algorithmic ADC as previously described in connection with FIG.
  • ADC_clk and ADC_clk_n such that ADC_clk is high for one clock period and ADC_clk_n is high for the remaining N-2 clock periods as explained in connection with FIG. 7 .
  • the differential analog input signal i.e., In_p 1806; In_n 1808) is sampled at the start of each conversion, using ADC_clk, while the gating with ADC_clk_n ensures that the differential output signal (i.e., Out_p 1810; Out_n 1812) is sampled for the remaining N-2 clock periods.
  • a final instantaneous decision can be made with a 1-bit flash to determine the last bit, giving a total of N-1 clock cycles to resolve N bits.
  • refcm may be nominally set halfway between refp and refn, but its exact position is not critical.
  • FIG. 14 illustrates a representative waveform diagram corresponding to an algorithmic ADC such as described in connection with FIG. 13.
  • a master clock 1900 is provided, where clk1 and clk2 are non-overlapping phases of the clock.
  • clocks ADC_clk 1906 and ADC_clk_n 1908 are non-overlapping, such that ADC_clk 1906 is high for one clock period and ADC_clk_n 1908 is high for the remaining N-2 clock periods.
  • the data ready signal (DRDY) 1914 is asserted when the ADC_clk 1906 is asserted, thereby allowing the parallel data 1912 to begin accumulating the associated digital data.
  • DRDY data ready signal
  • Non-overlapping clocks with early turn-off times i.e., clk1_e 1914 and clk2_e 1916, may be applied in the implementation of the algorithmic ADC.
  • the input switches switching with respect to refcm switch off early in one embodiment of the invention.
  • switches connecting the capacitors to the inputs of the amplifiers should switch off late in accordance with this embodiment of the invention. In this manner, when in cyclic mode, the outputs of the amplifiers can be sampled by the oppositely-phased capacitor networks before any switching occurs around the amplifiers, ensuring clean sampling.
  • FIGs. 15A and 15B An example of an ADC stage corresponding to a first half of a differential, algorithmic ADC implementation, such as that described in connection with FIG. 13, is illustrated in FIGs. 15A and 15B .
  • the example of FIGs. 15A and 15B is provided as a representative implementation, and those skilled in the art will appreciate that many variations to such an implementation are possible.
  • FIG. 15A corresponds to the circuitry coupled to the negative input of an amplifier, such as the switches and capacitors coupled to the negative input of the amplifier shown in block 1802 of FIG. 13.
  • an amplifier such as the switches and capacitors coupled to the negative input of the amplifier shown in block 1802 of FIG. 13.
  • two opposite phased clock signals are used, namely clock phases clkl and clk2.
  • the signal In_p 2000 of the differential input signal is sampled onto capacitance C 1a 2002 with respect to a reference voltage such as refcm, on clock phase clk1 2004.
  • the signal 2000 is sampled onto C 1a 2002 via switch circuit 2006.
  • the ADC_clk 2008 enables the clk1 2004 to be passed for one clock period, via the NAND gate 2010 and associated inverters 2012, 2014 to the CMOS switch 2016.
  • the switch 2016 samples the In_p 2000 signal onto C 1a 2002 with respect to the reference voltage through CMOS switch 2018 when switched by the early turn-off clock clk1_e 2020.
  • clk2 2022, C 1a 2002 is coupled to the negative terminal 2024 of the amplifier via switch circuit 2026.
  • the ADC_clk_n 2028 is high for the remaining N-2 clock periods, thereby gating the appropriate clock phase to the CMOS switch 2030 via the logic components 2032, 2034, 2036, 2038.
  • the output signal Out_p 2040 from the output of the amplifier (not shown), is thus fed back to switch 2030 and coupled to the bottom plate of the capacitor C 1a on clk2 2022.
  • switch circuits 2042 and 2044 are also provided. These switch circuits 2042, 2044 operate analogously to switch circuits 2006 and 2026 respectively, with the clk1 2004 and clk2 2022 signals reversed with respect to switch circuits 2006 and 2026.
  • In_p 2000 is sampled onto capacitance C 2a 2046, and on the next clock phase C 2a 2046 is coupled to the negative terminal 2024 of the amplifier via switch circuit 2048.
  • FIG. 15B corresponds to a portion of the circuitry coupled to the positive input of an amplifier, such as the switches and capacitors coupled to the positive input of the amplifier shown in block 802 of FIG. 13. Because the circuits associated with each of the capacitors C 3a and C 4a in a double-sampling implementation of FIG. 13 are analogous, only the circuitry of one such circuit is described in FIG. 15B .
  • In_n 2050 is sampled onto capacitance C 4a 2052 via switch circuit 2054. This occurs when clk2 2056 is high, and ADC_clk 2008 is asserted on the first clock period of the algorithmic implementation.
  • NAND gate 2056 and inverters 2058, 2060 enable passage of the In_n 2050 signal through the CMOS switch 2062 to be sampled on to C 4a 2052.
  • ADC_clk_n 2028 gates the clk2 2022 signal via switch circuit 2064, which includes NAND gate 2066 and inverters 2068, 2070, such that passage of the Out_n 2072 signal from the differential counterpart circuit is enabled through switch 2074 to be sampled on to C 4a 2052, and ultimately switched via switch 2074 to the positive terminal 2076 of the amplifier.
  • the sub-DAC provides control signals, such as bot_b, mid_b, and top_b, which selectively provide a corresponding voltage refp, refcm, or refn to the bottom plate of the capacitor C 4a via the level-shifting circuit 2078.
  • control signals such as bot_b, mid_b, and top_b
  • one of the output control signals of the sub-DAC i.e., bot_b, mid_b, top_b
  • bot_b, mid_b, top_b allows a corresponding voltage to level shift the voltage at the positive terminal 2076 of the amplifier.
  • Amplifiers that may be used in connection with the another exemplary embodiment of the present invention can retain a significant amount of residual charge when switching from one N-bit conversion to the next. This is due to the parasitic capacitance at the input to the amplifiers, where this parasitic capacitance includes the oxide input capacitance of the amplifier, wiring capacitance, switch diffusion capacitance, etc. This charge is transferred to the signal capacitors at the start of the next new conversion, giving rise to a substantial degradation in performance when any over-range occurs in the ADC (i.e., an input signal which has an amplitude larger than refp-refn).
  • a novel amplifier reset methodology is implemented to address this residual charge problem between conversions.
  • a number of reset switches are timed to remove the residual charge on the amplifier terminals, while performing the N-bit conversion in N clock cycles of the master clock.
  • the final decision is instantaneous and becomes available with the final LSB+1 bit in the DEC.
  • the N-bit conversion can be performed in only one additional clock cycle, thereby resulting in an N-bit conversion in N clock cycles of the master clock. If no such reset action were performed, and the input were to fall below 0V for example, then the input signal must reach a minimum level of the offset that has been transferred to the signal capacitors before the ADC starts to convert properly again. Therefore, the reset circuit used in connection with the another exemplary embodiment of the present invention dramatically improves the performance of the algorithmic ADC.
  • FIG. 16 illustrates a representative portion of an algorithmic ADC stage 2100 which implements such a reset circuit.
  • the amplifier 2102 a single-ended amplifier in the illustrated embodiment, includes a negative input 2104, a positive input 2106, and an output 2108.
  • the derived clock signal ADC_clk 2110 may be used to trigger the initial sampling of the input signal in an algorithmic ADC
  • the derived clock signal ADC_clk_n 2112 is used for the remaining N-2 clock periods.
  • the amplifier 2102 can be reset. It should be recognized that the amplifier 2102 can be reset using an additional clock cycle rather than during the sampling-in period corresponding to the ADC_clk 2110, however resetting the amplifier during this period allows the total conversion to be minimized.
  • each of the switches 2114, 2116, 2118, and 2120 close, and discharge any charge to a reference voltage which is refcm in the illustrated embodiment.
  • Reset switch 2114 is coupled between the negative input 2104 of the amplifier 2102 and refcm
  • reset switch 2118 is coupled between the positive input 2106 of the amplifier 2102 and refcm.
  • a reset switch 2116 is also coupled between the negative 2104 and positive 2106 inputs of the amplifier, which in turn are coupled to refcm.
  • reset switch 2120 is coupled between the amplifier 2102 output 2108 and refcm.
  • FIG. 17 is an example of how the another exemplary embodiment of the present invention may be implemented in a non-differential, single-sampling ADC stage 2200.
  • Vin 2202 is sampled onto a first capacitor C 1 2204 when switches 2206, 2208 are closed during clk1.
  • a complemented version of the Vin 2202 signal is generated in any known manner, represented by the inverter 2210.
  • Vin' 2212 is sampled onto C 2 2214 during clk1 when switches 2216, 2218 are closed.
  • the Vin 2202 signal is also received at the sub-ADC circuit 2220 of a level shifting circuit 2230, where the sub-ACD circuit 2220 provides the 1.5-bit (or other) data 2221, the value of which depends on the Vin 2202 analog voltage level.
  • This 1.5-bit digital output is received by the decoder/clock generator (clkgen) circuit 2222.
  • the decoder/clkgen 2222 asserts one of a plurality of control signals based on the 1.5-bit data 2221, such as the "bottom,” “middle,” or top” signals.
  • the asserted one of the bottom, middle, or top signals closes a corresponding one of the switches 2224, 2226, 2228 of the level shift circuit 2230.
  • the corresponding reference voltage -Vref, 0, +Vref is used to shift the output signal RESIDUE 2232 of the amplifier 2234, by providing the selected reference voltage to the positive input 2235 of the amplifier 2234.
  • the RESIDUE 2232 signal 2232 is generated during the clk2 phase, where the sampled voltage on C 1 2204 is coupled between the output 2236 and the negative terminal 2238 of the amplifier 2234, due to switches 2240 and 2242 closing and switches 2206 and 2208 opening. Further, the sampled voltage on C 2 2214 is coupled to the positive input 2235 of the amplifier 2234 when switch 2244 closes in response to clk2.
  • the Vin 2202 signal is therefore inverted, and the complementary signals Vin 2202 and Vin' 2212 are sampled, and provided to the amplifier 2234 as the Vin 2202 signal and an inverted version of the complemented Vin signal, to provide the MX2 function by adding these signals.
  • the RESIDUE 2232 is provided as a result of the subtraction of the voltage provided by the level shift circuit 2230 and the MX2 function performed at the amplifier 2234. As can be seen, the subtraction/level shifting, residue multiplication by two, and sample/hold functions are all performed in one clock cycle, independent of any capacitor mismatch that may occur between the signal capacitors C 1 2204 and C 2 2214.
  • sub-ADC 2220, decoder/clkgen 2222, and level shift circuit 2230 are representative of the circuit (or equivalent thereof) that may be used to provide the coarse analog-to-digital conversion, decoding, and level shift functions for any of the embodiments of the present invention described herein.
  • FIG. 18 is a flow diagram of a method for converting an analog input signal to a digital input signal in accordance with one embodiment of the present invention.
  • the analog input signal is sampled 2300 onto a first capacitor, or group of capacitors or capacitive elements collectively providing a capacitance in which the input signal may be stored.
  • a complemented analog input signal i.e., an inversion of the analog input signal, is similarly sampled 2302 onto a second capacitor(s).
  • One or more switches are actuated 2304 in order to couple the first capacitor between the amplifier output and a first amplifier input, in a unity gain feedback arrangement.
  • the sampled input signal is thus provided to the first amplifier input, such as the inverting/negative amplifier input.
  • One or more switches are also actuated 2306 in order to couple the second capacitor between a selected reference voltage and a second amplifier input, in order to provide an inverted version of the sampled complemented input signal to the first amplifier input as level-shifted by the selected reference voltage.
  • the sampled input signal is added 2308 to the inverted version of the complemented input signal using the amplifier, and the selected reference voltage is effectively subtracted from the output in order to provide a residue signal available for use in subsequent conversion stages.
  • next stage 2312 is considered, and the process is repeated for that stage.
  • the final flash stage can be processed 2314 as previously described.
  • the resulting ADC is substantially faster than prior art ADCs employing analogous hardware.
  • the use of amplifiers and capacitors in both prior art systems and in the another exemplary embodiment of the present invention, the another exemplary is substantially faster than the prior art systems by virtue of the fact that the feedback factor (and, consequently the gainbandwidth) for the amplifiers is substantially larger.

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Abstract

La présente invention concerne un appareil et un procédé d'ajout de signaux de tension d'entrée. Des premier (206) et deuxième (208) signaux de tension d'entrée sont respectivement échantillonnés sur des premier (218) et deuxième (228) condensateurs pendant une première phase d'horloge (202). En réponse à une deuxième phase d'horloge (204), la première tension d'entrée échantillonnée (206) qui est retenue sur le premier condensateur (218) est couplée à la borne d'entrée négative (236) d'un amplificateur (230) et la deuxième tension échantillonnée (208) retenue sur le deuxième condensateur (228) est couplée à la borne positive (240) de l'amplificateur (230). Une tension de retour est prévue entre la sortie (216) de l'amplificateur et la borne d'entrée négative (236) de l'amplificateur via le premier condensateur (218) pendant la deuxième phase d'horloge (204). Les premier et deuxième signaux de tension d'entrée (206) et (208) sont ajoutés à l'amplificateur (230) pendant la deuxième phase d'horloge (204) pour produire (216) la somme en réponse aux signaux de tension d'entrée échantillonnés et à la tension de retour, ceci produisant une fonction de transfert résultante qui est indépendante de la non linéarité et du décalage entre les condensateurs.

Claims (30)

  1. Circuit (200, 300) destiné à ajouter une pluralité de signaux d'entrée, comprenant :
    un amplificateur (230, 322) présentant des bornes d'entrée inverseuse (236, 328) et non-inverseuse (240, 332) et une borne de sortie (216, 308) ;
    un premier circuit d'échantillonnage couplé entre un premier signal d'entrée (206, 302) et un premier signal de référence (212) pour stocker une première tension à travers un premier condensateur (218, 310) en réponse à une première phase d'horloge (202) ;
    un deuxième circuit d'échantillonnage couplé entre un deuxième signal d'entrée (208, 304) et un deuxième signal de référence (210, 252) pour stocker une deuxième tension à travers un deuxième condensateur (228, 312) en réponse à la première phase d'horloge (202) ; et
    un circuit de commutation (220, 222, 224, 226, 232, 234, 238, 242, 314, 316, 318, 320, 324, 328, 330, 334, 338, 340, 342, 344, 346, 348, 350, 352) couplé à l'amplificateur (230, 322) et aux premier et deuxième circuits d'échantillonnage, dans lequel, en réponse à une seconde phase d'horloge (204), le circuit de commutation commute le premier condensateur (218, 310) stockant la première tension entre la borne d'entrée inverseuse (236, 328) et la borne de sortie (216, 308) de l'amplificateur (230, 322), et commute en outre le deuxième condensateur (228, 312) stockant la deuxième tension entre la borne d'entrée non-inverseuse (240, 332) et un troisième signal d'entrée (214, 306).
  2. Circuit selon la revendication 1, comprenant en outre un signal d'horloge à N phases comprenant les première (202) et seconde (204) phases d'horloge et les phases d'horloge restantes du signal d'horloge à N phases, et dans lequel le circuit de commutation commute le premier condensateur (218, 310) entre la borne d'entrée inverseuse (236, 328) et la borne de sortie (216, 308) de l'amplificateur (230, 322), et commute le deuxième condensateur (228, 312) entre la borne d'entrée non-inverseuse (236, 332) et un troisième signal d'entrée (214, 306), en réponse à des phases sélectionnées de la seconde phase d'horloge (204) et des phases d'horloge restantes du signal d'horloge à N phases.
  3. Circuit selon la revendication 1, dans lequel le premier signal de référence (206) comprend une tension de référence en c.c. ou un signal variable dans le temps.
  4. Circuit selon la revendication 1, dans lequel les premier (202) et deuxième (204) signaux de référence comportent une tension de référence en c.c. commune.
  5. Circuit selon la revendication 1 :
    (a) comprenant en outre :
    (i) un troisième circuit d'échantillonnage couplé entre le premier signal d'entrée (302) et le premier signal de référence pour stocker une troisième tension à travers un troisième condensateur (336) en réponse à la seconde phase d'horloge (204) ;
    (ii) un quatrième circuit d'échantillonnage couplé entre le deuxième signal d'entrée (304) et le deuxième signal de référence pour stocker une quatrième tension à travers un quatrième condensateur (338) en réponse à la seconde phase d'horloge (204) ; et
    (b) dans lequel le circuit de commutation est en outre couplé aux troisième et quatrième circuits d'échantillonnage, dans lequel, en réponse à la première phase d'horloge, le circuit de commutation commute le troisième condensateur (336) stockant la troisième tension entre la borne d'entrée inverseuse (328) et la borne de sortie de l'amplificateur (308), et commute en outre le quatrième condensateur (338) stockant la quatrième tension entre la borne d'entrée non-inverseuse (332) et le troisième signal d'entrée (306).
  6. Procédé destiné à ajouter au moins deux signaux de tension d'entrée (206, 208, 302, 304), comprenant les étapes ci-dessous consistant à :
    échantillonner des premier (206, 302) et deuxième (208, 304) signaux de tension d'entrée sur des premier (218, 310) et deuxième (228, 312) circuits de condensateur respectivement, au cours d'une première phase d'horloge (202) ;
    coupler la première tension d'entrée échantillonnée (206, 302) maintenue sur le premier circuit de condensateur (218, 310) à une borne d'entrée négative (236, 328) d'un amplificateur (230, 322) et coupler la deuxième tension d'entrée échantillonnée (208, 304) maintenue sur le deuxième circuit de condensateur (228, 312) à une borne d'entrée positive (240, 332) de l'amplificateur (230, 322) au cours d'une seconde phase d'horloge (204) ;
    fournir une tension de rétroaction, d'une sortie (216, 308) de l'amplificateur (230, 322) à l'entrée négative (236, 328) de l'amplificateur (230, 322), via le premier circuit de condensateur (218, 310) au cours de la seconde phase d'horloge (204) ; et
    générer en sortie une somme des premier (206, 302) et deuxième (208, 304) signaux de tension d'entrée en réponse à la tension de rétroaction et des première (206, 302) et deuxième (208, 304) tensions d'entrée échantillonnées au cours de la seconde phase d'horloge (204).
  7. Procédé selon la revendication 6, comprenant en outre l'étape consistant à décaler le niveau de tension à la sortie (216, 308) au cours de la seconde phase d'horloge (204) en appliquant une tension de niveau de décalage (214, 306) au deuxième circuit de condensateur (228, 312) en vue de modifier algébriquement la deuxième tension d'entrée échantillonnée (208, 304) présente au niveau de la borne d'entrée positive (240, 332) de l'amplificateur (230, 322).
  8. Procédé selon la revendication 6, comprenant en outre l'étape consistant à activer au moins un commutateur en vue de créer une connexion électrique entre le deuxième circuit de condensateur (228, 312) et la tension de niveau de décalage (214, 306) en réponse à la seconde phase d'horloge (204).
  9. Procédé selon la revendication 6, comprenant en outre les étapes ci-dessous consistant à :
    échantillonner les premier (302) et deuxième (304) signaux de tension d'entrée sur des troisième (238) et quatrième (338) circuits de condensateur, respectivement, au cours de la seconde phase d'horloge (204) ;
    coupler la première tension d'entrée échantillonnée (302) maintenue sur le troisième circuit de condensateur (336) à la borne d'entrée négative (328) de l'amplificateur (322), et coupler la deuxième tension d'entrée échantillonnée (304) maintenue sur le quatrième circuit de condensateur (338) à la borne d'entrée positive (332) de l'amplificateur (322), au cours de la première phase d'horloge (302) ;
    fournir une deuxième tension de rétroaction, d'une sortie (308) de l'amplificateur (322) à l'entrée négative (328) de l'amplificateur (322) via le troisième circuit de condensateur (336) au cours de la première phase d'horloge (202) ; et
    générer en sortie une somme des premier (302) et deuxième (304) signaux de tension d'entrée en réponse à la tension de rétroaction et des première (302) et deuxième (304) tensions d'entrée échantillonnées au cours de la première phase d'horloge (202).
  10. Procédé selon la revendication 9, comprenant en outre l'étape consistant à décaler le niveau de tension à la sortie (308) au cours de la seconde phase d'horloge en appliquant une tension de niveau de décalage (306) au deuxième circuit de condensateur (312) en vue de modifier algébriquement la deuxième tension d'entrée échantillonnée présente au niveau de la borne d'entrée positive (332) de l'amplificateur (322).
  11. Procédé selon la revendication 9, comprenant en outre l'étape consistant à décaler le niveau de tension à la sortie (308) au cours de la première phase d'horloge (202) en appliquant une tension de niveau de décalage (306) au quatrième circuit de condensateur (338) en vue de modifier algébriquement la deuxième tension d'entrée échantillonnée présente au niveau de la borne d'entrée positive (332) de l'amplificateur (322).
  12. Procédé selon la revendication 6, dans lequel l'étape consistant à coupler la première tension d'entrée échantillonnée (206, 302) maintenue sur le premier circuit de condensateur (218, 310) à la borne d'entrée négative (236, 328) de l'amplificateur (230, 322) comprend l'étape consistant à activer au moins un commutateur (232, 234, 324, 326) en réponse à la seconde phase d'horloge (204) en vue de créer une connexion électrique entre le premier circuit de condensateur (218, 310) et la borne d'entrée négative (236, 328) de l'amplificateur (230, 322).
  13. Procédé selon la revendication 6, dans lequel l'étape consistant à coupler la deuxième tension d'entrée échantillonnée (208, 304) maintenue sur le deuxième circuit de condensateur (228, 312) à la borne d'entrée positive (240, 332) de l'amplificateur (230, 322) comprend l'étape consistant à activer au moins un commutateur (238, 242, 330, 334) en réponse à la seconde phase d'horloge (204) en vue de créer une connexion électrique entre le deuxième circuit de condensateur (228, 312) et la borne d'entrée positive (240, 332) de l'amplificateur (230, 322).
  14. Circuit selon la revendication 1, comportant en outre un étage de convertisseur analogique-numérique (CAN) destiné à être utilisé dans des convertisseurs CAN, comprenant :
    un amplificateur (1724, 2234) présentant des première (1730, 2238) et seconde (1734, 2235) bornes d'entrée, et une borne de sortie (1732, 1770, 2232) pour fournir un signal résiduel de conversion CAN analogique ;
    des première (1704, 2204) et seconde (1722, 2214) capacitances couplées en vue d'échantillonner un signal de tension d'entrée (1702, 2202) et un signal de tension d'entrée complété (1720, 2212), respectivement, en réponse à une première phase d'horloge (clk1) ;
    un circuit de décalage de niveau (2230) couplé de manière à recevoir le signal de tension d'entrée, et de manière à sélectionner l'une d'une pluralité de tensions de référence en réponse à un deuxième signal d'horloge ;
    un premier circuit de commutateur (1706, 1708, 1726, 1728, 2206, 2208, 2240) couplé à la première capacitance (1704, 2204) pour fournir le signal de tension d'entrée échantillonné (1702, 2202) à la première borne d'entrée (1730, 2238) de l'amplificateur (1724, 2234), et pour coupler la borne de sortie (1732, 2232) de l'amplificateur (1724, 2234) à la première capacitance (1704, 2204) via une boucle de rétroaction, en réponse à la seconde phase d'horloge (clk2) ; et
    un deuxième circuit de commutateur (1714, 1716, 2218, 2244) couplé à la seconde capacitance (1722, 2214) pour fournir une version inversée du signal de tension d'entrée complété échantillonné (1720, 2212) à la seconde borne d'entrée (1734, 2235) de l'amplificateur (1724, 2234) et pour référencer la seconde capacitance à la tension de référence sélectionnée en réponse à la seconde phase d'horloge (clk2) ; et
    dans lequel l'amplificateur (1724, 2234) ajoute le signal d'entrée (1702, 2202) à la version inversée du signal d'entrée complété (1720, 2212), telle que décalée par la tension de référence sélectionnée pour créer le signal résiduel de conversion CAN analogique destiné à être utilisé dans un étage de conversion CAN subséquent.
  15. Circuit selon la revendication 14, dans lequel le circuit de décalage de niveau comprend :
    un sous-convertisseur CAN (2220) couplé de manière à recevoir le signal de tension d'entrée (2202) et à fournir un code numérique (2221) basé sur une tension du signal de tension d'entrée (2202) ;
    un circuit de décodeur (2222) couplé au sous-convertisseur CAN (2220) de manière à recevoir le code numérique (2221) et à affirmer l'un d'une pluralité de signaux de commutation en réponse à cela ; et
    une pluralité de commutateurs (2224, 2226, 2228), chacun couplé à l'une distincte de la pluralité des tensions de référence ; et
    dans lequel le signal affirmé parmi les signaux de commutation ferme l'un correspondant de la pluralité de commutateurs (2224, 2226, 2228) en vue de coupler l'une correspondante de la pluralité de tensions de référence à la seconde capacitance (2214) afin de l'ajouter à la version inversée (2212) de la tension d'entrée complétée échantillonnée.
  16. Circuit selon la revendication 15, dans lequel le code numérique est un code binaire à n bits présentant 2n valeurs possibles, et dans lequel chacune des 2 n valeurs possibles permet à l'un distinct de la pluralité de signaux de commutation d'être affirmé par le circuit de décodeur (2222).
  17. Circuit selon la revendication 15, dans lequel le code numérique est un code binaire à 1,5 bit présentant trois valeurs possibles, et dans lequel chacune des trois valeurs possibles permet à l'un distinct de la pluralité de signaux de commutation d'être affirmé par le circuit de décodeur (2222).
  18. Circuit selon la revendication 14, dans lequel :
    la première capacitance (1704, 2204) comprend au moins un condensateur présentant une plaque supérieure et une plaque inférieure ;
    la plaque supérieure du condensateur est couplée à une première tension de référence via le premier circuit de commutateur (1706, 1708, 1726, 1728, 2206, 2208, 2240) au cours de la première phase d'horloge (clk1) et à la première borne d'entrée (1730, 2238) de l'amplificateur (1724, 2234) via le premier circuit de commutateur au cours de la seconde phase d'horloge (clk2) ; et
    la plaque inférieure du condensateur est couplée au signal de tension d'entrée (1702, 2202) à travers le premier circuit de commutateur au cours de la première phase d'horloge (clk1), et à la borne de sortie (1732, 2232) de l'amplificateur (1724, 2232) via le premier circuit de commutateur au cours de la seconde phase d'horloge (clk2).
  19. Circuit selon la revendication 14, dans lequel :
    la seconde capacitance (1722, 2214) comprend au moins un condensateur présentant une plaque supérieure et une plaque inférieure ;
    la plaque supérieure du condensateur est couplée à une deuxième tension de référence via le deuxième circuit de commutateur (1714, 1716, 2218, 2244) au cours de la première phase d'horloge (clk1), et à la seconde borne d'entrée (1734, 2235) de l'amplificateur (1724, 2234) via le deuxième circuit de commutateur au cours de la seconde phase d'horloge (clk2) ; et
    la plaque inférieure du condensateur est couplée au signal de tension d'entrée complété (1720, 2212) à travers le deuxième circuit de commutateur au cours de la première phase d'horloge (clk1), et à la tension de référence sélectionnée par le circuit de décalage de niveau (2230) via le deuxième circuit de commutateur au cours de la seconde phase d'horloge (clk2).
  20. Circuit selon la revendication 14, comprenant en outre un circuit de réinitialisation (2110, 2114, 2116, 2118) couplé à l'amplificateur (1724, 2234, 2102) pour décharger une charge résiduelle présente au niveau d'une ou plusieurs des première (1730, 2104, 2238) et seconde (1734, 2106, 2235) bornes d'entrée et de la borne de sortie (1732, 2108, 2232) de l'amplificateur (1724, 2106, 2234) en vue de supprimer un signal résiduel de conversion CAN analogique de courant en préparation de la génération en sortie d'un signal résiduel de conversion CAN analogique subséquent.
  21. Circuit selon la revendication 14, dans lequel le signal de tension d'entrée et le signal de tension d'entrée complété comprennent des signaux de tension d'entrée complémentaires d'un signal de tension d'entrée différentiel.
  22. Circuit selon la revendication 14, comprenant en outre :
    des troisième (1736, 1766) et quatrième (1738, 1768) capacitances couplées de manière à échantillonner le signal de tension d'entrée (1702) et le signal de tension d'entrée complété (1720), respectivement, en réponse à la seconde phase d'horloge (clk2) ;
    un deuxième circuit de décalage de niveau couplé de manière à recevoir le signal de tension d'entrée, et à sélectionner l'une parmi une pluralité de deuxièmes tensions de référence en réponse à la première phase d'horloge (clk1) ;
    un troisième circuit de commutateur (1740, 1742, 1748, 1750) couplé à la troisième capacitance (1736, 1766) pour fournir le signal de tension d'entrée échantillonné (1702, 1720) à la première borne d'entrée (1730) de l'amplificateur (1724), et pour coupler la borne de sortie (1732, 1770) de l'amplificateur (1724) à la troisième capacitance (1736, 1766) via une seconde boucle de rétroaction, en réponse à la première phase d'horloge (clk1) ; et
    un quatrième circuit de commutateur (1744, 1746) couplé à la quatrième capacitance (1738, 1768) pour fournir une version inversée du signal de tension d'entrée complété échantillonné (1720, 1702) à la seconde borne d'entrée (1734) de l'amplificateur (1724) et pour référencer la quatrième capacitance (1738, 1768) au niveau de la deuxième tension de référence sélectionnée en réponse à la première phase d'horloge (clk1) ; et
    dans lequel l'amplificateur (1724) ajoute le signal d'entrée (1702, 1720) à la version inversée du signal d'entrée complété (1720, 1702), tel de décalé par la deuxième tension de référence sélectionnée, pour créer un deuxième signal résiduel de conversion CAN analogique destiné à être utilisé dans un étage de conversion CAN subséquent.
  23. Procédé selon la revendication 6, comprenant l'étape consistant à convertir un signal d'entrée analogique (1704, 2202) en un signal numérique, en utilisant un amplificateur (1724, 2234), comprenant les étapes ci-dessous consistant à :
    (a) échantillonner le signal d'entrée analogique (1704, 2202) sur un premier condensateur (1704, 2204) et un complément (1720, 2212) du signal d'entrée analogique sur un deuxième condensateur (1722, 2214) ;
    (b) fournir le signal d'entrée analogique échantillonné (1704, 2202) au niveau d'une première borne d'entrée (1730, 2238) de l'amplificateur (1714, 2234) en couplant de manière contrôlée le premier condensateur (1704, 2204) entre la sortie d'amplificateur (1732, 2232) et la première borne d'entrée (1730, 2238) dans une configuration de rétroaction à gain unitaire ;
    (c) fournir le signal d'entrée analogique complété échantillonné (1720, 2212), dont le niveau est décalé par l'une d'une pluralité de tensions de référence sélectionnables, au niveau d'une seconde borne d'entrée (1734, 2235) de l'amplificateur (1714, 2234) en couplant de manière contrôlée le deuxième condensateur (1722, 2214) entre l'une sélectionnée parmi les tensions de référence et la seconde borne d'entrée (1734, 2235) de l'amplificateur ; et
    (d) ajouter le signal d'entrée analogique échantillonné (1704, 2202) à une version inversée du signal d'entrée analogique complété échantillonné (1720, 2212) et soustraire la tension sélectionnée parmi les tensions de référence en vue de fournir un signal résiduel disponible pour une utilisation dans des étages de conversion subséquents.
  24. Procédé selon la revendication 23, comprenant en outre l'étape consistant à répéter les étapes (a)-(d) pour chacun des premiers M-1 étages d'une conversion d'analogique à numérique à M étages présentant une résolution de N bits.
  25. Procédé selon la revendication 24, comprenant en outre l'étape consistant à résoudre les bits de poids faible du signal numérique dans un Mième étage flash de la conversion analogique à numérique, en comparant le signal résiduel de l'étage M-1 à un ensemble de tensions de référence prédéterminées.
  26. Procédé selon la revendication 25, dans lequel l'ensemble de tensions de référence prédéterminées comporte 2n-1 tensions de référence, dans lequel n correspond à une résolution du Mième étage.
  27. Procédé selon la revendication 26, comprenant en outre l'étape consistant à résoudre N-M bits au niveau du Mième étage de la conversion analogique à numérique présentant la résolution de N bits.
  28. Procédé selon la revendication 23, comprenant en outre l'étape consistant à fournir un signal d'horloge à phases multiples comportant une première phase d'horloge (clk1) et une seconde phase d'horloge (clk2), et dans lequel l'étape (a) est mise en oeuvre au cours de la première phase d'horloge (clk1) et les étapes (b), (c) et (d) sont mises en oeuvre au cours de la seconde phase d'horloge (clk2).
  29. Procédé selon la revendication 28, dans lequel l'étape consistant à coupler de manière contrôlée le premier condensateur (1704, 2202) entre la sortie d'amplificateur et la première borne d'entrée comprend l'étape consistant à activer un ou plusieurs commutateurs (1726, 1728, 2240) couplés entre la sortie d'amplificateur (1732, 2232) et la première borne d'entrée (1730, 2238) en vue de compléter un chemin de circuit entre ces éléments en réponse à une transition de la seconde phase d'horloge (clk2).
  30. Procédé selon la revendication 29, comprenant en outre l'étape consistant à activer un ou plusieurs commutateurs d'échantillonnage couplés entre le signal d'entrée analogique (1702, 1720, 2202) et une tension de référence en réponse à une première transition de la première phase d'horloge (clk1), et l'étape consistant à désactiver les commutateurs d'échantillonnage en réponse à une seconde transition de la première phase d'horloge (clk1).
EP03791719A 2002-08-29 2003-08-20 Systeme de condensateur commute, procede correspondant et utilisation de ce dernier Expired - Lifetime EP1540565B1 (fr)

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Application Number Priority Date Filing Date Title
US10/231,541 US6784824B1 (en) 2002-08-29 2002-08-29 Analog-to-digital converter which is substantially independent of capacitor mismatch
US10/232,113 US6727749B1 (en) 2002-08-29 2002-08-29 Switched capacitor summing system and method
US232113 2002-08-29
US231541 2002-08-29
PCT/US2003/026198 WO2004021251A2 (fr) 2002-08-29 2003-08-20 Systeme de condensateur commute, procede correspondant et utilisation de ce dernier

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