CA2494264C - Systeme de condensateur commute, procede correspondant et utilisation de ce dernier - Google Patents
Systeme de condensateur commute, procede correspondant et utilisation de ce dernier Download PDFInfo
- Publication number
- CA2494264C CA2494264C CA2494264A CA2494264A CA2494264C CA 2494264 C CA2494264 C CA 2494264C CA 2494264 A CA2494264 A CA 2494264A CA 2494264 A CA2494264 A CA 2494264A CA 2494264 C CA2494264 C CA 2494264C
- Authority
- CA
- Canada
- Prior art keywords
- amplifier
- voltage
- capacitor
- input
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000003990 capacitor Substances 0.000 title claims abstract description 195
- 238000000034 method Methods 0.000 title claims abstract description 39
- 230000004044 response Effects 0.000 claims abstract description 31
- 238000005070 sampling Methods 0.000 claims description 57
- 230000008878 coupling Effects 0.000 claims description 7
- 238000010168 coupling process Methods 0.000 claims description 7
- 238000005859 coupling reaction Methods 0.000 claims description 7
- 230000003213 activating effect Effects 0.000 claims 3
- 238000012546 transfer Methods 0.000 abstract description 62
- 101100113692 Caenorhabditis elegans clk-2 gene Proteins 0.000 description 42
- 238000006243 chemical reaction Methods 0.000 description 24
- 101100112673 Rattus norvegicus Ccnd2 gene Proteins 0.000 description 18
- 238000013461 design Methods 0.000 description 11
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- 230000036039 immunity Effects 0.000 description 4
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- 230000003139 buffering effect Effects 0.000 description 3
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- 239000002184 metal Substances 0.000 description 3
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- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
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- 230000003068 static effect Effects 0.000 description 2
- 101100328957 Caenorhabditis elegans clk-1 gene Proteins 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
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- 238000006731 degradation reaction Methods 0.000 description 1
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- 230000007704 transition Effects 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06G—ANALOGUE COMPUTERS
- G06G7/00—Devices in which the computing operation is performed by varying electric or magnetic quantities
- G06G7/12—Arrangements for performing computing operations, e.g. operational amplifiers
- G06G7/14—Arrangements for performing computing operations, e.g. operational amplifiers for addition or subtraction
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06J—HYBRID COMPUTING ARRANGEMENTS
- G06J1/00—Hybrid computing arrangements
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Physics (AREA)
- General Physics & Mathematics (AREA)
- Software Systems (AREA)
- Computer Hardware Design (AREA)
- Automation & Control Theory (AREA)
- Evolutionary Computation (AREA)
- Fuzzy Systems (AREA)
- Amplifiers (AREA)
- Analogue/Digital Conversion (AREA)
- Filters That Use Time-Delay Elements (AREA)
Abstract
La présente invention concerne un appareil et un procédé d'ajout de signaux de tension d'entrée. Des premier (206) et deuxième (208) signaux de tension d'entrée sont respectivement échantillonnés sur des premier (218) et deuxième (228) condensateurs pendant une première phase d'horloge (202). En réponse à une deuxième phase d'horloge (204), la première tension d'entrée échantillonnée (206) qui est retenue sur le premier condensateur (218) est couplée à la borne d'entrée négative (236) d'un amplificateur (230) et la deuxième tension échantillonnée (208) retenue sur le deuxième condensateur (228) est couplée à la borne positive (240) de l'amplificateur (230). Une tension de retour est prévue entre la sortie (216) de l'amplificateur et la borne d'entrée négative (236) de l'amplificateur via le premier condensateur (218) pendant la deuxième phase d'horloge (204). Les premier et deuxième signaux de tension d'entrée (206) et (208) sont ajoutés à l'amplificateur (230) pendant la deuxième phase d'horloge (204) pour produire (216) la somme en réponse aux signaux de tension d'entrée échantillonnés et à la tension de retour, ceci produisant une fonction de transfert résultante qui est indépendante de la non linéarité et du décalage entre les condensateurs.
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/231,541 US6784824B1 (en) | 2002-08-29 | 2002-08-29 | Analog-to-digital converter which is substantially independent of capacitor mismatch |
| US10/232,113 | 2002-08-29 | ||
| US10/232,113 US6727749B1 (en) | 2002-08-29 | 2002-08-29 | Switched capacitor summing system and method |
| US10/231,541 | 2002-08-29 | ||
| PCT/US2003/026198 WO2004021251A2 (fr) | 2002-08-29 | 2003-08-20 | Systeme de condensateur commute, procede correspondant et utilisation de ce dernier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2494264A1 CA2494264A1 (fr) | 2004-03-11 |
| CA2494264C true CA2494264C (fr) | 2011-07-26 |
Family
ID=31980956
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA2494264A Expired - Lifetime CA2494264C (fr) | 2002-08-29 | 2003-08-20 | Systeme de condensateur commute, procede correspondant et utilisation de ce dernier |
Country Status (4)
| Country | Link |
|---|---|
| EP (1) | EP1540565B1 (fr) |
| JP (1) | JP4454498B2 (fr) |
| CA (1) | CA2494264C (fr) |
| WO (1) | WO2004021251A2 (fr) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4654998B2 (ja) * | 2005-11-08 | 2011-03-23 | 株式会社デンソー | サンプルホールド回路およびマルチプライングｄ／ａコンバータ |
| JP5155103B2 (ja) | 2008-11-05 | 2013-02-27 | 旭化成エレクトロニクス株式会社 | スイッチトキャパシタ回路およびパイプライン型ａ／ｄコンバータ |
| US8648779B2 (en) | 2009-10-20 | 2014-02-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | LCD driver |
| US8339302B2 (en) | 2010-07-29 | 2012-12-25 | Freescale Semiconductor, Inc. | Analog-to-digital converter having a comparator for a multi-stage sampling circuit and method therefor |
| CN102654987B (zh) * | 2012-02-03 | 2014-10-15 | 京东方科技集团股份有限公司 | Tft-lcd基板像素点充电方法、装置及源驱动器 |
| KR101876605B1 (ko) * | 2014-10-30 | 2018-07-11 | 한국과학기술원 | 파이프라인 구조의 정합 필터와 듀얼 경사 아날로그 디지털 변환기를 이용한 광분광학 시스템 및 그 제어 방법 |
| US10714185B2 (en) * | 2018-10-24 | 2020-07-14 | Micron Technology, Inc. | Event counters for memory operations |
| US11061100B2 (en) | 2019-06-12 | 2021-07-13 | Texas Instruments Incorporated | System for continuous calibration of hall sensors |
| US11867773B2 (en) | 2019-06-18 | 2024-01-09 | Texas Instruments Incorporated | Switched capacitor integrator circuit with reference, offset cancellation and differential to single-ended conversion |
| TWI768976B (zh) * | 2021-06-21 | 2022-06-21 | 瑞昱半導體股份有限公司 | 具有增益調整機制的切換電容放大裝置 |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6137321A (en) * | 1999-01-12 | 2000-10-24 | Qualcomm Incorporated | Linear sampling switch |
| US6362770B1 (en) * | 2000-09-12 | 2002-03-26 | Motorola, Inc. | Dual input switched capacitor gain stage |
-
2003
- 2003-08-20 CA CA2494264A patent/CA2494264C/fr not_active Expired - Lifetime
- 2003-08-20 EP EP03791719A patent/EP1540565B1/fr not_active Expired - Lifetime
- 2003-08-20 JP JP2004532939A patent/JP4454498B2/ja not_active Expired - Lifetime
- 2003-08-20 WO PCT/US2003/026198 patent/WO2004021251A2/fr active Application Filing
Also Published As
| Publication number | Publication date |
|---|---|
| JP2005537749A (ja) | 2005-12-08 |
| EP1540565A2 (fr) | 2005-06-15 |
| WO2004021251A2 (fr) | 2004-03-11 |
| WO2004021251A3 (fr) | 2004-06-17 |
| EP1540565B1 (fr) | 2012-01-18 |
| CA2494264A1 (fr) | 2004-03-11 |
| JP4454498B2 (ja) | 2010-04-21 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request | ||
| MKEX | Expiry |
Effective date: 20230821 |