WO2008065771A1

WO2008065771A1 - Sampling switch and pipeline a/d converter

Info

Publication number: WO2008065771A1
Application number: PCT/JP2007/062529
Authority: WO
Inventors: Koji Oka; Daisuke Nomasaki; Toshiaki Ozeki; Junji Nakatsuka
Original assignee: Panasonic Corporation
Priority date: 2006-11-30
Filing date: 2007-06-21
Publication date: 2008-06-05

Abstract

A boot strap sampling switch has a capacitor C1 for charging a VDD-VSS voltage and a capacitor C3 for charging zero charges during a hold period. During a sampling period, the capacitor C1 and the capacitor C3 are connected in parallel and this parallel circuit is connected between an analog input terminal Vin and the control terminal of an electric control switch (M1) consisting of an MOS transistor. Capacitance ratio between the capacitor C1 and the capacitor C3 is set to such a capacitance ratio that the control voltage of the electric control switch (M1) is reduced to a voltage not exceeding the withstand voltage of a gate oxide film. Consequently, the withstand voltage of the gate oxide film in the electric control switch (M1) can be prevented from being exceeded by simply adding the capacitor C3 without causing an increase in power consumption or in the number of elements, and the electric control switch (M1) can be protected effectively.

Description

Specification

Sampling switch and pipeline AZD converter

Technical field

The present invention relates to an analog / digital converter, a sample / hold circuit, a bootstrap sampling switch and a pipeline AZD converter used for a sampling device.

Background art

Conventionally, as a bootstrap sampling switch, for example, there is one described in Non-Patent Document 1. FIG. 6 shows a sampling switch described in the non-patent document. The conventional bootstrap switch has an electric control switch Ml. The analog input signal Vin is input to the input terminal 11, and the control signal Vg is given to the electrical control switch control terminal 13 to control the electrical control switch Ml to be on or off, and the analog output signal Vout is Output to output terminal 12. This bootstrap switch also includes a capacitor C1, a switch SW2 that connects the first terminal of the capacitor C1 to the low-potential power supply VSS, and a switch SW3 that connects the first terminal of the capacitor C1 and the input terminal 11. A switch SW1 connecting the second terminal of the capacitor C1 and the high-potential power supply VDD, a switch SW4 connecting the second terminal of the capacitor C1 and the control terminal 13 of the electric control switch M1, and an electric control switch. From switch SW5 that connects Ml control terminal 13 and low-potential power supply VSS, and sampling capacitor C2 that is placed between output terminal 12 of electric control switch Ml and low-potential power supply VSS and holds the output analog signal Become. The electric control switch Ml and the sampling capacitor C2 constitute a sampling circuit 15.

[0003] In the semiconductor integrated circuit, the electric control switch Ml is usually formed of an M0S transistor, and the input terminal is a source, the output terminal is a drain, and the control signal is a gate. In the example shown in Fig. 6, the electric control switch Ml is composed of an N-channel MOS transistor, and becomes conductive when the control terminal 13 is high (VDD potential or higher) and non-conductive when the control terminal 13 is low (VSS potential). . The switches SW1 to SW5 are also usually formed by MOS transistors, and their conduction and non-passage are controlled by a control signal. Next, the operation of the conventional bootstrap sampling switch will be described with reference to the timing waveform of FIG. 7 and FIGS. 8 and 9.

In FIG. 7, Vin is an analog signal input to the input terminal 11, CLK1 is a clock signal that controls the switches SW1, SW2, and SW3, CLK2b is a clock signal that controls the switches SW3 and SW4, and Vg is , The control signal of the electric control switch Ml, Vout represents the sampled analog signal output to the output terminal 12. Clock signals CLK1, CLK2b Force When the switch is S high, the switch controlled by this signal is turned on, and when it is low, it is turned off.

FIG. 8 shows conduction and non-conduction states of the switches during the hold period of FIG. 7, and FIG. 9 shows conduction and non-conduction states of the switches during the sample period of FIG.

[0007] In the hold period of FIG. 8, the capacitor C1 is connected between the high-potential power supply VDD and the low-potential power supply VSS, and the charge C1 is stored in the capacitor C1. Since the charge Q stored when the voltage applied to the capacitor C is a predetermined value V is Q = C XV, the charge Q1 stored in the capacitor C1 is Q1 = C1 X (VDD – VSS). At this time, the electrical control switch Ml is in a non-conductive state because its gate is connected to the low potential power supply VSS. For this reason, the voltage immediately before the electric control switch Ml is turned off is held in the capacitor C2.

FIG. 9 shows a state where the hold period has shifted to the next sample period. The capacitor C1 is connected between the input terminal 11 and the electrical control switch control terminal 13, and the switches SW1, SW2, and SW5 are turned off. In FIG. 7, in the transition period from the hold period to the sample period, both the clock signal CLK1 and the clock signal CLK2b are low, and all the switches are non-conductive. Since the Sampnore period starts after this period, the charge Q1 stored in the capacitor C1 is also retained during the Sampnore period. Due to the held charge Q1, the voltage of VDD-VSS is held at both ends of the capacitor C1, and the voltage between the input terminal 11 and the electrical control switch control terminal 13 is related to the voltage of the analog input signal Vin. A constant voltage (VDD— V SS) is applied.

[0009] A bootstrap switch is used in such a circuit configuration, and the voltage (Vg_Vin) between the electric control switch control terminal 13 and the input terminal 11 is a predetermined voltage (VDD-VSS). Because it is constant, the electric control switch Ml formed by the M〇S transistor The voltage between the gate and gate is constant, the on-resistance is almost constant regardless of the input voltage, and a low-distortion sampling switch can be formed. In the case of a normal sampling switch that does not use bootstrap, during the sampling period, the electric control switch control terminal 13 is normally fixed to the high potential power supply VDD, and when the input voltage Vin changes, the voltage (Vg Since -Vin) is not constant, the on-resistance of the switch also changes with the input voltage, which causes distortion in the sampling output.

^^ Patents ffl ^ l: Bootstrapped low-voltage analog switches ^ Jesper Steensgaard, ireu its and Systems ^ 1999, ISCAS '99. Proceedings of the 1999 IEEE International Symp osium on Volume2,30 May-2 June 1999 Page (s ): 29_32 vol.2 (Figure 3)

Disclosure of the invention

Problems to be solved by the invention

[0010] However, in the conventional configuration, when the voltage (Vin + (VDD—VSS)) is applied to the control terminal 13 of the electric control switch Ml during the sampling period, there is a problem with the withstand voltage. was there. When the electrical control switch Ml is a MOS transistor, the control terminal 13 is the gate terminal of the MOS transistor, and a voltage (Vin + (VDD—VSS)) is applied to it. The applied voltage allowed at the gate terminal is determined by the breakdown voltage of the gate oxide film forming the MOS transistor, and is usually set to the operating power supply voltage (VDD-VSS) plus one. If the analog input voltage Vin increases and Vin + (VDD—VSS)> (V DD-VSS) + a, that is, Vin> a, the gate oxide breakdown voltage will be exceeded, causing a problem in reliability.

[0011] In order to solve the above problem, it is conceivable that the voltage applied to the capacitor C1 is made lower than the voltage (VDD—VSS). In this case, however, the voltage is lower than the high potential power supply voltage VDD. It is necessary to make a circuit that generates a voltage higher than the low potential power supply voltage VSS. In addition, since these circuits need to be fully charged within the hold period, it is necessary to lower the output impedance, which leads to an increase in power consumption and an increase in the number of device elements.

[0012] The present invention has been made to solve the above-mentioned problems, and its object is to provide a control signal generation circuit for an electric control switch so as not to exceed the gate oxide film breakdown voltage. In addition, a circuit that adds new power consumption is added while maintaining a substantially constant on-resistance regardless of the input signal level, which is a characteristic of the conventional bootstrap sampling switch. Of course, it is also necessary to generate an electrical control switch control signal Vg with good voltage accuracy that would cause a large increase in the number of device elements.

Means for solving the problem

[0013] The present invention that achieves the above object is configured to generate an electric control switch control signal with high voltage accuracy only by adding a capacity and a switch that do not increase power consumption.

Specifically, the sampling switch of the present invention is a boost strap type sampling switch having a substantially constant on-resistance regardless of the level of the input signal input to the input terminal, and the input signal A sampling circuit having an electrical control switch for propagating the signal, and a sampling capacity for charging the charge of the input signal propagated from the electrical control switch, a first capacitor, and a second capacitor, In the hold period during which the electrical control switch is in a non-conducting state, both ends of the first capacitor are charged with a stored charge corresponding to a voltage difference between a high potential power source and a low potential power source, and the second capacitor The first capacitor and the second capacitor are connected in parallel during a sampling period in which zero charge is charged at both ends of the capacitor and the electrical control switch is turned on. , Connect the voltage at the terminals of one that the parallel connection to said input terminal, characterized in that the voltage of the other terminal and a switch group for the control signal of the electric control switch.

The present invention is characterized in that, in the sampling switch, both ends of the second capacitor are connected to a low potential power source during the hold period.

The present invention is characterized in that, in the sampling switch, both ends of the second capacitor are connected to a high potential power source during the hold period.

The present invention is characterized in that, in the sampling switch, both ends of the second capacitor are connected to the input terminal during the hold period.

The present invention of [0018] is characterized in that, in the sampling switch, a capacitance value of the first capacitor and the second capacitor is formed at a ratio of n: m (n and m are integers). And

In the sampling switch, the present invention provides the first capacitor and the second capacitor. Are each formed using an integer number of unit capacities.

In the sampling switch, the electrical control switch includes a source electrode connected to the input terminal, a drain electrode connected to the sampling capacitor, and a gate electrode to which the control signal is applied. It is composed of transistors.

[0020] The pipeline A / D converter of the present invention is arranged continuously after the sampling switch and the sampling switch, and converts a plurality of output signals of the sampling switch into a multi-bit digital signal. And a digital correction circuit for correcting the digital output value of each of the stages.

As described above, in the present invention, the control voltage of the electrical control switch of the sampling circuit can be set to the breakdown voltage of the gate oxide film only by appropriately setting the capacitance value and the capacitance ratio of the first capacitor and the second capacitor. It can be set not to exceed. Therefore, it is possible to obtain a boost strap type sampling switch that does not increase power consumption or increase the number of device elements.

[0022] In particular, according to the present invention, since the first capacitor C1 and the newly added second capacitor each have an integral number of unit capacitors, a control signal with high voltage accuracy can be generated. The variation in the characteristics of the sampling switch is effectively suppressed.

The invention's effect

[0023] As described above, according to the sampling switch of the present invention, the gate oxide film can be formed without increasing the power consumption and by adding only the capacitance with a large increase in the number of device elements or by adding only this capacitance and the switch. Electric control switch control voltage can be generated without exceeding the breakdown voltage.

[0024] In particular, according to the sampling switch of the present invention, since the first capacitor C1 and the second capacitor to be newly added are each configured with an integer number of unit capacitors, a control signal with high voltage accuracy is provided. This produces an effect of effectively suppressing variation in the characteristics of the sampling switch.

Brief Description of Drawings FIG. 1 is a circuit diagram according to Embodiment 1 of the present invention.

FIG. 2 is a diagram related to Embodiment 1 of the present invention; FIG. 2 is a diagram illustrating a switch state during a hold period.

[Fig. 3] Fig. 3 is a diagram showing a switch state during a sampling period of the sampling switch according to the first embodiment of the present invention.

FIG. 4 shows an embodiment of the present invention.

[FIG. 5] FIG. 5 is a circuit diagram according to Embodiment 3 of the present invention: [FIG. 6]

[Figure 7]

8] Fig. 8 is a diagram showing the state of the switch during the hold period of the conventional sampling switch.

9] Fig. 9 is a diagram showing the state of the switch during the Sampnore period of the conventional sampling switch.

FIG. 10 is related to Embodiment 5 of the present invention; FIG. 10 is a block diagram of the used pipeline A / D converter.

Explanation of symbols

C1 1st capacity

C2 sampling capacity

C3, C4, C5 second capacity

SW0 switch group

SW1 to SW9 switch

Ml Electric control switch

VDD

VSS Low potential power supply

Vin Analog input signal

Vout analog output signal

Vg Electric control switch control signal

11 Input terminal 12 Output terminal

13 Electric control switch control terminal

20 Sampling switch

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0028] (Embodiment 1)

FIG. 1 shows a sampling switch according to Embodiment 1 of the present invention. Compared to the conventional Fig. 6, in addition to the capacitance (first capacitance) C1, a second capacitance C3 is additionally inserted.The number and configuration of the switch group SW0 consisting of five switches SW1 to SW5 is There is no change.

In FIG. 1, the first terminal of the capacitor C3 is connected to the terminal to which the switch SW2 and the switch SW3 are connected, and the second terminal of the capacitor C3 is connected to the control terminal 13 of the electric control switch Ml. Connected. The operation timing at which SW1 to SW5 of this embodiment are turned on and off is the same as that in FIG. 7 of the conventional example. Figure 2 shows the state of each switch during the hold period in Fig. 7. In this hold period, the newly added capacitor C3 has both terminals connected to the low potential power supply VSS by the switch SW2 and the switch SW5. At this time, since both ends of the capacitor C3 are at the same potential, the charge Q3 stored in the capacitor C3 is zero. Since the charge Q1 stored in the capacitor C1 is the same as the conventional example, Q1 = C1 X (VDD—VSS).

[0030] Fig. 3 shows the connection of each switch when the next sample period starts. Capacitor C1 and capacitor C3 are connected in parallel by switch SW3 and switch SW4, and both terminals thereof are connected to input terminal 11 and control terminal (gate terminal of the MOS transistor) 13 of electric control switch Ml. At this time, the voltage Vg applied to the control terminal 13 becomes Vin + (VDD−VSS) × C1 / (C1 + C3). This is because when moving from the hold period to the sample period, the charge Q1 stored in the capacitor C1 is held, and the charge is redistributed to the capacitors C1 and C3 connected in parallel. That is, if the voltage applied to the capacitor C1 and the capacitor C3 connected in parallel during the sample period is V3sa, (VDD—VSS) X Cl = V3sa X (CI + C3) is established according to the law of charge conservation. From this, V3sa = This is because (VDD-VSS) XC 1 / (CI + C3). When C1 / (C1 + C3) = β, the voltage Vg applied to the control terminal 13 is Vin + β X (VDD−VSS) (0 << 1). By selecting the values of capacitance C1 and capacitance C3 as desired, the voltage Vg applied to the control terminal 13 can be kept lower than the voltage (Vin + (VDD—VSS)). This prevents the reliability problem due to the gate oxide breakdown voltage when the switch Ml is formed of MOS transistors. Here, since the force and voltage (Vg_Vin) between the control terminal 13 and the input terminal 11 is β X (VDD−VSS), the bootstrap has a constant on-resistance regardless of the input signal. Keep the characteristics of the switch. β can be freely set by determining the capacitance C1 and the capacitance C3 so as not to exceed the gate oxide breakdown voltage.

As described above, according to the present embodiment, the problem of reliability due to the gate oxide film breakdown voltage can be prevented only by adding the capacitor C3, and an effect of hardly increasing the power consumption can be obtained. It is done.

[0033] (Embodiment 2)

FIG. 4 shows a sampling switch according to Embodiment 2 of the present invention.

In the present embodiment, the capacity (second capacity) C4, the switch SW6, and the switch SW7 are arranged in comparison with the conventional example. The switch SW6 is connected between the first terminal of the capacitor C4 and the high potential power supply VDD, and the switch SW7 is a terminal connecting the first terminal of the capacitor C4, the switch SW2 and the switch SW3. The second terminal of the capacitor C4 is connected to the terminal connected to the switch SW1 and the switch SW4. The switch SW6 operates at the timing of the clock signal CLK1 in Fig. 7, the switch SW7 operates at the timing of the clock signal CLK2b, and during the hold period, the switch SW6 is conductive and the switch SW7 is nonconductive, while the sample period Then, switch SW6 is non-conductive and switch SW7 is conductive. In the hold period, both terminals of the capacitor C4 are connected to the high-potential power supply VDD, and there is no potential difference between the quantity terminals, so that the stored charge is zero as in the first embodiment. In the sample period, the configuration in which the capacitor C1 and the capacitor C4 are connected in parallel and connected between the input terminal 11 and the electric control switch control terminal 13 is the same as in the first embodiment, and the voltage of Vg is Vin + (VDD−VSS) × C1 / (C1 + C4), and the same effect as in the first embodiment can be obtained. There are two more switches than in the first embodiment. It is not a problem.

[0035] (Embodiment 3)

FIG. 5 shows a sampling switch according to Embodiment 3 of the present invention.

In the present embodiment, a capacitor (second capacitor) C5, a switch SW8, and a switch SW9 are added to the conventional example. The switch SW8 is connected between both terminals of the capacitor C5, and the first terminal of the capacitor C5 is connected to the input terminal 11. The switch SW9 is connected to the second terminal of the capacitor C5 and a terminal connecting the switch SW1 and the switch SW4. The switch SW8 operates at the timing of the clock signal CLK1 in FIG. 7, the switch SW9 operates at the timing of the clock signal CLK2b, and during the hold period, the switch SW8 is conductive and the switch SW9 is nonconductive. In the sample period, the switch SW8 is non-conductive and the switch SW9 is conductive. In the hold period, since both terminals of the capacitor C5 are connected to the input terminal and there is no potential difference, the charge stored in the capacitor C5 is zero as in the first embodiment. In the sample period, the capacitor C1 and the capacitor C5 are connected in parallel, and both terminals thereof are connected between the input terminal 11 and the electric control switch control terminal 13 in the same manner as in the first embodiment. The voltage of Vg is Vin + (VDD−VSS) × CI / (CI + C5), and the same effect as in the first embodiment is obtained. In this embodiment, there are two more switches than in the first embodiment, but this is not a big problem in terms of the overall circuit scale.

[0037] (Embodiment 4)

Next, a fourth embodiment of the present invention will be described.

[0038] In the first embodiment, the capacity C1 and the capacity C3 are each an integral multiple of the unit capacity CO, and C l = n X C0 and C3 = m X C0 (n and m are both integers) are controlled. The voltage Vg applied to pin 13 is Vin + (VDD -VSS) X nZ (n + m). In a semiconductor integrated circuit, when forming a capacitor, it is possible to increase the accuracy of the capacitor by arranging unit capacitors regularly. For example, when the unit capacitance CO is 0.5 pF and n = m = 1, the variation accuracy of nZ (n + m) is 1% or less. If the accuracy of this capacitance ratio is 1% or less, the control voltage variation of the electric control switch Ml can be suppressed to 1% or less, and the on-resistance variation in manufacturing of the electric control switch Ml is almost 1%. The following can be kept small. As a result, as a sampling switch, characteristic variation due to on-resistance variation, In addition, variations in distortion characteristics can be reduced, and a sampling switch with good characteristics can be provided.

In the above description, the electric control switch Ml is composed of an n-channel MOS transistor, but it goes without saying that the same effect can be obtained by using a p-channel MOS transistor. In addition, a detailed description of the configuration of switches SW1 to SW9 is omitted. Usually, MOS switches are used.

[0040] (Embodiment 5)

FIG. 10 shows a fourth embodiment of the present invention. This embodiment shows the application of the sampling switch described above.

[0041] This figure shows a pipeline A / D converter. The first stage is a sample-no-hold circuit 20 composed of the sampling switches described above, and a plurality of consecutively arranged downstream stages. A plurality of stages 211 to 21n comprising the above arithmetic circuits. The plurality of stages 211 to 21n convert the output signal of the sampling switch, that is, the charge amount of the sampling capacitor C2 shown in FIG. 1, into a predetermined multi-bit digital signal. These digital signals are input to the digital correction circuit 22 and corrected, and the corrected output becomes a multi-bit digital output value from the pipeline A / D converter.

Industrial applicability

[0042] As described above, the sampling switch of the present invention has the bootstrap circuit that effectively reduces the control voltage of the MOS transistor that constitutes the switch. It is useful as a hold circuit, etc., and can also be applied to pipeline / analog / digital conversion circuit applications.

Claims

The scope of the claims

[1] A boost strap type sampling switch having a substantially constant on-resistance regardless of the level of the input signal input to the input terminal,

A sampling circuit having an electrical control switch for propagating the input signal, and a sampling capacitor for charging the charge of the input signal propagated from the electrical control switch;

The first capacity,

A second capacity,

In the hold period in which the electrical control switch is turned off, the accumulated charge corresponding to the differential voltage between the high potential power source and the low potential power source is charged at both ends of the first capacitor, and the second capacitor The first capacitor and the second capacitor are connected in parallel during a sampling period in which zero charge is charged at both ends and the electrical control switch is in a conductive state, and the voltage of the one terminal connected in parallel is connected. Connected to the input terminal, and a switch group using the voltage of the other terminal as a control signal of the electric control switch.

[2] In the sampling switch according to claim 1,

In the hold period, the both ends of the second capacitor are connected to a low potential power source.

[3] The sampling switch according to claim 1,

In the hold period, the both ends of the second capacitor are connected to a high potential power supply.

[4] The sampling switch according to claim 1,

In the hold period, the both ends of the second capacitor are connected to the input terminal.

[5] The sampling switch according to claim 1,

The capacitance value of the first capacitor and the second capacitor is formed in a ratio of n: m (n and m are integers).

[6] The sampling switch according to claim 5,

The first capacitor and the second capacitor are each formed using an integer number of unit capacitors.

A sampling switch characterized by

[7] The sampling switch according to claim 1,

The electric control switch is

The MOS transistor includes a source electrode connected to the input terminal, a drain electrode connected to the sampling capacitor, and a gate electrode to which the control signal is applied.

A sampling switch characterized by that.

[8] The force according to any one of claims 1 to 7, and the sampling switch according to claim 1,

A plurality of stages comprising a plurality of arithmetic circuits arranged continuously after the sampling switch and converting the output signal of the sampling switch into a digital signal of a plurality of bits;

A pipeline A / D converter comprising: a digital correction circuit that corrects a digital output value of each stage.