WO2008053510A1 - Procédé pour faire fonctionner un panneau d'affichage plasma et dispositif d'affichage plasma - Google Patents

Procédé pour faire fonctionner un panneau d'affichage plasma et dispositif d'affichage plasma Download PDF

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Publication number
WO2008053510A1
WO2008053510A1 PCT/JP2006/321560 JP2006321560W WO2008053510A1 WO 2008053510 A1 WO2008053510 A1 WO 2008053510A1 JP 2006321560 W JP2006321560 W JP 2006321560W WO 2008053510 A1 WO2008053510 A1 WO 2008053510A1
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WIPO (PCT)
Prior art keywords
subfield
unnecessary
sustain
discharge
display
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PCT/JP2006/321560
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English (en)
Japanese (ja)
Inventor
Takashi Sasaki
Yukio Akiyama
Original Assignee
Hitachi, Ltd.
Hitachi Plasma Display Limited
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Publication date
Application filed by Hitachi, Ltd., Hitachi Plasma Display Limited filed Critical Hitachi, Ltd.
Priority to PCT/JP2006/321560 priority Critical patent/WO2008053510A1/fr
Publication of WO2008053510A1 publication Critical patent/WO2008053510A1/fr

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
    • G09G3/291—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes
    • G09G3/294—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes for lighting or sustain discharge
    • G09G3/2944—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes for lighting or sustain discharge by varying the frequency of sustain pulses or the number of sustain pulses proportionally in each subfield of the whole frame
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
    • G09G3/296—Driving circuits for producing the waveforms applied to the driving electrodes
    • G09G3/2965—Driving circuits for producing the waveforms applied to the driving electrodes using inductors for energy recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/066—Waveforms comprising a gently increasing or decreasing portion, e.g. ramp
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/16—Calculation or use of calculated indices related to luminance levels in display data

Definitions

  • the present invention relates to a plasma display panel driving method and a plasma display device.
  • the present invention relates to a plasma display panel and a plasma display device.
  • a plasma display panel is formed by bonding two glass substrates together, and displays an image by generating discharge light in a space formed between the glass substrates.
  • the discharge cells corresponding to the pixels in the image are self-luminous, and are coated with phosphors that generate red, green, and blue visible light in response to ultraviolet rays generated by the discharge.
  • a field for displaying one screen is composed of a plurality of subfields.
  • the number of subfield discharges is sequentially set to 2 to the nth power (n is a positive integer).
  • n is a positive integer.
  • a multi-tone image is displayed by selectively lighting the discharge cells in accordance with the luminance of the image. For example, in a high luminance image (high gradation image), a subfield with a large number of discharges is selected, but in a low luminance image (low gradation image), a subfield with a large number of discharges is not selected. Subfields that are not selected are not lit because the discharge cells are not selected.
  • the display rate is a ratio of the luminance of the actually displayed image to the luminance of the screen when all the pixels of the screen are lit at the maximum luminance.
  • the display rate is 100% when all pixels are lit at the maximum brightness, and the display rate is 10% when all pixels are lit at 1/10 the maximum brightness.
  • Patent Document 1 Japanese Patent Laid-Open No. 2005-234231
  • Patent Document 2 JP-A-9-68945
  • the object of the present invention is to adjust the number of sustain discharges in each field according to the display rate of the PDP, thereby adjusting the number of sustain discharges in each sub-field for each display line. To improve the image quality.
  • one field for displaying one screen of the plasma display panel is composed of a plurality of subfields.
  • the image is displayed in multiple gradations.
  • the display line is composed of pixels formed along the first electrode.
  • the load detection circuit detects a display rate that is a ratio of the luminance of the actual image to the maximum luminance of the plasma display panel.
  • the load control circuit sets the number of subfield sustain discharges to a predetermined first number when the display rate is less than or equal to a preset threshold value.
  • the load control circuit reduces the number of sustain discharges in the subfield less than the first number in order to reduce the luminance value of the image displayed on the plasma display panel when the display rate is larger than the threshold value. Set to 2 times each.
  • the grayscale detection circuit does not stop the sustain discharge generated in at least one of the subfields for each display line, but instead stops at least another subfield. Assume that one sustain discharge is generated. Then, based on the above assumption, the gradation detection circuit detects whether or not the subfield in which the sustain discharge is stopped can be made an unnecessary subfield that does not require the sustain discharge.
  • the sustain control circuit includes the first and second sub-fields in order to generate a second number of sustain discharges in each sub-field in the display line when there is no unnecessary sub-field. Controls the operation of the second drive circuit.
  • the sustain control circuit also includes the first and second sub-fields in order to generate a sustain discharge that is less than the minimum number of the second number of times in at least one of the sub-fields in the display line where the unnecessary subfield exists. Control the operation of the drive circuit.
  • the number of sustain discharges in a field is adjusted according to the display rate of the PDP, an image with low luminance is adjusted by adjusting the number of sustain discharges in each subfield for each display line.
  • the number of gradations can be increased, and the image quality can be improved.
  • FIG. 1 is an exploded perspective view showing a first embodiment of the present invention.
  • FIG. 2 is an exploded perspective view showing details of a main part of the PDP shown in FIG.
  • FIG. 3 is an explanatory diagram showing a configuration example of a field for displaying an image of one screen.
  • FIG. 4 is a characteristic diagram showing an example of the relationship between the gradation of the input image and the display gradation (number of discharge cycles) of the image displayed on the PDP in the number of discharge cycles shown in FIG.
  • FIG. 5 is a waveform diagram showing an example of discharge operation in the subfield shown in FIG.
  • FIG. 6 is a block diagram showing an outline of the circuit unit shown in FIG. 1.
  • FIG. 7 is a flowchart showing the operation of the control unit shown in FIG.
  • FIG. 8 is a circuit diagram showing details of the Y driver and the X driver shown in FIG. 6.
  • FIG. 9 is a timing chart showing details of operations in the address period and the sustain period shown in FIG. 3.
  • FIG. 10 is an explanatory diagram showing the number of discharge cycles when there is an unnecessary subfield.
  • FIG. 11 In the methods (1), (2), and (3) shown in FIG. 10, the relationship between the input gradation of the image data and the display gradation (number of discharge cycles) of the image displayed on the PDP It is a characteristic view which shows an example
  • FIG. 12 Characteristic showing an example of the relationship between the input gray level of image data and the display gray level (number of discharge cycles) of the image displayed on the PDP in the methods (4) and (5) shown in Fig. 10 FIG.
  • FIG. 13 In the methods (1), (2), (3) and Comparative Example 1 shown in FIG. 10, the input gradation and display gradation (number of discharge cycles) when quantizing the image data are Characteristics showing an example of a relationship FIG.
  • FIG. 14 is a characteristic diagram showing an example of the relationship between the input gradation and the display gradation (number of discharge cycles) when quantizing the image data in the method (4) and comparative example 2 shown in FIG. is there.
  • FIG. 15 is a characteristic diagram showing an example of a relationship between an input gradation and a display gradation (number of discharge cycles) when image data is quantized in the method (5) shown in FIG.
  • FIG. 16 is a circuit diagram showing details of a Y driver and an X driver in the second embodiment of the present invention.
  • FIG. 17 is a timing chart showing details of operations in the address period and the sustain period shown in FIG. 3 in the second embodiment of the present invention.
  • FIG. 18 is a characteristic diagram showing an example of the relationship between the input gradation of 12-bit image data and the display gradation (number of discharge cycles) of the image displayed on the PDP.
  • FIG. 1 shows a first embodiment of the present invention.
  • a plasma display device (hereinafter also referred to as a PDP device) is a plasma display panel 10 having a square plate shape (hereinafter also referred to as a PDP), and an optical filter provided on the image display surface 12 side (light output side) of the PDP10.
  • PDP10 image display surface 12 is mounted on the front housing 30 side
  • PDP10 rear panel 40 is mounted on the back side 14 and base chassis 50
  • base chassis 50 is mounted on the rear housing 40 side
  • PDP10 Circuit unit 60 for driving the PDP 10 and a double-sided adhesive sheet 70 for attaching the PDP 10 to the base chassis 50. Since the circuit part 60 is composed of a plurality of parts, it is indicated by a dashed box in the figure.
  • the PDP 10 includes a front substrate 16 (first substrate) that constitutes the image display surface 12 and a rear substrate 18 (second substrate) that faces the front substrate 16.
  • a discharge space (discharge cell) (not shown) is formed between the front substrate 16 and the rear substrate 18.
  • the front substrate 16 and the back substrate 18 are formed of, for example, a glass substrate.
  • the optical filter 20 is attached to a protective glass (not shown) attached to the opening 32 of the front housing 30.
  • FIG. 2 shows details of a main part of the PDP 10 shown in FIG.
  • the front substrate 16 is parallel and alternate with each other on the glass substrate 16a (lower side in the figure) in order to repeatedly generate a discharge.
  • X electrode 16b first electrode, sustain electrode
  • Y electrode 16c second electrode, stray electrode
  • the X electrode 16b and the Y electrode 16c are composed of a bus electrode BE (electrode line) extending in the horizontal direction in the figure and a transparent electrode TE connected to the bus electrode BE.
  • the electrodes 16b and 16c are covered with a dielectric layer 16d, and the surface of the dielectric layer 16d is covered with a protective layer 16e such as MgO.
  • the rear substrate 18 facing the front substrate 16 via the discharge space DS has address electrodes 18b (third electrodes) formed in parallel to each other on the glass base material 18a.
  • the address electrode 18b is arranged in a direction orthogonal to the bus electrode BE.
  • the address electrode 18b is covered with a dielectric layer 18c.
  • partition walls (ribs) 18d are formed at positions corresponding to between the adjacent address electrodes 18b.
  • the side wall of the discharge cell is constituted by the barrier rib 18d.
  • visible light of red (R), green (G), and blue (B) is emitted on the side surface of the partition wall 18d and on the dielectric layer 18c between the partition walls 18d adjacent to each other by being excited by ultraviolet rays.
  • the resulting phosphors 18e, 18f, and 18g are applied respectively.
  • One discharge cell (one color pixel) of the PDP 10 is formed in a region including a pair of transparent electrodes TE in a region surrounded by a pair of adjacent barrier ribs 18d. That is, the discharge cell is formed at the intersection of the electrodes 16b and 16c and the electrode 18b.
  • the PDP 10 is configured by disposing discharge cells in a matrix in order to display an image, and alternately arranging a plurality of types of discharge cells that generate light of different colors.
  • one pixel PX shown in FIG. 6 to be described later includes three discharge cells that generate red, blue, and green light.
  • a display line is constituted by discharge cells formed along the electrodes 16b and 16c.
  • the PDP 10 is configured by bonding the front substrate 16 and the rear substrate 18 so that the protective layer 16e and the partition wall 18d are in contact with each other and enclosing a discharge gas such as Ne or Xe.
  • the bus electrode BE is connected to the X driver XDRV and the Y driver YDRV shown in FIG.
  • the address electrode 18b is connected to the address driver ADRV shown in FIG.
  • FIG. 3 shows a configuration example of the field FLD for displaying an image of one screen.
  • One Fino Red FLD has a length of 1Z60 seconds (about 16.7 ms), and is composed of, for example, 8 subfields SF (SF1-SF8).
  • Each subfield SF has a reset period RST, key.
  • Dress period ADR sustain period SUS
  • erase period ERS is defined as being included in the sustaining period SUS because it is a period for generating a discharge for erasing the wall charges of only the lit discharge cells.
  • the wall charge is, for example, a brass charge and a negative charge accumulated on the MgO layer 16e shown in FIG. 2 in each discharge cell, and erasing includes the meaning of reducing the wall charge. .
  • the sustain period SUS length varies depending on the subfield SF and depends on the number of discharges (luminance) of the discharge cell. For this reason, it is possible to display an image in multiple gradations by changing the combination of the subfields SF to be lit.
  • the number of times N1 is a subfield when there is no unnecessary subfield, which will be described later, and the display rate is equal to or less than a preset threshold value (for example, a display rate of 15%).
  • the number N1 of sustain discharges in subfield SF1-8 is 4, 8, 16, 32, 64, 128, 256, and 512, respectively.
  • the display rate is a ratio of the luminance of the actually displayed image to the luminance of the screen when all the pixels of the screen are lit at the maximum luminance.
  • the number of times N2 is the number of discharge cycles set in the subfield SF1-8 when the unnecessary subfield does not exist !, the display line! An example of the number of times) is shown.
  • the number of times N2 is calculated based on the display rate and is less than the number of times N1.
  • the display rate is 50%, for example, the number of sustain discharges N2 of subfield SF1-8 is set to 24, 8, 16, 32, 64, 128, and 256, respectively.
  • FIG. 4 shows an example of the relationship between the gradation of the input image and the display gradation (number of discharge cycles) of the image displayed on the PDP 10 in the number of discharge cycles shown in FIG. Figure 4 shows the relationship between the input gray level and the display gray level when the display rate is below the threshold and the display rate is higher than the threshold when the input gray level is expressed in 1024 brightness levels (1024 gray levels).
  • the thick solid line in the figure shows the case where the display rate is below the threshold value, that is, the number of discharge cycles set in the subfield SF is N1.
  • a thick broken line indicates a case where the display rate is larger than the threshold value, that is, a case where the number of discharge cycles set in the subfield SF is the number N2.
  • the display gradation discharge cycle
  • the number of display cycles (number of discharge cycles) when the display rate is larger than the threshold is 256.
  • the display rate is larger than the threshold value, the brightness value of the image displayed on the PDP 10 decreases, and the power consumption can be suppressed.
  • the upper subfields SF8 and SF7 are used in a high luminance (high gradation) image, and the upper subfields SF8 and SF7 are not used in a low luminance (low gradation) image.
  • the number of discharge cycles indicates the number of sustain pulses applied to the X electrode 16b (or Y electrode 16c). As shown in Fig. 5 below, the discharge cell discharges twice during one discharge cycle CYC (star in the figure).
  • FIG. 5 shows an example of the discharge operation of subfield SF shown in FIG.
  • the star in the figure indicates the occurrence of discharge.
  • a negative write voltage is applied to the sustain electrode X (X electrode 16b), and a slowly rising positive write voltage (write blunt wave) is applied to the scan electrode Y (Y electrode 16c).
  • a positive adjustment voltage is applied to the sustain electrode X, and a negative adjustment voltage (adjusted blunt wave) is applied to the scan electrode (FIG. 5 (b)).
  • the positive adjustment voltage is a voltage lower than the voltage VsZ2
  • the negative adjustment voltage is a voltage higher than the voltage VsZ2.
  • a positive scan voltage is applied to the sustain electrode X
  • a negative scan pulse is applied to the scan electrode Y
  • a positive address pulse (voltage Vsa) is applied to the address corresponding to the discharge cell that is lit.
  • Applied to the electrode Al (18b) (Fig. 5 (c, d)).
  • the discharge cell selected by the address pulse is temporarily discharged.
  • the address pulses shown in the waveform of the address electrode A1 are sequentially applied to sequentially select the discharge cells on the display line. In the present invention, the discharge in the address period ADR is not included in the discharge cycle.
  • a negative pre-erase pulse and a positive high-voltage pre-erase pulse force X are applied to the sustain electrode X and the scan electrode Y, respectively, and a discharge is generated (FIG. 5 (g)).
  • wall charges are accumulated in the sustain electrode X and the scan electrode Y.
  • positive erase pulse and negative erase pulse force are applied to sustain electrode X and scan electrode Y, respectively (Fig. 5 (h)). As a result, discharge occurs and the amount of wall charges is reduced.
  • a negative voltage (blunt wave) that gradually falls is applied to the sustain electrode X and applied to the positive pulse force scanning electrode Y (Fig. 5 (i )).
  • the discharge in the erase period ERS is not included in the discharge cycle. This completes the SF for one subfield period.
  • the number of discharge cycles is “3” (six discharges in the sustain period SUS), which is the same as the number of pulses of the scan electrode Y.
  • the Y driver YDRV and the X driver XDRV shown in FIGS. 8 and 16, which will be described later, have predetermined voltages (eg, positive adjustment voltage, negative The description of the circuit for applying the adjustment voltage to the sustain electrode X and the scan electrode Y is omitted.
  • FIG. 6 shows an outline of the circuit unit 60 shown in FIG.
  • the circuit unit 60 includes an X driver XDRV (first drive circuit) that applies a common pulse to the X electrode 16b, a Y driver YDRV (second drive circuit) that selectively applies a pulse to the Y electrode 16c, and an address electrode. It has an address driver ADRV (third drive circuit) that selectively applies pulses to 18b, a control unit CNT that controls the operation of the drivers XDRV, YDRV, and AD RV, and a power supply unit PWR.
  • Drivers XDRV, YDRV, and ADRV operate as a drive unit that drives the PDP 10.
  • the control unit CNT includes a gradation detection circuit 62, a sustain control circuit 64, a load detection circuit 66, and a load control circuit 68.
  • Image data RO-9, GO-9, and BO-9 are 10-bit data for displaying red, green, and blue, respectively. Alternatively, it is sequentially input from the external input to the load detection circuit 66.
  • 1024 brightness (1024 gradations) force image data are expressed according to the bit values of RO-9, GO-9, and BO-9.
  • a bit with a small number has a high weight for a bit with a small weight (high order bit).
  • the load detection circuit 66 detects the display rate of the PDP 10 based on the image data RO-9, GO-9, and BO-9.
  • the display rate is the size of one screen indicated by image data RO-9, GO-9, BO-9 for the maximum luminance value of the screen when all pixels of PDP10 are lit at the maximum luminance. It is a ratio of the luminance value.
  • the display rate is 100% when the luminance values indicated by the image data RO-9, GO-9, and BO-9 of all the pixels are the maximum luminance value.
  • half of the image data R0-9, GO-9, B0-9 show the maximum luminance value
  • the other half of the pixel image data R0-9, GO-9, B0-9 show off.
  • the display rate is 50%.
  • the load detection circuit 66 outputs the data RATE indicating the display rate of the PDP 10 to the gradation detection circuit 62, the sustain control circuit 64, and the load control circuit 68.
  • the load control circuit 68 sets the number of sustain discharges of the subfield SF to the number N1 (for example, in FIG. 3 described above, when the display rate is equal to or less than a preset threshold value (for example, display rate 15%). Set to the number of sustain discharges N1) shown. Further, when the display rate is larger than the threshold value, the load control circuit 68 sets the number of sustain discharges of the subfield SF to a number N2 smaller than the number N1 (for example, the number of sustain discharges shown in FIG. 3 described above). Set each to the number N2).
  • a preset threshold value for example, display rate 15%
  • the load control circuit 68 controls the number of sustain discharges in order to keep the power consumption below the preset maximum value even when the display rate is larger than the threshold value.
  • the load control circuit 68 outputs control data PCNT indicating the number of sustain discharges of each subfield SF set based on the display rate to the gradation detection circuit 62 and the sustain control circuit 64.
  • the gradation detection circuit 62 is based on the display rate, the image data RO-9, GO-9, BO-9, and the number of sustain discharges of each subfield SF set by the load control circuit 68.
  • the subfield SF used for image display is obtained for each pixel.
  • the subfield SF to be lit for each pixel PX is obtained by calculation. This calculation also detects the luminance distribution of the pixels that are lit on each display line.
  • the display line is composed of the pixels PX arranged along the electrodes 16b and 16c.
  • one image PX is composed of three discharge cells that generate red, blue, and green light.
  • Each pixel PX may be composed of three or more discharge cells.
  • a display line including a high-luminance image is a display line having pixels that display an image by turning on the subfield SF8 (or SF7-8).
  • subfield SF8 (or SF7-8) is an unnecessary subfield in which sustain discharge (lighting) does not occur during the sustain period SUS.
  • the gradation detection circuit 62 may provide an unnecessary subfield that does not require a sustain discharge for each display line based on the luminance distribution of the pixels! Detects whether or not it is possible.
  • the gradation detection circuit 62 detects whether or not the subfield SF7 becomes an unnecessary subfield by generating a sustain discharge in the subfield SF8 instead of stopping the sustain discharge generated in the subfield SF7. To do. Further, the subfield SF8 is detected as an unnecessary subfield in a display line of a high brightness image in which the subfield SF8 is not used.
  • the gradation detection circuit 62 detects whether or not an unnecessary subfield exists for each display line. Then, the gradation detection circuit 62 outputs data SCNT including the presence / absence of unnecessary subfields and information indicating the subfield SF to be lit to the sustain control circuit 64 for each display line.
  • the sustain control circuit 64 provides a control signal to the drivers YDRV and XDRV in order to generate the sustain discharge for the number of times set by the load control circuit 68 in each subfield SF1-8 on the display line where there is no unnecessary subfield. Outputs YCNT and XCNT, and outputs control signal ACNT to driver ADRV. At this time, the sustain control circuit 64 outputs control signals YCNT and XCNT to display an image of 256 gradations corresponding to the upper 8-bit image data R2-9, G2-9, and B2-9.
  • control signal YCNT is a switch control signal SW1, SW2, S shown in FIG. 9 described later. Includes W3, SW4, SW5n, SW5m, SW6n, SW6m.
  • the control signal XCNT includes switch control signals SW7, SW8, SW9, and SW10 shown in FIG. 9 described later.
  • the control signal ACNT is a timing signal for generating an address pulse.
  • the sustain control circuit 64 causes the control signals YCNT, XCNT to be sent to the drivers YDRV, XDRV in order to generate sustain discharges less than the minimum number set by the load control circuit 68 on the display line where the unnecessary subfield exists.
  • the control signal ACNT is output to the driver ADRV.
  • the sustain control circuit 64 separates the low luminance corresponding to the image data R1-7, G1-7, B1-7 and the high luminance corresponding to the image data R8-9, G8-9, B8-9.
  • the lower bits Rl, Gl, and B1 or RO-l, GO-l, and BO- 1 instead of the upper bits, the number of gradations of the dark image can be increased and the image quality can be improved.
  • the power supply unit PWR generates power supply voltages Vsc, Vs / 2, one VsZ2, and Vsa to be supplied to the drivers YDRV, XDRV, and ADRV.
  • Y driver YDRV has a scan driver circuit SD for each Y electrode 16c. As a result, a desired number of sustain pulses can be selectively applied to each Y electrode 16c.
  • FIG. 7 shows the operation of the control unit CNT shown in FIG. In FIG. 7, only the control related to the sustain period SUS is shown, and the control related to the address period ADR is not shown.
  • the flow shown in Fig. 7 may be realized by controlling a hard wafer by software, which may be realized only by hardware.
  • step S10 the load detection circuit 66 receives image data RO-9, GO-9, BO-9 for one screen.
  • the control unit CNT shown in FIG. And continuously receiving image data of a plurality of screens. For this reason, the control unit CNT performs the flow of FIG. 7 every time it receives image data for one screen of display lines.
  • the processing of steps S16, S18, S20, S22, S26, S28, S30, and S32 is performed for each display line.
  • step S12 the load detection circuit 66 detects the display rate of the received image based on the image data for one screen.
  • step S14 the load control circuit 68 determines whether or not the display rate is equal to or less than the threshold based on the information (display rate) from the load detection circuit 66. If the display rate is less than or equal to the threshold, the process moves to step S26.
  • step S16 the load control circuit 68 sets the number of discharge cycles in the subfield SF1-8 to the number N2 that is less than the number N1, based on the display rate.
  • step S18 the gradation detection circuit 62 determines the subfield SF that is lit to display an image based on the image data of one display line, the display rate, and the number of discharge cycles set in step S16. Obtained for each pixel PX. As described above, the upper subfields SF8 and SF7 are used in the pixel PX that displays a high gradation image.
  • the subfield SF7 is not used.
  • a high brightness image can be displayed. That is, the gradation detection circuit 62 detects whether or not there is an unnecessary subfield SF that does not require a sustain discharge for each display line.
  • the unnecessary subfield SF is a subfield in which the sustain discharge is detected to be unnecessary in all the discharge cells (red, blue, and green) of one pixel PX.
  • step S20 the sustain control circuit 64 determines based on the information from the gradation detection circuit 62 whether or not there is an unnecessary subfield that is not lit to display an image. . If there is no unnecessary subfield, the process proceeds to step S40, and if there is an unnecessary subfield, the process proceeds to step S22.
  • step S22 the sustain control circuit 64 applies at least one of the subfields SF1-8 including the unnecessary subfield SF1-8 for the number of times N2 set in step S16. Assign to subfields that generate a number of sustain discharges less than the minimum number of discharges. For example, the minimum number of times N2 shown in FIG. 3 described above is two discharge cycles of the lowest subfield SF1. In step S22, the smallest number of discharge cycles is set to one discharge cycle. The operation of step S22 is, for example, setting of the number of discharge cycles for displaying a display line L1-4 in FIG.
  • step S26 the load control circuit 68 sets a predetermined number of discharge cycles (number of times N1) in subfield SF1-8. Then, in step S28, the gradation detection circuit 62 obtains a subfield SF that is lit to display an image for each pixel PX, as in step S18.
  • This calculation detects whether there is an unnecessary subfield that does not require sustain discharge while maintaining the number of discharge cycles (number of times N1) set in subfield SF for each display line. Is done.
  • step S30 the sustain control circuit 64 determines whether or not an unnecessary subfield exists based on information from the gradation detection circuit 62. If the unnecessary subfield does not exist, the process proceeds to step S40. If the unnecessary subfield exists, the process proceeds to step S32.
  • step S32 the sustain control circuit 64 sets at least one of the subfields SF1-8 including the unnecessary subfield to a number less than the minimum number of sustain discharges of the number N1 set in step S26. Assign to the subfield that generates sustain discharge.
  • step S40 the sustain control circuit 64 uses the subfield SF1-8 to perform the number of sustain discharges set in step S16, S22, S26, or S32, so that the drivers XDRV and YDRV Control the behavior.
  • FIG. 8 shows details of the Y driver YDRV and the X driver XDRV shown in FIG.
  • the Y driver YDRV has a driver circuit DRV (Y) and a scan driver circuit SD.
  • the X driver XDRV has a driver circuit DRV (X).
  • the switches S Wl, SW2, SW3, SW4, SW6 (SW6n, SW6m), SW7, SW8, SW9, SWIO shown in the figure are For example, it is composed of an nMOS transistor (MOSFET). Each nMOS transistor has a parasitic diode that connects between the source and the drain, as shown in the figure. Further, the switch SW5 (SW5n, SW5m) is configured by, for example, an IGBT (Insulated Gate Bipolar Transistor).
  • IGBT Insulated Gate Bipolar Transistor
  • the driver circuit DRV (Y) includes a coin La, switches SW1, SW2, SW3, SW4 and a diode.
  • Coil La and switch SW1–4 operate as a resonance circuit to generate a resonance pulse on the Y electrode (Yn, Ym, etc.).
  • the resonant pulse is a signal common to all Y electrodes.
  • Switches SW1–4 are turned on when a high logic level switch control signal is received, and turned off when a low logic level switch control signal is received.
  • the drain of the switch SW1 and the source of the switch SW3 are connected to the ground line G1.
  • the source of the switch SW1 is connected to the node ND1, which is one end of the coil La, via a forward-connected diode.
  • the drain of switch SW3 is connected to node ND1 through a diode connected in the reverse direction.
  • the node ND1 is connected to the power supply Vs / 2 and one Vs / 2 through diodes connected in the reverse direction.
  • the drain is connected to the power source VsZ2, and the source is connected to the node ND2, which is the other end of the coil La.
  • Switch SW4 has its source connected to the power supply—Vs / 2 and its drain connected to node ND2.
  • Node ND2 is connected to each scan driver circuit SD
  • Each scan driver circuit SD has a switch SW5 (SW5n, SW5m, etc.) and a switch SW6 (SW6n, SW6m, etc.) arranged in series between the power supply Vsc and the node ND2.
  • the switch SW5 the drain is connected to the power supply Vsc via a diode connected in the forward direction, and the source is connected to the Y electrode (Yn, Ym, etc.).
  • the drain of the switch SW5 is connected to the node ND2 via the capacitor C1.
  • Switch SW6 has its source connected to node ND2 and its drain connected to the Y electrode.
  • the driver circuit DRV (X) of the X driver XDRV has the same circuit configuration as the driver circuit DRV (Y). That is, the driver circuit DRV (X) has a coil Lb, switches SW7, SW8, SW9, SW10 and a diode.
  • the coil Lb and switch SW7-10 operate as a resonance circuit for generating a resonance pulse on the X electrode (Xn, Xm, etc.).
  • Switch SW7-10 turns on when a high logic level switch control signal is received, and turns off when a low logic level switch control signal is received.
  • Capacitor Cp indicates the capacitance of PDP10.
  • FIG. 9 shows details of operations in the address period ADR and the sustain period SUS shown in FIG.
  • a signal for controlling on / off of the switch SW1-10 is referred to as a switch control signal SW1-10.
  • the switch SW1-10 is turned on during the high logic level of the switch control signal SW1-10, and is turned off during the low logic level of the switch control signal SW1-10.
  • the star in the figure indicates the occurrence of discharge.
  • the switches SW4 and SW8 are always turned on (Fig. 9 (a, b)). For this reason, the node ND2 shown in FIG. 8 is set to a voltage of 1 Vs / 2.
  • the X electrodes Xn and Xm are set to the voltage VsZ2 (Fig. 9 (c, d)).
  • the switches SW5n and SW5m are turned on and the switches SW6n and SW6m are turned off during the period in which the pixel PX selection operation is not performed (FIG. 9 (e)).
  • the Y electrodes Yn and Ym are set to the voltage Vsc (Fig. 9 (f, g)).
  • the corresponding switch SW5n (or SW5m) is turned off and the corresponding switch SW6n (or SW6m) is turned on in synchronization with the driving of the address electrode A1.
  • the Y electrode Yn (or Ym) is temporarily set to the voltage—VsZ2 (FIG. 9 (h, i)). Then, the scanning operation force for selecting the pixel PX to be lit is performed for each display line.
  • the voltages of the X electrodes Xn and Xm are initialized to the same voltage Vs / 2 by turning on the switch SW10 (Fig. 9 (j, k) ).
  • the voltages of the Y electrodes Yn and Ym are initialized to 1 VsZ 2 by turning on the switches SW6n and SW6m (Fig. 9 (1, m)).
  • the switches SW5n and SW5m are always turned off during the sustain period SUS.
  • ground line G1 is connected to capacitor Cp via switch SW1, coil La, switch SW6n, SW6m, and Y electrodes Yn, Ym.
  • the voltage of the Y electrodes Yn and Ym rises due to the LC resonance effect of the coil La and the capacitor Cp.
  • the switch SW2 is turned on, the voltage of the Y electrodes Yn and ⁇ m is clamped to the voltage VsZ2 (FIG. 9 (n, o)).
  • the switch SW3 when the switch SW3 is turned on, the capacitor Cp is connected to the ground line G1 via the Y electrodes Yn and Ym, the switches SW6n and SW6m, the coil La, and the switch SW3.
  • the voltage of the Y electrodes Yn and Ym drops due to the LC resonance effect of the coil La and the capacitor Cp.
  • the switch SW4 when the switch SW4 is turned on, the voltages of the Y electrodes Yn and Ym are clamped to the voltage VsZ2 (FIG. 9 (p, q)).
  • the sustain pulses are applied to the Y electrodes Yn and Ym by sequentially turning on the switches SW1-4.
  • the sustain pulses of the X electrodes Xn and Xm are generated by sequentially turning on the switches SW7-10.
  • the sustain pulse (discharge cycle) of at least one of the subfields SF1-8 is detected.
  • the number is set to be smaller than the display line (for example, Yn), which has unnecessary subfields.
  • the discharge inhibition period DIS for inhibiting discharge is set during the sustain period SUS.
  • the discharge inhibition period DIS is generated by clamping the Y electrode Ym to the voltage VsZ2 and then turning off the switch SW6m (Fig. 9 (r)).
  • the Y electrode Ym When the switch SW6m is turned off, the Y electrode Ym enters a high impedance state and maintains the state (voltage) immediately before turning off, which is not related to the operation of the switch SW1-4. As a result, the voltage between the X electrode Xm and the Y electrode Ym does not reach the discharge start voltage. That is, the pixel PX of the corresponding display line is not lit during the discharge inhibition period DIS.
  • the discharge inhibition period DIS ends when the switch SW6m is turned on in synchronization with the switch SW3 being turned on.
  • the OFF period of switch SW6m is set to the same length as one discharge cycle.
  • the number of discharge cycles of the display line Ym is set to be smaller by one discharge cycle than the display line Yn.
  • the discharge inhibition period DIS is set at the end of the sustain period SUS.
  • the position of the discharge inhibition period DIS may be at the beginning or middle of the sustain period SUS. Sarako, no discharge period By changing the position of the DIS, it is possible to prevent false contours and improve the quality of the displayed image.
  • the switch SW6 (SW6n, SW6m) of the scan driver circuit SD used for the address period ADR is turned off during the sustain period SUS, so that the resonance pulse applied to the Y electrode is reduced.
  • the number (number of discharge cycles) can be easily adjusted for each display line. In other words, even when the resonance pulse force common to all Y electrodes is generated by the driver circuit DRV (Y), the number of discharge cycles in the sustain period SUS can be adjusted independently only by controlling the switch SW6. . Furthermore, since the number of discharge cycles can be adjusted simply by controlling the on / off state of the switch SW6, the logic for generating the discharge inhibition period DIS in the sustain control circuit 64 can be easily configured.
  • FIG. 10 shows the number of discharge cycles in each subfield when there is an unnecessary subfield when the display rate is larger than the threshold value.
  • the shaded portion of the figure shows a subfield in which the number of discharge cycles is set to be less than the minimum value of the number of times N2 or more than the maximum value of the number of times N2.
  • the upper and lower display lines Ll and L4 are high luminance areas H (high gradation areas) in any of the red (R), green (G), and blue (B) discharge cells. Does not have.
  • the center display line L2-3, red (R), green (G), and blue (B) discharge cells for example, as shown in FIG. It is separated into a gradation area) and a high luminance area H (high gradation area). That is, the display lines Ll and L4 have an unnecessary subfield in the upper subfield.
  • the display line L2-3 has an unnecessary subfield in a subfield other than the topmost subfield.
  • the figure shows five control methods (1) to (5) and two comparative examples.
  • the maximum value of the display gradation (number of discharge cycles) of the image displayed on the PDP is 512 (the luminance value of the input image) based on the display rate. 50%) or less)
  • Method (4) is an example where the maximum value of the display gradation (number of discharge cycles) of the image displayed on the PDP is suppressed to 768 (75% of the luminance value of the input image) or less based on the display rate. Is shown.
  • Method (5) is based on the display rate and the image displayed on the PDP.
  • the maximum value of the display gradation (number of discharge cycles) is suppressed to 832 (approximately 80% of the luminance value of the input image) or less.
  • the present invention is not applied when the maximum display gradation (number of discharge cycles) of the image displayed on the PDP is suppressed to 512 and 768 or less based on the display rate. An example of the case is shown.
  • the control unit CNT shown in FIG. 6 performs discharge control of unnecessary subfields using at least one of methods (1) and (5).
  • the number of unnecessary subfield SF8 discharge cycles is set to 1 for display lines Ll and L4.
  • One discharge cycle can be realized by first turning off the switch SW6m after the Y electrode (for example, Ym shown in FIG. 9) is first set to the voltage VsZ2 during the sustain period SUS. That is, in this case, one discharge cycle can be realized by the first discharge and the last discharge of the sustain period SUS.
  • the number of discharge cycles in unnecessary subfield SF7 is set to 1, and the number of discharge cycles in subfield SF8 is set to 384.
  • the PDP displays a high-intensity image with a display gradation of 384 or higher. it can.
  • a low-luminance image with a display gradation (number of discharge cycles) of 256 or less can be displayed in 256 gradations.
  • a low-luminance image with a display gradation (number of discharge cycles) of 128 or less can be displayed in 128 gradations.
  • a low-brightness image with a display gradation (number of discharge cycles) of 256 or less is displayed in 128 gradations on the display lines Ll and L4.
  • the display gradation (number of discharge cycles) on display line L2-3 is 128 or less. Low, images are displayed in 64 gradations.
  • the number of gradations of an image with low brightness can be increased, and the image quality of an image with low brightness can be improved.
  • the number of discharge cycles in subfield SF1-8 is set to the number N2 calculated based on the display rate (for example, set to display line L1 4 in Comparative Example 1). Is set to N2).
  • the number of discharge cycles in subfield SF1-7 shown in FIG. 3 is set to half of the number of times N2 in display line L14. Furthermore, for display lines Ll and L4, the number of discharge cycles of unnecessary subfield SF8 is set to 128, and for display line L2-3, the number of discharge cycles of subfield SF8 is set to 384. As a result, the same effect as method (1) can be obtained.
  • Method (3) shows an example in which the unnecessary subfields of display lines Ll and L4 are subfields SF7 and SF8, and the unnecessary subfield of display line L2-3 is subfields SF6 and SF7.
  • the number of discharge cycles in subfield SF2-7 is set to one-fourth of number N2, and the number of discharge cycles in subfield SF1 is set to zero.
  • the number of discharge cycles for unnecessary subfield SF8 is set to 64, and for display line L2-3, the number of discharge cycles for subfield SF8 is set to 448.
  • the unnecessary subfield of the display lines Ll and L4 is the subfield SF8 and the unnecessary subfield of the display line L2-3 is the subfield SF7 is shown.
  • the maximum value of the display gradation (number of discharge cycles) of the image displayed on the PDP is suppressed to 768 (75% of the luminance value of the input image) or less based on the display rate.
  • the number of discharge cycles in subfield SF1-8 is set to 4, 8, 16, 32, 64, 128, 256, and 2, respectively.
  • the display line is set to L2-3, and the discharge cycle number of sub-fino red SF1-8 is set to 4, 8, 16, 32, 64, 128, 2, 512, respectively.
  • the increment of the display gradation (number of discharge cycles) is “3”.
  • the increment of the display gradation (number of discharge cycles) is “2”. That is, the number of gradations of an image with low luminance can be increased, and the same effect as the method (1) can be obtained.
  • a high-brightness image with a tone of 512 or more can be displayed.
  • Method (5) shows an example in which the unnecessary subfields of display lines Ll and L4 are subfields SF7 and SF8, and the unnecessary subfield of display line L2-3 is subfields SF5 and SF6.
  • the maximum value of the display gradation (number of discharge cycles) of the image displayed on the PDP is suppressed to 832 (approximately 80% of the luminance value of the input image) or less based on the display rate. It is an example.
  • the number of discharge cycles of subfield SF 1-8 is set to 1, 2, 4, 8, 16, 32, 64, and 128, respectively.
  • the display line L2-3 is set to ⁇
  • the number of discharge cycles of sub-fino red SF1-8 is set to 1, 2, 4, 8, 16, 32, 256, 512.
  • the same effect as the method (4) can be obtained.
  • the PDP can display high-luminance images with a display gradation of 768 or higher.
  • the sustain discharge of N1 times is set in the subfield SF1-8.
  • the display gradation (display luminance) can be suppressed by reducing the number of sustain discharges of each pixel.
  • Subfields SF1 and SF2 having 2) are configured. In other words, it is possible to increase the number of gradations of a low-luminance image and obtain the same effect as method (1).
  • the unnecessary subfield includes the subfield SF7 in which the sustain discharge of the second largest number of times N2 is set.
  • the gradation detection circuit 62 only needs to determine whether or not there is an unnecessary subfield only when the luminance distribution of the input image is separated into low luminance and high luminance, thus simplifying the detection process. Can be.
  • the brightness of the image is less than half of the maximum brightness.
  • the human eye is the image of relatively low brightness. It is sensitive to changes in brightness. For this reason, increasing the number of gradations of an image with low luminance has a greater effect of improving the image quality than increasing the number of gradations of an image with high luminance. This is because when the difference in the number of discharge cycles is "4", the difference in luminance between 256 and 260 discharge cycles (luminance variation of about 1.5%) is the difference in luminance between 512 and 516 discharge cycles. It is clear from the fact that it is easier to discriminate than (approximately 0.8% luminance change).
  • FIG. 11 shows the input gradation of the image data and the display gradation (number of discharge cycles) of the image displayed on the PDP in the methods (1), (2), and (3) shown in FIG. Show an example of the relationship.
  • FIG. 11 shows a case where the methods (1), (2), and (3) are applied to the display line L2-3 shown in FIG.
  • the broken line in the figure shows the relationship between the input gradation and the display gradation
  • the thick solid line shows the gradation (luminance) of the image actually displayed on the display line L2-3.
  • the display gradation of the image displayed on the PDP is reduced to 50% of the actual input gradation of the image in order to reduce power consumption.
  • an image can be displayed in which a low luminance region L with an input gradation of 256 or less and a high luminance region H with an input gradation force of S768 or higher are mixed.
  • Method (3) can display an image in which a low luminance region L with an input gradation of 128 or less and a high luminance region H with an input gradation of 896 or more are mixed.
  • FIG. 12 shows an example of the relationship between the input gradation of the image data and the display gradation (number of discharge cycles) of the image displayed on the PDP in the methods (4) and (5) shown in FIG. Is shown.
  • Fig. 12 shows the case where methods (4) and (5) are applied to the display line L2-3 shown in Fig. 10. The meanings of the broken line and the thick solid line in the figure are the same as those in FIG. 11 described above.
  • the display gradation of the image displayed on the PDP is reduced to 75% of the input gradation of the actual image in order to reduce power consumption.
  • Method (4) can display an image in which the low luminance region L with an input gradation of 340 or less and the high luminance region H with an input gradation of 684 or more are mixed.
  • the display gradation of the image displayed on the PDP is reduced to 80% of the input gradation of the actual image in order to reduce power consumption.
  • a low luminance region L with an input gradation of 80 or less, a high luminance region H with an input gradation of 960 or more, and an intermediate luminance region M with an input gradation of 320 to 400 are mixed. An image can be displayed.
  • FIG. 13 shows image data in the methods (1), (2), (3) and Comparative Example 1 shown in FIG. This shows an example of the relationship between the input gradation and the display gradation (number of discharge cycles) when the data is quantized.
  • the display gradation increases by two for every four increase in the value of the image data R0-9, GO-9, and B0-9. Specifically, it is set as a value power display gradation in which the lower 2 bits of the image data R0-9, G0-9, B0-9 are reset to "00". This is equivalent to displaying an image of 256 gradations using the upper 8-bit image data R2-9, G2-9, and B2-9.
  • the minimum unit for quantizing the display gradation (luminance value) for displaying the input pixel data R0-9, GO-9, and B0-9 is "4" "It is.
  • the display gradation is increased every time the value of the image data R0-9, GO-9, and B0-9 increases by two. Increase by one. That is, in the display line L14 having an unnecessary subfield, the minimum unit for quantizing the display gradation (luminance value) is “2”, and in the case of Comparative Example 1 to which the present invention is not applied. It is set smaller than this.
  • the display gradation of the display line in which the unnecessary subfield exists is changed to the comparative example 1 or the unnecessary subfield where the present invention is not applied. Can be doubled compared to the display gradation of display lines that do not exist
  • FIG. 14 shows an example of the relationship between the input gradation and the display gradation (number of discharge cycles) when quantizing the image data in the method (4) and the comparative example 2 shown in FIG. ing.
  • the increment of the display gradation is “3”.
  • the gradation of the display gradation is “2”.
  • the display gray scale of the display line in which the unnecessary subfield exists is not applied to the display line in the comparative example 2 without applying the present invention. It can be reduced to two-thirds compared to the display gradation increment of the display line that does not.
  • FIG. 15 shows an example of the relationship between the input gradation and the display gradation (number of discharge cycles) when image data is quantized in the method (5) shown in FIG.
  • the increment of the display gradation is “1”.
  • the display gradation of the display line in which the unnecessary subfield exists is not changed, and the present invention is not applied, and the display gradation of the display line in the comparative example 2 or the unnecessary subfield does not exist. It can be reduced to 1/3 compared to the step.
  • an unnecessary subfield when the display rate is larger than the threshold, an unnecessary subfield can be provided, and the number of discharge cycles calculated based on the display rate using this unnecessary subfield.
  • a sub-field having a number of discharge cycles smaller than the minimum number of times (number N2) can be configured. Therefore, when a high-brightness image and a low-brightness image are mixed, the number of gradations of the relatively low-brightness image can be increased compared to the conventional case, and the image quality of the low-brightness image can be improved.
  • the gradation detection circuit 62 has a subfield when no sustain discharge occurs and the subfield exists for the number of discharge cycles set by the load control circuit 68 regardless of the display rate.
  • a subfield can be detected as an unnecessary subfield.
  • a subfield having a number of discharge cycles smaller than the minimum number of discharge cycles set by the load control circuit 68 can be configured by using an unnecessary subfield. Therefore, when a high-brightness image and a low-brightness image are mixed, the number of gradations of the relatively low-brightness image can be increased compared to the conventional case, and the image quality of the low-brightness image can be improved.
  • FIG. 16 shows details of the Y driver YDRV and the X driver XDR V in the second embodiment of the present invention.
  • the scan driver circuit SD of the Y driver YDRV is different from the first embodiment.
  • the configuration excluding the scan driver circuit SD is the same as that of the first embodiment (FIGS. 1 to 7).
  • the same elements as those described in the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.
  • the switch SW6 (SW6n, SW6m) of the scan driver circuit SD is It is composed of IGBTs, not nMOS transistors.
  • An IGBT is a bipolar transistor that incorporates MOSFE T in its gate. Unlike an nMOS transistor, an IGBT does not have a parasitic diode between the source and drain. For this reason, for example, even when the node ND2 rises to VsZ2 while the switch SW6m is off, the voltage of the Y electrode Ym does not change.
  • FIG. 17 shows details of operations in the address period ADR and the sustain period SUS shown in FIG. 3 in the second embodiment. Detailed description of the same operations as those in FIG. 9 described above will be omitted.
  • This embodiment is different from the first embodiment in the method of setting the discharge inhibition period DIS (control method of the switch SW6 m) and the voltage of the Y electrode Ym in the discharge inhibition period DIS. Other waveforms are the same as those in the first embodiment (FIG. 9).
  • the discharge inhibition period DIS is generated by turning off the switch SW6m before the switch SW1 is turned on after the Y electrode Ym is clamped to the voltage -VsZ2.
  • the switch SW6m is turned off, the Y electrode Ym enters the no-impedance state and maintains the state (voltage) immediately before turning off.
  • the voltage between the X electrode Xm and the Y electrode Ym does not reach the discharge start voltage.
  • the discharge inhibition period DIS ends when the switch SW6m is turned on in synchronization with the switch SW4 being turned on.
  • the switch SW6m is turned off for the entire sustain period SUS, so that a specific Y electrode (Ym in this example) is used during the sustain period SUS, as indicated by a thick broken line in the figure. Discharge can be prohibited. At this time, discharge occurs only in the address period ADR and the erase period ERS. Furthermore, as described in the subfield SF6 of the control method (7) shown in FIG. 10, it is possible to inhibit discharge during the address period ADR by not selecting a discharge cell during the address period ADR. Therefore, for example, when the switch SW6m is turned off throughout the sustain period SUS, the luminance in the case of a discharge cycle power of 0 "can be changed depending on whether or not the address pulse is applied. The low V and the number of gradations of the image ( ⁇ , image) can be further increased.
  • the position of the discharge inhibition period DIS may be the first or middle of the sustain period SUS. Furthermore, by changing the position of the discharge inhibition period DIS, it is possible to prevent false contours and improve the quality of the display image. As described above, also in the second embodiment, it is possible to obtain the same effect as that of the first embodiment described above. Furthermore, the number of discharge cycles can be set to “0” in the sustain period SUS by forming the scan driver circuit SD with an IGBT having no parasitic diode between the source and drain. Therefore, the number of gradations of an image with low brightness (dark image) can be further increased by selecting whether or not to apply an address pulse.
  • the present invention is configured so that one field has eight subfields SF1.
  • the example applied to the plasma display panel consisting of 8 was described.
  • the invention is not limited to the powerful embodiments.
  • the present invention may be applied to a plasma display panel in which one field is composed of 10 or more subfields.
  • the number of subfield discharge cycles is not limited to 2 to the nth power (n is an integer of 2 or more).
  • the subfields SFl-8 (Fig. 3) in the field FLD need not be arranged sequentially.
  • subfield SF8 may be arranged near the center of field FLD.
  • one pixel PX force is composed of three discharge cells (red (R), green (G), and blue (B)) has been described.
  • the invention is not limited to the powerful embodiments.
  • one pixel PX may be composed of four or more discharge cells.
  • one pixel PX force may be composed of discharge cells that generate colors other than red (R), green (G), and blue (B). Discharge cells that generate colors other than (G) and blue (B) may be included.
  • the display gradation of the image displayed on the PDP 10 is obtained from the 10-bit image data RO-9, GO-9, and BO-9 has been described.
  • the present invention is not limited to powerful embodiments.
  • the 12-bit image data power can also be used to determine the display gradation of the image displayed on the PDP10.
  • the input gradation indicated by the upper 10 bits of the 12-bit image data corresponds to the input gradation indicated by the 10-bit image data RO-9, GO-9, and BO-9 in the first embodiment.
  • the input gradation step can be reduced to a quarter of the input gradation step in the above-described embodiment.
  • FIG. 18 shows an example of the relationship between the input gradation of 12-bit image data and the display gradation (number of discharge cycles) of the image displayed on the PDP.
  • Figure 18 corresponds to method (5) shown in Figure 10.
  • the thin solid line in the figure shows the relationship between the input gradation and the display gradation when the image displayed on the PDP is set to 80% of the luminance value ORG (dashed line in the figure) of the actual image.
  • the value of the image data increases by the display gradation force S1 every time 5 is increased.
  • the display gradation can be increased evenly with respect to the increase of 5 increments of the image data. Also in this case, the same effect as the above-described embodiment can be obtained.
  • the present invention can be applied to a plasma display panel and a plasma display device.

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  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

Selon la présente invention, un champ pour afficher un écran d'un panneau d'affichage plasma est constitué d'une pluralité de sous-champs. Une image est affichée par tramage à multiniveaux lorsque la décharge soutenue est générée de façon sélective dans chaque sous-champ. Un circuit de détection de charge détecte la vitesse d'affichage, c'est-à-dire le rapport de luminance d'une image réelle par rapport à la luminance maximale du panneau d'affichage plasma. Lorsque le taux d'affichage est supérieur à une valeur seuil, un circuit de détection de niveaux de gris détecte la présence ou non d'un sous-champ superflu en ajustant le nombre de décharges soutenues de chaque sous-champ pour chaque ligne d'affichage. S'il y a un sous-champ superflu, un circuit de commande soutenue effectue un contrôle pour générer un nombre plus petit de décharges soutenues qu'en cas d'absence de sous-champ superflu. Par conséquent, les niveaux de gris d'une image à faible luminance peuvent être augmentés et la qualité de l'image peut être améliorée.
PCT/JP2006/321560 2006-10-27 2006-10-27 Procédé pour faire fonctionner un panneau d'affichage plasma et dispositif d'affichage plasma WO2008053510A1 (fr)

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Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10222123A (ja) * 1997-02-06 1998-08-21 Fujitsu General Ltd Ｐｄｐ表示装置
JPH10282929A (ja) * 1997-04-09 1998-10-23 Fujitsu Ltd 階調表示方法
JPH1165519A (ja) * 1997-08-21 1999-03-09 Victor Co Of Japan Ltd プラズマディスプレイパネル表示装置及びその駆動方法
JPH1165520A (ja) * 1997-08-21 1999-03-09 Victor Co Of Japan Ltd プラズマディスプレイパネル表示装置及びその駆動方法
JPH1165521A (ja) * 1997-08-20 1999-03-09 Fujitsu General Ltd ディスプレイの駆動方式
JPH11231825A (ja) * 1997-12-10 1999-08-27 Matsushita Electric Ind Co Ltd 明るさによるサブフィールド数調整可能な表示装置
WO2001056003A2 (fr) * 2000-01-26 2001-08-02 Thomson Licensing S.A. Procede de traitement d'images video en vue de l'affichage sur un dispositif d'affichage
JP2001306019A (ja) * 2000-04-18 2001-11-02 Pioneer Electronic Corp ディスプレイパネルの駆動方法
JP2006209078A (ja) * 2005-01-25 2006-08-10 Samsung Sdi Co Ltd プラズマ表示装置及びその駆動方法

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10222123A (ja) * 1997-02-06 1998-08-21 Fujitsu General Ltd Ｐｄｐ表示装置
JPH10282929A (ja) * 1997-04-09 1998-10-23 Fujitsu Ltd 階調表示方法
JPH1165521A (ja) * 1997-08-20 1999-03-09 Fujitsu General Ltd ディスプレイの駆動方式
JPH1165519A (ja) * 1997-08-21 1999-03-09 Victor Co Of Japan Ltd プラズマディスプレイパネル表示装置及びその駆動方法
JPH1165520A (ja) * 1997-08-21 1999-03-09 Victor Co Of Japan Ltd プラズマディスプレイパネル表示装置及びその駆動方法
JPH11231825A (ja) * 1997-12-10 1999-08-27 Matsushita Electric Ind Co Ltd 明るさによるサブフィールド数調整可能な表示装置
WO2001056003A2 (fr) * 2000-01-26 2001-08-02 Thomson Licensing S.A. Procede de traitement d'images video en vue de l'affichage sur un dispositif d'affichage
JP2001306019A (ja) * 2000-04-18 2001-11-02 Pioneer Electronic Corp ディスプレイパネルの駆動方法
JP2006209078A (ja) * 2005-01-25 2006-08-10 Samsung Sdi Co Ltd プラズマ表示装置及びその駆動方法

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