WO2008050454A1 - Écran plasma et son procédé de pilotage - Google Patents

Écran plasma et son procédé de pilotage Download PDF

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Publication number
WO2008050454A1
WO2008050454A1 PCT/JP2006/321559 JP2006321559W WO2008050454A1 WO 2008050454 A1 WO2008050454 A1 WO 2008050454A1 JP 2006321559 W JP2006321559 W JP 2006321559W WO 2008050454 A1 WO2008050454 A1 WO 2008050454A1
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WIPO (PCT)
Prior art keywords
sustain
subfield
electrode
display line
discharge
Prior art date
Application number
PCT/JP2006/321559
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English (en)
Japanese (ja)
Inventor
Takashi Sasaki
Akihiro Takagi
Original Assignee
Hitachi Plasma Display Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Plasma Display Limited filed Critical Hitachi Plasma Display Limited
Priority to PCT/JP2006/321559 priority Critical patent/WO2008050454A1/fr
Publication of WO2008050454A1 publication Critical patent/WO2008050454A1/fr

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
    • G09G3/291—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes
    • G09G3/294—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes for lighting or sustain discharge
    • G09G3/2946—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes for lighting or sustain discharge by introducing variations of the frequency of sustain pulses within a frame or non-proportional variations of the number of sustain pulses in each subfield

Definitions

  • the present invention relates to a plasma display panel driving method and a plasma display device.
  • the present invention relates to a plasma display panel and a plasma display device.
  • a plasma display panel is formed by bonding two glass substrates together, and displays an image by generating discharge light in a space formed between the glass substrates.
  • the discharge cells corresponding to the pixels in the image are self-luminous, and are coated with phosphors that generate red, green, and blue visible light in response to ultraviolet rays generated by the discharge.
  • a field for displaying one screen is composed of a plurality of subfields.
  • the number of subfield discharges is sequentially set to 2 to the nth power (n is a positive integer).
  • n is a positive integer.
  • a multi-tone image is displayed by selectively lighting the discharge cells in accordance with the luminance of the image. For example, in a high luminance image (high gradation image), a subfield with a large number of discharges is selected, but in a low luminance image (low gradation image), a subfield with a large number of discharges is not selected.
  • a PDP has been proposed that detects the total amount of display data for each display line and adjusts the number of sustain discharges in the subfield according to the data amount (see, for example, Patent Document 1).
  • the luminance power of an image of a display line with a small amount of data is used to prevent a relatively high luminance compared to the luminance of an image of a display line with a large amount of data.
  • the number of sustain discharges is reduced.
  • An object of the present invention is to lower the luminance of a dark image and improve the image quality when a bright image and a dark image are mixed in the screen.
  • one field for displaying one screen of the plasma display panel includes a first subfield having a relatively small number of sustain discharges and a second subfield having a relatively large number of sustain discharges. Consists of fields.
  • the sustain discharge is selectively generated between the first and second electrodes, so that the image is displayed in multi-tone.
  • the detection circuit detects whether a sustain discharge is generated in the second subfield for each display line.
  • the display line is composed of pixels formed along the first electrode.
  • the sustain control circuit generates a preset standard number of sustain discharges in each subfield in a high-luminance display line that generates sustain discharge in the second subfield.
  • the sustain control circuit does not generate a sustain discharge in the second subfield, but generates a sustain discharge less than the standard number in at least one of the first subfields in a low-luminance display line.
  • the luminance of the dark image can be further lowered and the image quality can be improved.
  • FIG. 1 is an exploded perspective view showing a first embodiment of the present invention.
  • FIG. 2 is an exploded perspective view showing details of a main part of the PDP shown in FIG.
  • FIG. 3 is an explanatory diagram showing a configuration example of a field for displaying an image of one screen.
  • FIG. 4 is a waveform diagram showing an example of a discharge operation in the subfield shown in FIG.
  • FIG. 5 is a block diagram showing an outline of the circuit unit shown in FIG. 1.
  • FIG. 6 is a flowchart showing the operation of the control unit shown in FIG.
  • FIG. 7 is a circuit diagram showing details of the Y driver and the X driver shown in FIG. 3.
  • FIG. 8 is a timing chart showing details of operations in the address period and the sustain period shown in FIG. 3.
  • FIG. 9 is an explanatory diagram showing the number of discharge sites in each subfield in a low luminance display line and a high luminance display line.
  • FIG. 10 is an explanatory diagram showing the number of discharge cycles in each subfield of the display line in the second embodiment of the present invention.
  • FIG. 11 is a circuit diagram showing details of a Y driver and an X driver in a third embodiment of the present invention.
  • FIG. 12 is a timing chart showing details of operations in the address period and the sustain period shown in FIG. 3 in the third embodiment.
  • FIG. 13 is a block diagram showing an outline of a circuit unit in a fourth embodiment of the present invention.
  • FIG. 1 shows a first embodiment of the present invention.
  • a plasma display device (hereinafter also referred to as a PDP device) is a plasma display panel 10 having a square plate shape (hereinafter also referred to as a PDP), and an optical filter provided on the image display surface 12 side (light output side) of the PDP10.
  • PDP10 image display surface 12 is mounted on the front housing 30 side
  • PDP10 rear panel 40 is mounted on the back side 14 and base chassis 50
  • base chassis 50 is mounted on the rear housing 40 side
  • PDP10 Circuit unit 60 for driving the PDP 10 and a double-sided adhesive sheet 70 for attaching the PDP 10 to the base chassis 50. Since the circuit part 60 is composed of a plurality of parts, it is indicated by a dashed box in the figure.
  • the PDP 10 includes a front substrate 16 (first substrate) that forms the image display surface 12 and a rear substrate 18 (second substrate) that faces the front substrate 16.
  • a discharge space (discharge cell) (not shown) is formed between the front substrate 16 and the rear substrate 18.
  • the front substrate 16 and the back substrate 18 are formed of, for example, a glass substrate.
  • the optical filter 20 is attached to a protective glass (not shown) attached to the opening 32 of the front housing 30.
  • FIG. 2 shows details of a main part of the PDP 10 shown in FIG.
  • the front substrate 16 has X electrodes 16b (first electrode, sustain electrode) and Y electrodes 16c (first electrode and sustain electrode) formed in parallel and alternately on the glass substrate 16a (lower side in the figure) in order to generate discharge repeatedly.
  • the X electrode 16b and the Y electrode 16c are composed of a bus electrode BE (electrode line) extending in the horizontal direction in the figure and a transparent electrode TE connected to the bus electrode BE.
  • the electrodes 16b and 16c are covered with a dielectric layer 16d, and the surface of the dielectric layer 16d is covered with a protective layer 16e such as MgO.
  • the rear substrate 18 facing the front substrate 16 through the discharge space DS has address electrodes 18b (third electrodes) formed in parallel with each other on the glass base material 18a.
  • the address electrode 18b is arranged in a direction orthogonal to the bus electrode BE.
  • the address electrode 18b is covered with a dielectric layer 18c.
  • partition walls (ribs) 18d are formed at positions corresponding to between the adjacent address electrodes 18b.
  • the side wall of the discharge cell is constituted by the barrier rib 18d.
  • visible light of red (R), green (G), and blue (B) is emitted on the side surface of the partition wall 18d and on the dielectric layer 18c between the partition walls 18d adjacent to each other by being excited by ultraviolet rays.
  • the resulting phosphors 18e, 18f, and 18g are applied respectively.
  • One discharge cell (one color pixel) of the PDP 10 is formed in a region including a pair of transparent electrodes TE in a region surrounded by a pair of adjacent barrier ribs 18d. That is, the discharge cell is formed at the intersection of the electrodes 16b and 16c and the electrode 18b.
  • the PDP 10 is configured by disposing discharge cells in a matrix in order to display an image, and alternately arranging a plurality of types of discharge cells that generate light of different colors.
  • one pixel PX shown in FIG. 5 described later is composed of three discharge cells that generate red, blue, and green light.
  • a display line is constituted by discharge cells formed along the electrodes 16b and 16c.
  • the PDP 10 is configured by bonding the front substrate 16 and the rear substrate 18 so that the protective layer 16e and the partition wall 18d are in contact with each other and enclosing a discharge gas such as Ne or Xe.
  • the bus electrode BE is connected to the X driver XDRV and the Y driver YDRV shown in FIG.
  • the address electrode 18b is connected to the address driver ADRV shown in FIG.
  • FIG. 3 shows a configuration example of the field FLD for displaying an image of one screen.
  • One Fino Red FLD has a length of 1Z60 seconds (about 16.7 ms), and is composed of, for example, 8 subfields SF (SF1-SF8).
  • Each subfield SF includes a reset period RST, an address period ADR, a sustain period SUS, and an erase period ERS.
  • the erasing period ERS is defined as being included in the sustaining period SUS because it is a period for generating a discharge for erasing the wall charges of only the lit discharge cells.
  • the wall charge is, for example, a brass charge and a minus charge accumulated on the MgO layer 16e shown in FIG. 2 in each discharge cell.
  • the reset period RST, address period ADR, and erase period ERS have the same length regardless of the subfield SF.
  • the sustain period SUS length varies depending on the subfield SF and depends on the number of discharges (luminance) of the discharge cell. For this reason, it is possible to display an image in multiple gradations by changing the combination of the subfields SF to be lit.
  • the standard number of discharge cycles (standard number of sustain discharges) of subfield SF1-8 is 4, 8, 16, 32, 64, 128, 256, and 512, respectively.
  • the upper subfields SF8 and SF7 are used for high luminance (high gradation) images, and the upper subfields SF8 and SF7 are not used for low luminance (low gradation) images.
  • the number of discharge cycles indicates the number of sustain pulses applied to the X electrode 16 b (or Y electrode 16c). As shown in Fig. 4 below, the discharge cell is discharged twice during one discharge cycle CYC (star in the figure).
  • the subfield SF1-3 is treated as the first subfield IstSF with a relatively small number of sustain discharges (4, 8, 16), and the subfield SF4-8 is the sustain discharge. It is treated as the 2nd subfield 2ndSF with a relatively large number of times (32, 64, 128, 256, 512).
  • FIG. 4 shows an example of the discharge operation of subfield SF shown in FIG.
  • the star in the figure indicates the occurrence of discharge.
  • a negative write voltage is applied to the sustain electrode X (X electrode 16b), and a positive write voltage (write blunt wave) that rises slowly is a scan electrode Y (Y electrode 16c).
  • a positive adjustment voltage is applied to the sustain electrode X, and a negative adjustment voltage (adjusted blunt wave) is applied to the scan electrode (FIG. 4 (b)).
  • the positive adjustment voltage is a voltage lower than the voltage VsZ2
  • the negative adjustment voltage is a voltage higher than the voltage VsZ2.
  • a negative pre-erase pulse and a positive high-voltage pre-erase pulse force X are applied to the sustain electrode X and the scan electrode Y, respectively, and discharge occurs (FIG. 4 (g)).
  • wall charges are accumulated in the sustain electrode X and the scan electrode Y.
  • positive erase pulse and negative erase pulse force are applied to sustain electrode X and scan electrode Y, respectively (Fig. 4 (h)). As a result, discharge occurs and the amount of wall charges is reduced.
  • a slowly decreasing negative voltage (blunt wave) is applied to the sustain electrode X and applied to the positive pulse force scanning electrode Y (Fig. 4 (i)).
  • the discharge in the erase period ERS is not included in the discharge cycle. This completes the SF for one subfield period.
  • the number of discharge cycles is “3” (six discharges in the sustain period SUS), which is the same as the number of pulses of the scan electrode Y.
  • the Y driver YDRV and the X driver XDRV shown in FIGS. 7 and 11, which will be described later, have predetermined voltages (eg, positive adjustment voltage, negative The description of the circuit for applying the adjustment voltage to the sustain electrode X and the scan electrode Y is omitted.
  • FIG. 5 shows an outline of the circuit unit 60 shown in FIG.
  • the circuit unit 60 includes an X driver XDRV (first drive circuit) that applies a common pulse to the X electrode 16b, a Y driver YDRV (second drive circuit) that selectively applies a pulse to the Y electrode 16c, and an address electrode. It has an address driver ADRV (third drive circuit) that selectively applies pulses to 18b, a control unit CNT that controls the operation of the drivers XDRV, YDRV, and AD RV, and a power supply unit PWR.
  • Drivers XDRV, YDRV, and ADRV operate as a drive unit that drives the PDP 10.
  • the control unit CNT includes a gradation detection circuit 62 that obtains a high-luminance display line and a low-luminance display line, which will be described later, and a sustain that controls the operation of the X driver XDRV and the Y driver YDRV to generate a sustain discharge. And a control circuit 64.
  • Image data RO—R 7, G0—G7, and BO—B7 are 8-bit data for displaying red, green, and blue, respectively. Input sequentially.
  • 256 luminance (256 gradations) force image data are expressed according to the bit values of RO-R7, GO-G7, and BO-B7.
  • a bit with a small number has a high weight for a bit with a small number (high order bit) with a small weight. Note that the number of gradations can be increased by increasing the number of subframes.
  • the gradation detection circuit 62 obtains a subfield SF for use in displaying an image for each pixel based on the image data R0—R7, G0—G7, and BO—B7.
  • the subfield SF to be lit for each pixel PX is obtained by calculation.
  • a display line including a high luminance (high gradation) image and a display line not including a high luminance image are detected.
  • the display line is composed of the pixels PX arranged along the electrodes 16b and 16c.
  • one pixel PX includes three discharge cells that generate red, blue, and green light. Each pixel PX should be composed of 3 or more discharge cells.
  • a display line containing only a low-luminance image lights at least! / Of sub-field SF1-3 (first sub-field IstSF), and sub-field SF4- Reference numeral 7 denotes a display line having non-illuminated pixels.
  • a display line including a high-intensity image is a display line having pixels that light at least one of the subfields SF4-7 (second subfield 2ndSF).
  • the gradation detection circuit 62 determines whether or not it is possible to generate a sustain discharge in the second subfield according to the image data, and outputs the calculated result to the sustain control circuit 64.
  • the sustain control circuit 64 performs sustain for a predetermined standard number of times (4, 8,..., 512 shown in FIG. 3) in each subfield SF1-8.
  • control signals YCNT and XCNT are output to drivers YDRV and XDRV, and control signal ACNT is output to driver ADRV. That is, the sustain control circuit 64 applies the first subfield SF1-8 to the first subfield SF1-8 in the high luminance display line that generates the sustain discharge not only in the first subfield SF1-3 but also in the second subfield SF4-8.
  • the standard number of sustain discharges is generated.
  • the sustain control circuit 64 outputs control signals YCNT and XCNT in order to display a 256-gradation image corresponding to the image data R0-R7, G0-G7, and BO-G7.
  • the sustain control circuit 64 sets the number of sustain discharges of the subfield SF1-3 to be smaller than the standard number in the display line with low luminance. That is, the sustain control circuit 64 generates the sustain discharge only in the first subfield SF1-3, and the first subfield SF1-3 in the low-luminance display line that does not generate the sustain discharge in the second subfield SF4-8. However, the sustain discharge is generated a smaller number of times than the standard number. For example, the number of sustain discharges in subfield SF1-3 is set to 2, 4, and 8, which are half the standard number.
  • control signal YCNT is a switch control signal SW1, SW2, S shown in FIG. Includes W3, SW4, SW5n, SW5m, SW6n, SW6m.
  • the control signal XCNT includes switch control signals SW7, SW8, SW9, and SW10 shown in FIG.
  • the control signal ACNT is a timing signal for generating an address pulse.
  • the power supply PWR generates the power supply voltages Vsc, Vs / 2, one VsZ2, and Vsa that are supplied to the drivers YDRV, XDRV, and ADRV.
  • Y driver YDRV has a scan driver circuit SD for each Y electrode 16c. As a result, a desired number of sustain pulses can be selectively applied to each Y electrode 16c.
  • FIG. 6 shows an operation of the control unit CNT shown in FIG. In FIG. 6, only the control related to the sustain period SUS is shown, and the control related to the address period ADR is not shown.
  • the flow in Fig. 6 may be realized by controlling the hardware, which may be realized only by hardware, by software.
  • step S10 the gradation detection circuit 62 receives image data RO-7, GO-7, BO-7 for one display line.
  • the control unit CNT shown in FIG. 5 continuously receives image data of a plurality of display lines and a plurality of screens. Therefore, the control unit CNT performs the flow of FIG. 6 every time it receives image data of one display line.
  • the gradation detection circuit 62 determines, for each pixel PX, a subfield SF that is lit to display an image, based on the image data of one display line.
  • the upper subfield SF4-8 (second subfield 2ndSF) is used in the pixel PX that displays an image with relatively high luminance. That is, the gradation detection circuit 62 determines whether or not to generate a sustain discharge in the second subfield SF4-8 according to the image data.
  • the gradation detection circuit 62 reduces the brightness of the display line when the second subfield SF4-8 is not used in all the discharge cells (red, blue, and green) in each pixel PX in the display line. The display line is determined.
  • the gradation detection circuit 62 converts the display line to a high-luminance display line. Is determined.
  • step S14 the sustain control circuit 64 determines whether or not the display line is a low luminance display line that does not generate a sustain discharge in the second subfield SF4-8 based on the information from the gradation detection circuit 62. judge.
  • step S16 The sustain control circuit 64 controls the operations of the drivers XDRV and YDRV in order to generate a predetermined standard number of sustain discharges using all the subfields SF1-8.
  • the number of discharges of each subfield SF1-8 set by this operation is a preset standard number of discharge cycles.
  • the operation in step S16 is, for example, an operation for displaying display lines L2 and L3 in FIG. 9 to be described later.
  • the sustain control circuit 64 assigns the second subfield SF1-3 to a subfield that generates a number of sustain discharges less than the standard number.
  • the number of sustain discharges in the first subfield SF1-3 in the low-luminance display line is set to 2, 4, and 8, which are half the standard number.
  • the sustain control circuit 64 uses the first subfield SF1-3 to control the operation of the drivers XDRV and YDRV in order to generate a newly set number of sustain discharges.
  • the operation in step S18 is, for example, an operation for displaying display lines Ll and L4 in FIG.
  • FIG. 7 shows details of the Y driver YDRV and the X driver XDRV shown in FIG.
  • the Y driver YDRV has a driver circuit DRV (Y) and a scan driver circuit SD.
  • the X driver XDRV has a driver circuit DRV (X).
  • the switches SW1, SW2, SW3, SW4, SW6 (SW6n, SW6m), SW7, SW8, SW9, SW10 shown in the figure are constituted by, for example, nMOS transistors (MOSFETs). Each nMOS transistor has a parasitic diode that connects between the source and the drain, as shown in the figure. Further, the switch SW5 (SW5n, SW5m) is configured by, for example, an IGBT (Insulated Gate Bipolar Transistor).
  • the driver circuit DRV (Y) includes a coin La, switches SW1, SW2, SW3, SW4 and a diode.
  • Coil La and switch SW1–4 operate as a resonance circuit to generate a resonance pulse on the Y electrode (Yn, Ym, etc.).
  • the resonant pulse is a signal common to all Y electrodes.
  • Switches SW1–4 are turned on when a high logic level switch control signal is received, and turned off when a low logic level switch control signal is received.
  • the drain of the switch SW1 and the source of the switch SW3 are connected to the ground line G1.
  • the source of switch SW1 is connected to one end of coil La via a forward-connected diode. Is connected to node ND1.
  • the drain of switch SW3 is connected to node ND1 through a diode connected in the reverse direction.
  • the node ND1 is connected to the power supply Vs / 2 and one Vs / 2 through diodes connected in the reverse direction.
  • the drain is connected to the power source VsZ2, and the source is connected to the node ND2, which is the other end of the coil La.
  • Switch SW4 has its source connected to the power supply—Vs / 2 and its drain connected to node ND2.
  • Node ND2 is connected to each scan driver circuit SD
  • Each scan driver circuit SD has a switch SW5 (SW5n, SW5m, etc.) and a switch SW6 (SW6n, SW6m, etc.) arranged in series between the power supply Vsc and the node ND2.
  • the switch SW5 the drain is connected to the power supply Vsc via a diode connected in the forward direction, and the source is connected to the Y electrode (Yn, Ym, etc.).
  • the drain of the switch SW5 is connected to the node ND2 via the capacitor C1.
  • Switch SW6 has its source connected to node ND2 and its drain connected to the Y electrode.
  • the driver circuit DRV (X) of the X driver XDRV has the same circuit configuration as the driver circuit DRV (Y). That is, the driver circuit DRV (X) has a coil Lb, switches SW7, SW8, SW9, SW10 and a diode.
  • the coil Lb and switch SW7-10 operate as a resonance circuit for generating a resonance pulse on the X electrode (Xn, Xm, etc.). Switches SW7-10 are turned on when a high logic level switch control signal is received, and turned off when a low logic level switch control signal is received.
  • Capacitor Cp indicates the capacitance of PDP10.
  • FIG. 8 shows details of operations in the address period ADR and the sustain period SUS shown in FIG.
  • a signal for controlling on / off of the switch SW1-10 is referred to as a switch control signal SW1-10.
  • the switch SW1-10 is turned on during the high logic level of the switch control signal SW1-10, and is turned off during the low logic level of the switch control signal SW1-10.
  • the star in the figure indicates the occurrence of discharge.
  • the corresponding switch SW5n (or SW5m) is turned off and the corresponding switch SW6n (or SW6m) is turned on in synchronization with the driving of the address electrode A1.
  • the Y electrode Yn (or Ym) is temporarily set to the voltage—VsZ2 (FIG. 8 (h, i)). Then, the scanning operation force for selecting the pixel PX to be lit is performed for each display line.
  • the voltages of the X electrodes Xn and Xm are initialized to the same voltage Vs / 2 by turning on the switch SW10 (Fig. 8 (j, k) ).
  • the voltages of the Y electrodes Yn and Ym are initialized to the voltage VsZ2 by turning on the switches SW6n and SW6m (Fig. 8 (1, m)).
  • the switches SW5n and SW5m are always turned off during the sustain period SUS.
  • ground line G1 is connected to capacitor Cp via switch SW1, coil La, switch SW6n, SW6m, and Y electrodes Yn and Ym.
  • the voltages of the Y electrodes Yn and Ym rise due to the LC resonance effect of the coil La and the capacitor Cp.
  • the switch SW2 is turned on, the voltage of the Y electrodes Yn and ⁇ m is clamped to the voltage VsZ2 (FIG. 8 (n, o)).
  • the switch SW3 when the switch SW3 is turned on, the capacitor Cp is connected to the ground line G1 via the Y electrodes Yn and Ym, the switches SW6n and SW6m, the coil La, and the switch SW3.
  • the voltage of the Y electrodes Yn and Ym drops due to the LC resonance effect of the coil La and the capacitor Cp.
  • the switch SW4 when the switch SW4 is turned on, the voltages of the Y electrodes Yn and Ym are clamped to the voltage VsZ2 (FIG. 8 (p, q)).
  • the sustain pulses are applied to the Y electrodes Yn and Ym by sequentially turning on the switches SW1-4.
  • the sustain pulses of the X electrodes Xn and Xm are generated by sequentially turning on the switches SW7-10.
  • the display line (for example, Ym) determined as the low-luminance display line by the gradation detection circuit 62 shown in FIG. 5, the number of sustain pulses (discharge cycles) in the subfield SF1-3 is It is set to 2, 4, and 8 times, respectively, which is smaller than the standard number.
  • a discharge inhibition period DIS for inhibiting discharge is set during the sustain period SUS.
  • the discharge inhibition period DIS is generated by clamping the Y electrode Ym to the voltage VsZ2 and then turning off the switch SW6m (Fig. 8 (r)).
  • the Y electrode Ym When the switch SW6m is turned off, the Y electrode Ym enters a high impedance state, and maintains the state (voltage) immediately before it is turned off regardless of the operation of the switch SW1-4. As a result, the voltage between the X electrode Xm and the Y electrode Ym does not reach the discharge start voltage. That is, the pixel PX of the corresponding display line is not lit during the discharge inhibition period DIS.
  • the discharge inhibition period DIS ends when the switch SW6m is turned on in synchronization with the switch SW3 being turned on.
  • the off period of switch SW6m is set to the same length as one discharge cycle.
  • the number of discharge cycles of the display line Ym is set to be smaller by one discharge cycle than the display line Yn.
  • the discharge inhibition period DIS is set at the end of the sustain period SUS.
  • the position of the discharge inhibition period DIS may be at the beginning or middle of the sustain period SUS. Furthermore, by changing the position of the DIS during the discharge inhibition period, it is possible to prevent false contours and improve the display image quality.
  • the switch SW6 (SW6n, SW6m) of the scan driver circuit SD used in the address period ADR is turned off during the sustain period SUS, so that the resonance pulse applied to the Y electrode is reduced.
  • the number (number of discharge cycles) can be easily adjusted for each display line. In other words, even when the resonance pulse force common to all Y electrodes is generated by the driver circuit DRV (Y), the number of discharge cycles in the sustain period SUS can be adjusted independently only by controlling the switch SW6. . Furthermore, since the number of discharge cycles can be adjusted simply by controlling the on / off state of the switch SW6, the logic for generating the discharge inhibition period DIS in the sustain control circuit 64 can be easily configured.
  • FIG. 9 shows the number of discharge cycles of each subfield in the low-luminance display line and the high-luminance display line.
  • a PDP with 10 display lines L1-10 is described.
  • the center display line L5-6 is connected to the discharge cell of at least one of red (R), green (G), and blue (B) in the second subfield SF4-8.
  • the upper and lower display lines LI-4 and L7-10 are high and bright using the second subfield SF4-8 for both red (R), green (G) and blue (B) discharge cells.
  • the display lines L1-4 and L7-10 have only a low luminance region L that uses only the first subfield SF1-3 (low luminance display line).
  • the number of discharge cycles when subfield SF1-8 is lit as shown in Fig. 3, [4, 8, 16, 32, 64, respectively] 128, 256, 512 [This is set (a preset standard number of times).
  • the number of discharge cycles when subfield SF1-3 shown in Fig. 3 is lit is 2, 4, and 8, which is half the standard number. Set each.
  • subfield SF1-3 having a discharge cycle number smaller than the standard discharge cycle number can be configured. Therefore, in the low-brightness display lines L1-4 and L7-10, the brightness of the dark image can be lowered and the image quality can be improved. In particular, as shown in FIG. 4, even when discharge occurs in the address period ADR and the reset period RST, the brightness of a dark image can be further reduced.
  • the brightness of the dark image can be lowered without changing the brightness of the bright image, and the image quality can be improved.
  • the effect of improving the image quality is significant for dark images that have a bright image power at a distant location.
  • FIG. 10 shows the number of discharge cycles in each subfield of the display line LI-10 in the second embodiment of the present invention.
  • the operation of the sustain control circuit 64 shown in FIG. 5 is different from that of the first embodiment.
  • Other operations and configurations are the same as those of the first embodiment (FIGS. 1 to 8).
  • the displayed image is the same as that in the first embodiment.
  • the sustain control circuit 64 (FIG. 5) has a function of detecting the positional relationship between the high luminance display line and the low luminance display line.
  • the sustain control circuit 64 displays the display lines L4, L7 adjacent to the display line L5-6.
  • the sustain control circuit 64 determines the number of sustain discharges in the first subfield SF1-3 in the second display lines L3 and L8 from the bright display line L5-6 to the display lines L4 and L7. Set to 2, 4, and 8 respectively.
  • the sustain control circuit 64 determines the number of sustain discharges of the first subfield SF1-3 in the display lines L1-2, L910 separated by three or more lines by the display lines L5, L6, and the number of display lines L3, L8. Set to 1, 2, and 4 respectively.
  • the number of sustain discharges in the first subfield SF1-3 in the low-brightness display line relatively close to the high-brightness display lines L5 and L6 is determined from the high-brightness display lines L5 and L6.
  • the number of sustain discharges in the first subfield SF1-3 in the low-brightness display lines L4 and L7 adjacent to the high-brightness display lines L5 and L6 is increased as compared with the first embodiment, and the standard It becomes possible to approach the number of times.
  • the pseudo line is a line that does not exist in the image data but is displayed on the PDP.
  • the pseudo line is generated when the image data has a special luminance pattern, and is not always generated.
  • FIG. 11 shows details of the Y dry YDRV and the X driver XDR V in the third embodiment of the present invention.
  • the scan driver circuit SD of the Y driver YDRV is different from the first embodiment.
  • the configuration excluding the scan driver circuit SD is the same as that of the first embodiment (FIGS. 1, 6, and 9).
  • the same elements as those described in the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.
  • the switch SW6 (SW6n, SW6m) of the scan driver circuit SD is configured by an IGBT instead of an nMOS transistor.
  • An IGBT is a bipolar transistor that incorporates MOSFE T in its gate. Unlike an nMOS transistor, an IGBT does not have a parasitic diode between the source and drain. For this reason, for example, even when the node ND2 rises to the voltage VsZ2 while the switch SW6m is off, the voltage of the Y electrode Ym does not change.
  • FIG. 12 shows details of operations in the address period ADR and the sustain period SUS shown in FIG. 3 in the third embodiment. Detailed description of the same operations as those in FIG. 8 is omitted.
  • This embodiment is different from the first embodiment in the method of setting the discharge inhibition period DIS (control method of the switch SW6 m) and the voltage of the Y electrode Ym in the discharge inhibition period DIS.
  • Other waveforms are the same as those in the first embodiment (FIG. 8).
  • the discharge inhibition period DIS is generated by turning off the switch SW6m after the Y electrode Ym is clamped to the voltage -VsZ2 and before the switch SW1 is turned on.
  • the switch SW6m is turned off, the Y electrode Ym enters the no-impedance state and maintains the state (voltage) immediately before turning off.
  • the voltage between the X electrode Xm and the Y electrode Ym does not reach the discharge start voltage.
  • the discharge inhibition period DIS ends when the switch SW6m is turned on in synchronization with the switch SW4 being turned on.
  • the position of the discharge inhibition period DIS may be at the beginning or middle of the sustain period SUS. Furthermore, by changing the position of the discharge inhibition period DIS, it is possible to prevent false contours and improve the quality of the display image.
  • the same effect as in the first embodiment described above can be obtained. Furthermore, the number of discharge cycles can be set to “0” in the sustain period SUS by forming the scan driver circuit SD with an IGBT having no parasitic diode between the source and drain. Therefore, by selecting whether or not the power to apply the address pulse is selected, the luminance of the low luminance display line can be further reduced.
  • FIG. 13 shows a fourth embodiment of the present invention.
  • an operation unit 66 is added to the first embodiment (FIG. 5).
  • the configuration excluding the operation unit 66 is the same as that of the first embodiment (FIGS. 1 to 9).
  • the same elements as those described in the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.
  • the operation unit 66 outputs a mode signal MD in response to an operation OP by the user. Specifically, the operation unit 66 outputs, for example, information output from the remote control as the mode signal MD in response to the remote control operation OP attached to the PDP device. For example, when the pseudo line described in the second embodiment is generated at the boundary between the high luminance display line and the low luminance display line, the user operates the remote control to discharge the low luminance display line. Stops the function that reduces the number of cycles. The operation unit 66 outputs a mode signal MD when the operation switch of the PDP device is directly operated by the user. A little.
  • the sustain control circuit 64 for example, has a function of setting the number of discharge cycles of the subfield SF1-3 in the low-luminance display line to be smaller than the standard number when receiving the low logic level mode signal MD. Enable. At this time, the operations shown in FIGS. 6 and 9 are performed. On the other hand, the sustain control circuit 64 performs the detection operation of the gradation detection circuit 62 (detection of whether or not to generate sustain discharge in the second subfield) when receiving the mode signal MD of a high logic level. Stops the above function regardless. At this time, the sustain control circuit 64 sets the number of discharge cycles in all the display lines including the low-luminance display line to the standard number as in the conventional case.
  • the sustain control circuit 64 always performs step S16 without performing the determination of step S14 of FIG.
  • the sustain control circuit 64 may determine that all display lines are high-luminance lines. Then, the number of discharge cycles in the first subfield SF1-3 is set to the standard number or less than the standard number according to the operation mode (mode signal), and the sustain control circuit 64 causes the X driver XDRV and Y driver to YDRV operation is controlled and an image is displayed on the PDP.
  • the same effect as in the first embodiment described above can be obtained. Furthermore, when the user views an image with a noticeable pseudo-line, the image quality can be improved by stopping the function of reducing the number of sustain discharges. In other words, the quality of the image displayed on the PDP can always be set optimally by enabling or disabling the above function according to the type of image.
  • the present invention is configured so that one field has eight subfields SF1.
  • the example applied to the plasma display panel consisting of 8 was described.
  • the invention is not limited to the powerful embodiments.
  • the present invention may be applied to a plasma display panel in which one field is composed of 10 or more subfields.
  • the number of subfield discharge cycles is not limited to 2 to the nth power (n is an integer of 2 or more).
  • the subfields SFl-8 (Fig. 3) in the field FLD need not be arranged sequentially.
  • subfield SF8 may be arranged near the center of field FLD.
  • a display line that uses only the first subfield SF1-2 may be treated as a low-luminance display line.
  • a display line that uses only the first subfield SF1-5 may be treated as a low-luminance display line.
  • the number of sustain discharges in the first subfield in the low-luminance display line is not limited to the numbers shown in FIG. 9 and FIG.
  • the sustain discharge in the first subfield SF1-3 is performed using three display lines L2-4 (or L7-9) adjacent to the high-luminance display lines L5, L6.
  • L2-4 or L7-9
  • L5 high-luminance display lines
  • An example of gradually decreasing the number of times was described.
  • the invention is not limited to the powerful embodiments.
  • the number of sustain discharges in the first subfield SF1-3 may be gradually reduced by using two display lines or four or more display lines.
  • one pixel PX force is constituted by three discharge cells (red (R), green (G), and blue (B)) has been described.
  • the invention is not limited to the powerful embodiments.
  • one pixel PX may be composed of four or more discharge cells.
  • one pixel PX force may be composed of discharge cells that generate colors other than red (R), green (G), and blue (B). Discharge cells that generate colors other than (G) and blue (B) may be included.
  • the second embodiment may be applied to the PDP device of the third or fourth embodiment.
  • the present invention can be applied to a plasma display panel and a plasma display device.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of Gas Discharge Display Tubes (AREA)

Abstract

Selon la présente invention, une zone d'affichage d'un écran plasma est formée d'une première sous-zone où les décharges d'entretien interviennent un nombre de fois relativement petit et d'une deuxième sous-zone où les décharges d'entretien interviennent un nombre de fois relativement grand. Un circuit de détection détecte pour chaque ligne s'il y a lieu de produire une décharge d'entretien dans la deuxième sous-zone. Un circuit de commande d'entretien produit une décharge d'entretien un nombre standard prédéfini de fois dans chaque sous-zone dans une ligne d'écran de haute luminance produisant une décharge d'entretien dans la deuxième sous-zone, et produit une décharge d'entretien un nombre de fois inférieur au nombre standard au moins dans l'une des premières sous-zones de la ligne d'écran de basse luminance ne produisant pas de décharge d'entretien dans la deuxième sous-zone. Il est ainsi possible d'abaisser la luminance d'une image sombre quand une image lumineuse et une image sombre sont mélangées dans un écran.
PCT/JP2006/321559 2006-10-27 2006-10-27 Écran plasma et son procédé de pilotage WO2008050454A1 (fr)

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Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10222123A (ja) * 1997-02-06 1998-08-21 Fujitsu General Ltd Ｐｄｐ表示装置
JPH10282929A (ja) * 1997-04-09 1998-10-23 Fujitsu Ltd 階調表示方法
JPH1165520A (ja) * 1997-08-21 1999-03-09 Victor Co Of Japan Ltd プラズマディスプレイパネル表示装置及びその駆動方法
JPH1165521A (ja) * 1997-08-20 1999-03-09 Fujitsu General Ltd ディスプレイの駆動方式
JPH1165519A (ja) * 1997-08-21 1999-03-09 Victor Co Of Japan Ltd プラズマディスプレイパネル表示装置及びその駆動方法
JPH11231825A (ja) * 1997-12-10 1999-08-27 Matsushita Electric Ind Co Ltd 明るさによるサブフィールド数調整可能な表示装置
WO2001056003A2 (fr) * 2000-01-26 2001-08-02 Thomson Licensing S.A. Procede de traitement d'images video en vue de l'affichage sur un dispositif d'affichage
JP2001306019A (ja) * 2000-04-18 2001-11-02 Pioneer Electronic Corp ディスプレイパネルの駆動方法
JP2006209078A (ja) * 2005-01-25 2006-08-10 Samsung Sdi Co Ltd プラズマ表示装置及びその駆動方法

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10222123A (ja) * 1997-02-06 1998-08-21 Fujitsu General Ltd Ｐｄｐ表示装置
JPH10282929A (ja) * 1997-04-09 1998-10-23 Fujitsu Ltd 階調表示方法
JPH1165521A (ja) * 1997-08-20 1999-03-09 Fujitsu General Ltd ディスプレイの駆動方式
JPH1165520A (ja) * 1997-08-21 1999-03-09 Victor Co Of Japan Ltd プラズマディスプレイパネル表示装置及びその駆動方法
JPH1165519A (ja) * 1997-08-21 1999-03-09 Victor Co Of Japan Ltd プラズマディスプレイパネル表示装置及びその駆動方法
JPH11231825A (ja) * 1997-12-10 1999-08-27 Matsushita Electric Ind Co Ltd 明るさによるサブフィールド数調整可能な表示装置
WO2001056003A2 (fr) * 2000-01-26 2001-08-02 Thomson Licensing S.A. Procede de traitement d'images video en vue de l'affichage sur un dispositif d'affichage
JP2001306019A (ja) * 2000-04-18 2001-11-02 Pioneer Electronic Corp ディスプレイパネルの駆動方法
JP2006209078A (ja) * 2005-01-25 2006-08-10 Samsung Sdi Co Ltd プラズマ表示装置及びその駆動方法

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