WO2008047409A1 - Procédé de pilotage d'écran plasma et appareil à écran plasma - Google Patents

Procédé de pilotage d'écran plasma et appareil à écran plasma Download PDF

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Publication number
WO2008047409A1
WO2008047409A1 PCT/JP2006/320655 JP2006320655W WO2008047409A1 WO 2008047409 A1 WO2008047409 A1 WO 2008047409A1 JP 2006320655 W JP2006320655 W JP 2006320655W WO 2008047409 A1 WO2008047409 A1 WO 2008047409A1
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WO
WIPO (PCT)
Prior art keywords
subfield
electrode
unnecessary
discharge
sustain
Prior art date
Application number
PCT/JP2006/320655
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English (en)
Japanese (ja)
Inventor
Takashi Sasaki
Akira Ohtsuka
Akihiro Takagi
Original Assignee
Hitachi Plasma Display Limited
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Publication date
Application filed by Hitachi Plasma Display Limited filed Critical Hitachi Plasma Display Limited
Priority to PCT/JP2006/320655 priority Critical patent/WO2008047409A1/fr
Publication of WO2008047409A1 publication Critical patent/WO2008047409A1/fr

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
    • G09G3/291—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes
    • G09G3/294—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes for lighting or sustain discharge
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2018—Display of intermediate tones by time modulation using two or more time intervals
    • G09G3/2022—Display of intermediate tones by time modulation using two or more time intervals using sub-frames
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
    • G09G3/296—Driving circuits for producing the waveforms applied to the driving electrodes
    • G09G3/2965—Driving circuits for producing the waveforms applied to the driving electrodes using inductors for energy recovery

Definitions

  • the present invention relates to a plasma display panel driving method and a plasma display device.
  • the present invention relates to a plasma display panel and a plasma display device.
  • a plasma display panel is formed by bonding two glass substrates together, and displays an image by generating discharge light in a space formed between the glass substrates.
  • the discharge cells corresponding to the pixels in the image are self-luminous, and are coated with phosphors that generate red, green, and blue visible light in response to ultraviolet rays generated by the discharge.
  • an X driver that drives the X electrode and a Y driver that drives the Y electrode are provided.
  • the X driver and Y driver apply pulses alternately to the X and Y electrodes.
  • the X driver and the Y driver apply pulses having opposite polarities to the X electrode and the Y electrode.
  • a field for displaying one screen is composed of a plurality of subfields.
  • the number of subfield discharges is sequentially set to 2 to the nth power (n is a positive integer).
  • n is a positive integer.
  • a multi-tone image is displayed by selectively lighting the discharge cells in accordance with the luminance of the image. For example, in a high luminance image (high gradation image), a subfield with a large number of discharges is selected, but in a low luminance image (low gradation image), a subfield with a large number of discharges is not selected.
  • a plasma display panel that detects the total amount of display data for each display line and adjusts the number of sustain discharges in the subfield according to the data amount has been proposed (for example, see Patent Document 1). .
  • Patent Document 1 Japanese Patent Laid-Open No. 9-68945
  • the Y driver when adjusting the number of sustain discharges in a subfield, the Y driver masks a pulse output to a predetermined Y electrode, and the X driver outputs a pulse output to a predetermined X electrode. Mask it. In this case, it is necessary to form a circuit for driving each X electrode independently. This increases the circuit scale and power consumption. Or, only the Y driver is capable of masking the pulse output to the specified Y electrode, and the X driver outputs a common pulse to all X electrodes. In this case, the X driver always outputs pulses to all X electrodes during the sustain period. Therefore, even if the number of discharges is reduced, the power consumption does not decrease.
  • An object of the present invention is to increase the number of gradations of an image with low brightness and improve image quality by utilizing a useless subfield that does not contribute to discharge. In particular, it is to improve image quality without increasing power consumption.
  • one field for displaying one screen of the plasma display panel is composed of a plurality of subfields.
  • the voltage of the first electrode is fixed.
  • the sustain discharge is selectively generated by the pulse applied to the second electrode, so that the image is displayed in multiple gradations.
  • the detection circuit detects whether or not there is an unnecessary subfield that does not require sustain discharge for each display line.
  • the display line is composed of pixels formed along the first electrode.
  • the sustain control circuit generates a sustain discharge of a predetermined number of times in each subfield in a display line in which no unnecessary subfield exists, and in a display line in which an unnecessary subfield exists, in at least one of the subfields.
  • the sustain discharge is generated a number less than the preset minimum number of sustain discharges.
  • the number of gradations of the low brightness image can be increased and the image quality can be improved.
  • the first electrode is fixed to a predetermined voltage without applying a pulse. This eliminates the need for a circuit for applying a pulse to the first electrode, and improves image quality without increasing power consumption.
  • FIG. 1 is an exploded perspective view showing a first embodiment of the present invention.
  • FIG. 2 is an exploded perspective view showing details of a main part of the PDP shown in FIG.
  • FIG. 3 is an explanatory diagram showing a configuration example of a field for displaying an image of one screen.
  • FIG. 4 is a waveform diagram showing an example of a discharge operation in the subfield shown in FIG.
  • FIG. 5 is a block diagram showing an outline of the circuit unit shown in FIG. 1.
  • FIG. 6 is a flowchart showing the operation of the control unit shown in FIG.
  • FIG. 7 is a circuit diagram showing details of the Y driver shown in FIG. 3.
  • FIG. 8 is a timing chart showing details of operations in the address period and the sustain period shown in FIG. 3.
  • FIG. 9 is an explanatory diagram showing the number of discharge cycles when there is an unnecessary subfield.
  • FIG. 10 is a characteristic diagram showing the relationship between the input gradation of the image data and the display gradation of the image displayed on the PDP in the methods (1), (2), and (5) shown in FIG.
  • FIG. 11 is a characteristic diagram showing the relationship between the input gradation of the image data and the display gradation of the image displayed on the PDP in the methods (3), (4), and (6) shown in FIG.
  • FIG. 12 is a circuit diagram showing details of a Y driver in a second embodiment of the present invention.
  • FIG. 13 is a timing chart showing details of operations in the address period and the sustain period shown in FIG. 3 in the second embodiment.
  • FIG. 1 shows a first embodiment of the present invention.
  • the plasma display device (hereinafter also referred to as “PDP device”) is a plasma display panel 10 having a square plate shape (hereinafter also referred to as “PDP”), an optical display provided on the image display surface 12 side (light output side) of the PDP 10. It is attached to the rear case 40 of the filter 20, the front case 30 arranged on the image display surface 12 side of the PDP10, the rear case 40 and the base chassis 50 arranged on the back side 14 of the PDP10, A circuit unit 60 for driving the PDP 10 and a double-sided adhesive sheet 70 for attaching the PDP 10 to the base chassis 50 are provided. Since the circuit part 60 is composed of a plurality of parts, it is indicated by a dashed box in the figure.
  • the PDP 10 includes a front substrate 16 (first substrate) that constitutes the image display surface 12 and a rear substrate 18 (second substrate) that faces the front substrate 16.
  • a discharge space (discharge cell) (not shown) is formed between the front substrate 16 and the rear substrate 18.
  • the front substrate 16 and the back substrate 18 are formed of, for example, a glass substrate.
  • the optical filter 20 is attached to a protective glass (not shown) attached to the opening 32 of the front housing 30.
  • FIG. 2 shows details of a main part of the PDP 10 shown in FIG.
  • the front substrate 16 has X electrodes 16b (first electrode, sustain electrode) and Y electrodes 16c (first electrode and sustain electrode) formed in parallel and alternately on the glass substrate 16a (lower side in the figure) in order to generate discharge repeatedly.
  • the X electrode 16b and the Y electrode 16c are composed of a bus electrode BE (electrode line) extending in the horizontal direction in the figure and a transparent electrode TE connected to the bus electrode BE.
  • the electrodes 16b and 16c are covered with a dielectric layer 16d, and the surface of the dielectric layer 16d is covered with a protective layer 16e such as MgO.
  • the rear substrate 18 facing the front substrate 16 via the discharge space DS has address electrodes 18b (third electrodes) formed in parallel to each other on the glass base material 18a.
  • the address electrode 18b is arranged in a direction orthogonal to the bus electrode BE.
  • the address electrode 18b is covered with a dielectric layer 18c.
  • partition walls (ribs) 18d are formed at positions corresponding to between the adjacent address electrodes 18b.
  • the side wall of the discharge cell is constituted by the barrier rib 18d.
  • visible light of red (R), green (G), and blue (B) is emitted on the side surface of the partition wall 18d and on the dielectric layer 18c between the partition walls 18d adjacent to each other by being excited by ultraviolet rays.
  • the resulting phosphors 18e, 18f, and 18g are applied respectively.
  • One discharge cell (one color pixel) of the PDP 10 is formed in a region including a pair of transparent electrodes TE in a region surrounded by a pair of adjacent barrier ribs 18d. That is, the discharge cell is formed at the intersection of the electrodes 16b and 16c and the electrode 18b.
  • PDP10 In order to display an image, discharge cells are arranged in a matrix and a plurality of types of discharge cells that generate light of different colors are alternately arranged. Note that one pixel PX shown in FIG. 5 described later is composed of three discharge cells that generate red, blue, and green light. Although not particularly shown, a display line is constituted by discharge cells formed along the electrodes 16b and 16c.
  • the PDP 10 is configured by bonding the front substrate 16 and the rear substrate 18 so that the protective layer 16e and the partition wall 18d are in contact with each other and enclosing a discharge gas such as Ne or Xe.
  • the bus electrode BE is connected to the Y driver YDRV shown in FIG.
  • the address electrode 18b is connected to the address driver ADRV shown in FIG.
  • FIG. 3 shows a configuration example of the field FLD for displaying an image of one screen.
  • One Fino Red FLD has a length of 1Z60 seconds (about 16.7 ms), and is composed of, for example, 8 subfields SF (SF1-SF8).
  • Each subfield SF includes a reset period RST, an address period ADR, a sustain period SUS, and an erase period ERS.
  • the erasing period ERS is defined as being included in the sustaining period SUS because it is a period for generating a discharge for erasing the wall charges of only the lit discharge cells.
  • the wall charge is, for example, a brass charge and a minus charge accumulated on the MgO layer 16e shown in FIG. 2 in each discharge cell.
  • the reset period RST, address period ADR, and erase period ERS have the same length regardless of the subfield SF.
  • the sustain period SUS length varies depending on the subfield SF and depends on the number of discharges (luminance) of the discharge cell. For this reason, it is possible to display an image in multiple gradations by changing the combination of the subfields SF to be lit.
  • the number of discharge cycles (number of sustain discharges) of subfield SF1-8 is 4, 8, 16, 32, 64, 128, respectively, without the unnecessary subfield described later. 256, 512.
  • the upper subfields SF8 and SF7 are used for high luminance (high gradation) images, and the upper subfields SF8 and SF7 are not used for low luminance (low gradation) images.
  • the number of discharge cycles indicates the number of sustain pulses applied to the X electrode 16b (or Y electrode 16c).
  • the discharge cell is discharged twice during one discharge cycle CYC (star in the figure).
  • FIG. 4 shows an example of the discharge operation of subfield SF shown in FIG. The star in the figure indicates the occurrence of discharge.
  • sustain electrode X (X electrode 16b) is fixed to ground voltage GND.
  • a positive write voltage (write blunt wave) that rises slowly is applied to the scan electrode Y (Y electrode 16c) (FIG. 4 (a)).
  • a slowly decreasing adjustment voltage (adjusted blunt wave) is applied to the scan electrode Y (Fig. 4 (b)). This reduces the amount of wall charges and makes the wall charges of all discharge cells equal.
  • the adjustment voltage is higher than the voltage ⁇ Vs.
  • a negative scan pulse is applied to the scan electrode Y, and a positive address pulse (voltage Vsa) is applied to the address electrode Al (18b) corresponding to the discharge cell that is lit (FIG. 4 ( c)).
  • the discharge cell selected by the address pulse is temporarily discharged.
  • the second address pulse shown in the waveform of address electrode A1 is applied to select the discharge cell for the next display line (Fig. 4 (d)).
  • the discharge in the address period ADR is not included in the discharge cycle.
  • a high-voltage pre-erase pulse is applied to the scan electrode Y, and discharge occurs (Fig. 4 (g)).
  • wall charges are accumulated in the sustain electrode X and the scan electrode Y.
  • a negative erase pulse having a voltage higher than the voltage ⁇ Vs is applied to the scan electrode Y (FIG. 4 (h)).
  • the discharge in the erase period ERS is not included in the discharge cycle. This completes one subfield period SF.
  • the number of discharge cycles is “3” (six discharges of sustain period SUS), which is the same as the number of pulses of scan electrode Y.
  • FIG. 5 shows an outline of the circuit unit 60 shown in FIG.
  • the circuit unit 60 includes a Y-drino YDRV (first drive circuit) that selectively applies a pulse to the Y electrode 16c, an address driver ADRV (second drive circuit) that selectively applies a pulse to the address electrode 18b, and a driver YDRV. It has a control unit CNT that controls the operation of AD RV and a power supply unit PWR! /.
  • Drivers YDRV and ADRV operate as a drive unit for driving PDP10. In the present invention, a driver for applying a pulse to the X electrode 16b is not formed.
  • the X electrode 16b is connected to the ground line GND.
  • the control unit CNT includes a gradation detection circuit 62 and a sustain control circuit 64.
  • the image data RO-9, GO-9, and BO-9 are 10-bit data for displaying red, green, and blue, respectively. Input sequentially.
  • 1024 luminances (1024 gradations) are represented according to the bit values of the image data R 0-9, GO-9, and B0-9.
  • a bit with a small number (low order bit) has a high weight for a bit with a small number (high order bit) with a small weight.
  • the gradation detection circuit 62 obtains a subfield SF to be used for displaying an image for each pixel based on the image data R0-9, GO-9, and B0-9.
  • the subfield SF to be lit for each pixel PX is obtained by calculation.
  • a display line including a high luminance (high gradation) image and a display line not including a high luminance image are detected.
  • the display line is configured by the pixels PX arranged along the electrodes 16b and 16c.
  • one pixel PX includes three discharge cells that generate red, blue, and green light. Each pixel PX is composed of 3 or more discharge cells.
  • a display line including a high-luminance image is a display line having pixels that display an image by turning on the subfield SF8 (or SF7-8).
  • subfield SF8 (or SF7-8) is an unnecessary subfield that does not require sustain discharge (lighting) in the sustain period SUS.
  • the detection circuit 62 outputs information indicating the presence or absence of unnecessary subfields to the sustain control circuit 64 for each display line.
  • the sustain control circuit 64 has no unnecessary subfields. In the display line, the sustain control circuit 64 generates a sustain discharge of a preset number of times in each subfield SF1-8. Outputs control signal YCNT and outputs control signal ACNT to driver ADRV. At this time, the sustain control circuit 64 outputs a control signal YCNT to display an image of 256 gradations corresponding to the upper 8-bit image data R2-9, G2-9, and B2-9.
  • the control signal YCNT includes switch control signals SW1, SW2, SW3, SW4, SW5n, SW5m, SW6n, and SW6m shown in FIG. 8 to be described later.
  • the control signal ACNT is a timing signal for generating an address pulse.
  • an image can be displayed without using the upper bits R9, G9, and B9 (or R8-9, G8-9, and B8-9) of the image data.
  • the lower bits instead of the upper bits, the number of gradations of a dark image can be increased and the image quality can be improved.
  • the power supply unit PWR generates power supply voltages Vsc, Vs, —Vs, and Vsa supplied to the drivers YDRV and ADRV.
  • Y driver YDRV has a scan driver circuit SD for each Y electrode 16c. As a result, a desired number of sustain pulses can be selectively applied to each Y electrode 16c.
  • FIG. 6 shows the operation of the control unit CNT shown in FIG. In FIG. 6, only the control related to the sustain period SUS is shown, and the control related to the address period ADR is not shown.
  • the flow shown in Fig. 6 may be realized by controlling a hard wafer by software, which may be realized only by hardware.
  • the gradation detection circuit 62 receives image data R0-9, GO-9, and B0-9 for one display line.
  • the control unit CNT shown in FIG. 5 continuously receives image data of a plurality of display lines and a plurality of screens. Therefore, the control unit CNT performs the flow of FIG. 6 every time it receives image data of one display line.
  • the gradation detection circuit 62 determines, for each pixel PX, a subfield SF that is lit to display an image based on the image data of one display line.
  • the upper subfields SF8 and SF7 are used in the pixel PX that displays an image with high luminance. That is, the gradation detection circuit 62 detects whether or not there is a force in which an unnecessary subfield SF that does not require sustain discharge exists for each display line.
  • the unnecessary subfield SF is a subfield in which the sustain discharge is detected to be unnecessary in all the discharge cells (red, blue, and green) of one pixel PX.
  • step S14 the sustain control circuit 64 determines, based on information from the gradation detection circuit 62, whether or not there is an unnecessary subfield that is not lit to display an image. . If there is no unnecessary subfield, in step S16, the sustain control circuit 64 controls the operation of the driver YDRV to generate a preset number of sustain discharges using the subfield SF1-8. To do. The number of discharges of each subfield SF1-8 set by this operation is a preset standard number of discharge cycles. The operation in step S16 is, for example, an operation for displaying display lines L2 and L3 in FIG.
  • step S18 the sustain control circuit 64 determines at least one of the subfields SF1-8 including the unnecessary subfield from the preset minimum number of sustain discharges. Assign to a subfield that generates a small number of sustain discharges.
  • the minimum number of times of this embodiment is four discharge cycles of the lowest subfield SF1, as shown in FIG.
  • the minimum number of discharge cycles is set to 2 discharge cycles or 1 discharge cycle.
  • the sustain control circuit 64 uses the subfield SF1-8 to control the operation of the driver YDRV in order to generate a newly set number of sustain discharges.
  • the operation in step S18 is, for example, an operation for displaying display lines Ll and L4 in FIG.
  • FIG. 7 shows details of the Y driver YDRV shown in FIG.
  • Y driver YDRV has driver circuit DRV (Y) and scan driver circuit SD.
  • the switches SW1, SW2, SW3, SW4, SW6 (SW6n, SW6m) shown in the figure are composed of, for example, nMOS transistors (MOSFETs). As shown in the figure, each nMOS transistor has a parasitic diode that connects between the source and drain.
  • the switch SW5 (SW5n, SW5m) is configured by, for example, an IGBT (Insulated Gate Bipolar Transistor).
  • the X electrode (Xn, Xm, etc.) is connected to the ground line G2 (GND).
  • Capacitor C p indicates the capacitance of PDP10.
  • the driver circuit DRV (Y) includes a coin La, switches SW1, SW2, SW3, SW4 and a diode.
  • Coil La and switch SW1–4 operate as a resonance circuit to generate a resonance pulse on the Y electrode (Yn, Ym, etc.).
  • the resonant pulse is a signal common to all Y electrodes.
  • Switches SW1–4 are turned on when a high logic level switch control signal is received, and turned off when a low logic level switch control signal is received.
  • the drain of the switch SW1 and the source of the switch SW3 are connected to the ground line G1.
  • the source of the switch SW1 is connected to the node ND1, which is one end of the coil La, via a forward-connected diode.
  • the drain of switch SW3 is connected to node ND1 through a diode connected in the reverse direction.
  • Node ND1 is connected to power supplies Vs and -Vs via diodes connected in the opposite direction.
  • Switch SW2 connects the drain to power source Vs and connects the source to node ND2, which is the other end of coil La.
  • the switch SW4 has a source connected to the power supply Vs and a drain connected to the node ND2.
  • the node ND2 is connected to the scan driver circuit SD.
  • Each scan driver circuit SD has a switch SW5 (SW5n, SW5m, etc.) and a switch SW6 (SW6n, SW6m, etc.) arranged in series between the power supply Vsc and the node ND2.
  • the switch SW5 the drain is connected to the power supply Vsc via a diode connected in the forward direction, and the source is connected to the Y electrode (Yn, Ym, etc.).
  • the drain of the switch SW5 is connected to the node ND2 via the capacitor C1.
  • Switch SW6 has its source connected to node ND2 and its drain connected to the Y electrode.
  • FIG. 8 shows details of the operation of the address period ADR and the sustain period SUS shown in FIG. Show.
  • a signal for controlling on / off of the switch SW1-6 is referred to as a switch control signal SW1-6.
  • Switch SW1-6 is turned on during the high logic level of switch control signal SW1-6, and is turned off during the low logic level of switch control signal SW1-6.
  • the star in the figure indicates the occurrence of discharge.
  • the switch SW4 In the address period ADR, the switch SW4 is always on (FIG. 8 (a)). Therefore, the node ND2 shown in Fig. 7 is set to voltage-Vs.
  • the X electrodes Xn and Xm are fixed to the ground voltage GND (Fig. 8 (b, c)).
  • a period not perform selective operation of the pixel PX switch SW5n, SW5M is turned on, switch SW6n, SW6M is turned off (FIG. 8 (d, e)) 0 Therefore, Y electrode Yn, the Ym, The voltage is set to Vsc (Fig. 8 (f, g)).
  • the corresponding switch SW5n (or SW5m) is turned off and the corresponding switch SW6n (or SW6m) is turned on in synchronization with the driving of the address electrode A1.
  • the Y electrode Yn (or Ym) is temporarily set to voltage-Vs (Fig. 8 (h, i)). Then, a scanning operation for selecting the pixel PX to be lit is performed for each display line.
  • the ground line G1 is connected to the capacitor Cp via the switch SW1, the coil La, the switch SW6n, SW6m, and the Y electrodes Yn, Ym.
  • the voltages of the Y electrodes Yn and Ym rise due to the LC resonance effect of the coil La and the capacitor Cp.
  • the switch SW2 is turned on, the voltage of the Y electrode Yn, ⁇ m is clamped to the voltage Vs (Fig. 8 (1, m)).
  • the switch SW3 when the switch SW3 is turned on, the capacitor Cp is connected to the ground line G1 via the Y electrodes Yn and Ym, the switches SW6n and SW6m, the coil La, and the switch SW3.
  • the voltage of the Y electrodes Yn and Ym drops due to the LC resonance effect of the coil La and the capacitor Cp.
  • the switch SW4 when the switch SW4 is turned on, the voltages of the Y electrodes Yn and Ym are clamped to the voltage Vs (FIG. 8 (n, o)). In this way, the sustain pulses are applied to the Y electrodes Yn and Ym by sequentially turning on the switches SW1-4.
  • the sustain pulse (discharge cycle) is detected in at least one of the subfields SF1-8.
  • the number is set to be smaller than the display line (for example, Yn), which has unnecessary subfields.
  • the discharge inhibition period DIS for inhibiting discharge is set during the sustain period SUS. Discharge inhibition period DIS is generated by turning off switch SW6m after clamping Y electrode Ym to voltage Vs (Fig. 8 (p)).
  • the Y electrode Ym When the switch SW6m is turned off, the Y electrode Ym enters a high impedance state, and maintains the state (voltage) immediately before turning off regardless of the operation of the switch SW1-4. As a result, the voltage between the X electrode Xm and the Y electrode Ym does not reach the discharge start voltage. That is, the pixel PX of the corresponding display line is not lit during the discharge inhibition period DIS.
  • the discharge inhibition period DIS ends when the switch SW6m is turned on in synchronization with the switch SW3 being turned on.
  • the off period of switch SW6m is set to the same length as one discharge cycle.
  • the number of discharge cycles of the display line Ym is set to be smaller by one discharge cycle than the display line Yn.
  • the discharge inhibition period DIS is set at the end of the sustain period SUS.
  • the position of the discharge inhibition period DIS may be at the beginning or middle of the sustain period SUS. Furthermore, by changing the position of the DIS during the discharge inhibition period, it is possible to prevent false contours and improve the display image quality.
  • the switch SW6 (SW6n, SW6m) of the scan driver circuit SD used in the address period ADR is turned off during the sustain period SUS, so that the resonance pulse applied to the Y electrode is reduced.
  • the number (number of discharge cycles) can be easily adjusted for each display line. In other words, even when the resonance pulse force common to all Y electrodes is generated by the driver circuit DRV (Y), the number of discharge cycles in the sustain period SUS can be adjusted independently only by controlling the switch SW6. .
  • FIG. 9 shows the number of discharge cycles in each subfield when there is an unnecessary subfield.
  • a PDP with four display lines L1-4 is described.
  • the center display line L2-3 has a high brightness area H (high gradation area), and the upper and lower display lines Ll and L4 have a low brightness area "low gradation area”.
  • the display lines Ll and L4 have unnecessary subfields.
  • six control methods from (1) to (6) are shown.
  • Techniques (1) and (2) show examples in which the unnecessary subfield is only the subfield SF8.
  • Methods (3) and (4) show examples when the unnecessary subfield is subfield SF7-8.
  • Method (5) shows an example where the unnecessary subfield is only subfield SF6.
  • Method (6) shows an example where the unnecessary subfields are subfields SF6, 7, and 8.
  • the control unit CNT shown in FIG. 5 performs discharge control of unnecessary subfields using at least one of the methods (1) and (6).
  • the number of discharge cycles of subfield SF1-8 is 4, 8, 16 as shown in FIG. , 32, 64, 128, 256, 512 (preset standard values).
  • the number of discharge cycles of subfield SF1-7 shown in FIG. 3 is set to half of the standard value, and the number of discharge cycles of unnecessary subfield SF8 is set to 256.
  • the number of discharge cycles of subfield SF1-7 shown in FIG. 3 is assigned to subfield SF2-8, and the number of discharge cycles of subfield SF1 is set to 2.
  • the discharge control for display line L2-3 that does not have unnecessary subfields is the same as in method (1).
  • unnecessary lines are displayed on display lines Ll and L4.
  • the sustain count of “2” less than the minimum count “4” in any of the subfields SF are generated.
  • the luminance of the pixel where the subfield SF8 is not used is less than half that when the subfield SF8 is used. That is, in the present invention, the luminance is low, and the number of gradations of the image ( ⁇ , image) can be increased.
  • the number of discharge cycles in subfield SF1-7 shown in Fig. 3 is set to 1/4 of the standard value for display lines Ll and L4 with unnecessary subfields.
  • the number of discharge cycles in subfield SF1-6 shown in FIG. 3 is assigned to subfield SF3-8, and the number of discharge cycles in subfield SF1-2 is set to 1 and 2, respectively.
  • the number of gradations of the image can be increased to 256 with the conventional 64-gradation power on the display lines Ll and L4, which do not have a high-luminance region. It can be further improved.
  • the discharge electrode of one time is the voltage of the Y electrode (for example, Ym shown in FIG. 8) first during the sustain period SUS. After setting to Vs, this can be achieved by keeping switch SW6m off. That is, in this case, one discharge cycle can be realized by the first discharge and the last discharge of the sustain period SUS.
  • the same effect as method (3) can be obtained by setting the number of discharge cycles of unnecessary subfield SF7-8 to 1 and 2 on display lines Ll and L4, respectively.
  • the number of discharge cycles of unnecessary subfield SF6 is set to 2 in display lines Ll and L4.
  • the intermediate gradation subfield for example, SF6
  • the number of gradations of the image can be increased, and the contrast of an image with low luminance can be improved.
  • the number of discharge cycles of the unnecessary subfield SF6-8 is set to 0, 1, and 2, respectively.
  • switch SW6 of scan driver circuit SD is set to nMOS transistor.
  • the voltage of the Y electrode changes to the voltage Vs following the change to the voltage Vs of the node ND2 by the parasitic diode of the switch SW6. Therefore, one discharge cycle occurs even when the discharge inhibition period DIS is set for the entire sustain period SUS.
  • the brightness of the image is less than half of the maximum brightness.
  • human eyes are more sensitive to changes in brightness than images with relatively low brightness. For this reason, increasing the number of gradations of an image with low luminance has a greater effect of improving the image quality than increasing the number of gradations of an image with high luminance.
  • FIG. 10 shows the relationship between the input gradation of the image data in the methods (1), (2), and (5) shown in FIG. 9 and the display gradation (number of discharge cycles) of the image displayed on the PDP. Showing the relationship.
  • FIG. 10 shows a case where the methods (1), (2), and (5) shown in FIG. 9 are applied.
  • the display gradation power increases by 4 each time the image data RO-9, GO9, and BO-9 increase in value power. Specifically, it is set as a value power display gradation in which the lower 2 bits of image data RO-9, GO-9, and B0-9 are reset to "00". This is equivalent to displaying a 256-level image using the upper 8-bit image data R2-9, G2-9, and B2-9.
  • the display gradation increases by two every time the value of image data R0-9, G0-9, and B0-9 increases by two.
  • the minimum unit for quantizing the display gradation is “2”, which is compared with the display line L2-3 having no unnecessary subfields. Is set to a small value.
  • the display gradation of the display line having the unnecessary subfield is changed to the display gradation of the display line having no unnecessary subfield. Can be doubled.
  • FIG. 11 shows the relationship between the input gradation of the image data in the methods (3), (4), and (6) shown in FIG. 9 and the display gradation (number of discharge cycles) of the image displayed on the PDP. Showing the relationship.
  • FIG. 11 shows a case where the methods (3), (4), and (6) shown in FIG. 9 are used.
  • the display gradation on display line L2-3 is the same as in Fig. 10.
  • the display gradation increases by 1 each time the value of image data RO-9, GO-9, BO-9 increases. That is, the values of the image data R0-9, GO-9, and B0-9 are set as display gradations as they are.
  • the display gradation of the display line having the unnecessary subfield is changed to the display level of the display line having no unnecessary subfield. It can be increased 4 times compared to the key.
  • the unnecessary subfield when an unnecessary subfield is present, the unnecessary subfield is used to use a subcycle having a number of discharge cycles that is less than a preset minimum number of discharge cycles. You can configure fields. Therefore, when a high-brightness image and a low-brightness image coexist, the number of gradations of the relatively low-brightness image can be increased compared to the conventional case, and the image quality of the low-brightness image can be improved.
  • the X electrode is fixed to the ground voltage GND and is not driven. By realizing the above-described operation without driving the X electrode, it is possible to improve the image quality without increasing the power consumption. Furthermore, the cost of the plasma display panel and the plasma display device can be reduced because a driver circuit for driving the X electrode is not required.
  • FIG. 12 shows details of the Y dryno YDRV in the second embodiment of the present invention.
  • the scan driver circuit SD of the Y driver YDRV is different from the first embodiment.
  • the configuration excluding the scan driver circuit SD is the same as that of the first embodiment (FIGS. 1 to 6).
  • the same elements as those described in the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.
  • the switch SW6 (SW6n, SW6m) of the scan driver circuit SD is configured by an IGBT instead of an nMOS transistor.
  • An IGBT is a bipolar transistor that incorporates MOSFE T in its gate. Unlike an nMOS transistor, an IGBT does not have a parasitic diode between the source and drain. For this reason, for example, when the node ND2 rises to the voltage Vs while the switch SW6m is off, the voltage of the Y electrode Ym does not change.
  • FIG. 13 shows details of operations in the address period ADR and the sustain period SUS shown in FIG. Detailed description of the same operations as those in FIG. 8 described above will be omitted.
  • This embodiment differs from the first embodiment in the method of setting the discharge inhibition period DIS (control method of the switch SW6m) and the voltage of the Y electrode Ym in the discharge inhibition period DIS.
  • Other waveforms are the same as those in the first embodiment (FIG. 8).
  • the discharge inhibition period DIS is generated by turning off the switch SW6m after clamping the Y electrode Ym to the voltage Vs and before turning on the switch SW1.
  • the switch SW6m When the switch SW6m is turned off, the Y electrode Ym enters a high impedance state and maintains the state (voltage) immediately before turning off. As a result, the voltage between the X electrode Xm and the Y electrode Ym does not reach the discharge start voltage.
  • Discharge prohibited period DIS ends when switch SW6m is turned on in synchronization with switch SW4 being turned on.
  • the position of the discharge inhibition period DIS may be at the beginning or middle of the sustain period SUS. Furthermore, by changing the position of the discharge inhibition period DIS, it is possible to prevent false contours and improve the quality of the display image.
  • the number of discharge cycles can be set to “0” in the sustain period SUS by forming the scan driver circuit SD with an IGBT having no parasitic diode between the source and drain. Therefore, the number of gradations of an image with low brightness (dark image) can be further increased by selecting whether or not to apply an address pulse.
  • the present invention is configured so that one field has eight subfields SF1.
  • the example applied to the plasma display panel consisting of 8 was described.
  • the invention is not limited to the powerful embodiments.
  • the present invention may be applied to a plasma display panel in which one field is composed of 10 or more subfields.
  • the number of subfield discharge cycles is not limited to 2 to the nth power (n is an integer of 2 or more).
  • the subfields SFl-8 (Fig. 3) in the field FLD need not be arranged sequentially.
  • subfield SF8 may be arranged near the center of field FLD.
  • the present invention can be applied to a plasma display panel and a plasma display device.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of Gas Discharge Display Tubes (AREA)

Abstract

La présente invention concerne la recherche d'un accroissement des gradations concernant une image à faible luminance en cas de mélange d'image haute luminance et d'image basse luminance, ce façon à atteindre une amélioration de la qualité de l'image sans solliciter d'augmentation de consommation électrique. Un champ à afficher à l'écran plasma se décompose en une multitude de sous-champs. À cet effet, une première électrode est bloquée à une tension donnée, l'induction de la décharge sélective d'entretien étant le fait uniquement d'impulsions appliquées à une deuxième électrode. On obtient ainsi un affichage à plusieurs tons de l'image. Un circuit de détection recherche tout sous-champ non désiré ne nécessitant aucune décharge d'entretien pour chaque ligne d'affichage. En l'absence de tout sous-champ non désiré, un circuit de commande d'entretien induit un nombre prédéfini de décharges d'entretien dans chacun des sous-champs. En présence de sous-champ non désiré, le circuit de commande d'entretien induit des décharges d'entretien en nombre inférieur au nombre minimal prédéfini de décharges d'entretien dans l'un au moins des sous-champs.
PCT/JP2006/320655 2006-10-17 2006-10-17 Procédé de pilotage d'écran plasma et appareil à écran plasma WO2008047409A1 (fr)

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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10222123A (ja) * 1997-02-06 1998-08-21 Fujitsu General Ltd Ｐｄｐ表示装置
JPH10282929A (ja) * 1997-04-09 1998-10-23 Fujitsu Ltd 階調表示方法
JPH1165519A (ja) * 1997-08-21 1999-03-09 Victor Co Of Japan Ltd プラズマディスプレイパネル表示装置及びその駆動方法
JPH1165520A (ja) * 1997-08-21 1999-03-09 Victor Co Of Japan Ltd プラズマディスプレイパネル表示装置及びその駆動方法
JPH1165521A (ja) * 1997-08-20 1999-03-09 Fujitsu General Ltd ディスプレイの駆動方式
JPH11231825A (ja) * 1997-12-10 1999-08-27 Matsushita Electric Ind Co Ltd 明るさによるサブフィールド数調整可能な表示装置
JP2001306019A (ja) * 2000-04-18 2001-11-02 Pioneer Electronic Corp ディスプレイパネルの駆動方法
JP2006209078A (ja) * 2005-01-25 2006-08-10 Samsung Sdi Co Ltd プラズマ表示装置及びその駆動方法

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10222123A (ja) * 1997-02-06 1998-08-21 Fujitsu General Ltd Ｐｄｐ表示装置
JPH10282929A (ja) * 1997-04-09 1998-10-23 Fujitsu Ltd 階調表示方法
JPH1165521A (ja) * 1997-08-20 1999-03-09 Fujitsu General Ltd ディスプレイの駆動方式
JPH1165519A (ja) * 1997-08-21 1999-03-09 Victor Co Of Japan Ltd プラズマディスプレイパネル表示装置及びその駆動方法
JPH1165520A (ja) * 1997-08-21 1999-03-09 Victor Co Of Japan Ltd プラズマディスプレイパネル表示装置及びその駆動方法
JPH11231825A (ja) * 1997-12-10 1999-08-27 Matsushita Electric Ind Co Ltd 明るさによるサブフィールド数調整可能な表示装置
JP2001306019A (ja) * 2000-04-18 2001-11-02 Pioneer Electronic Corp ディスプレイパネルの駆動方法
JP2006209078A (ja) * 2005-01-25 2006-08-10 Samsung Sdi Co Ltd プラズマ表示装置及びその駆動方法

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