WO2008051300A2 - Dispositifs à nano-émission, circuits intégrés utilisant des dispositifs à nano-émission, et procédés associés - Google Patents

Dispositifs à nano-émission, circuits intégrés utilisant des dispositifs à nano-émission, et procédés associés Download PDF

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Publication number
WO2008051300A2
WO2008051300A2 PCT/US2007/009829 US2007009829W WO2008051300A2 WO 2008051300 A2 WO2008051300 A2 WO 2008051300A2 US 2007009829 W US2007009829 W US 2007009829W WO 2008051300 A2 WO2008051300 A2 WO 2008051300A2
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WO
WIPO (PCT)
Prior art keywords
terminal
channel cavity
gate
emitter
nano emission
Prior art date
Application number
PCT/US2007/009829
Other languages
English (en)
Other versions
WO2008051300A3 (fr
Inventor
David Summers
Phil Brown
Original Assignee
Kanzen Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kanzen Inc. filed Critical Kanzen Inc.
Publication of WO2008051300A2 publication Critical patent/WO2008051300A2/fr
Publication of WO2008051300A3 publication Critical patent/WO2008051300A3/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y20/00—Nanooptics, e.g. quantum optics or photonic crystals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J21/00—Vacuum tubes
    • H01J21/02—Tubes with a single discharge path
    • H01J21/06—Tubes with a single discharge path having electrostatic control means only
    • H01J21/10—Tubes with a single discharge path having electrostatic control means only with one or more immovable internal control electrodes, e.g. triode, pentode, octode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs

Definitions

  • FIG. 2(b) is an end cross section view of the N-type nano emission transistor of FIG. 2(a);
  • FIG. 7 is a flow chart of a method of fabricating a nano emission device in accordance with an embodiment of the present invention.
  • FIG. 12 is a cross section view of a diode using nano emission technology in accordance with an embodiment of the present invention.
  • FIG. 13 is an illustration of schematic symbols for various nano emission devices in accordance with an embodiment of the present invention
  • FIG. 14 is a schematic of various components using nano emission devices in accordance with an embodiment of the present invention
  • FIG. 19 is a cross section view of a nano emission transistor in accordance with another embodiment of the present invention.
  • FIG. 23 is a side view of a nano emission device having a heating element in accordance with an embodiment of the present invention.
  • the device includes a gate terminal having at least two gate portions 106 disposed at opposite sides of the channel cavity between the first position and the second position.
  • the gate portions are separated from the channel cavity by interposed portions 114, 116 of the insulating body.
  • the channel cavity can be evacuated, but absolute vacuum is not required. For example, vacuum levels of about 10 " 2 torr (1.3 pascals) can typically be achieved in semiconductor processing and packaging and are expected to prove adequate.
  • the channel cavity can be filled with a gas.
  • a gas which provides similar properties as vacuum with respect to the emission and flow of electrons may be used.
  • Noble gasses, such as argon, neon, krypton, xenon, and radon may prove useful.
  • smaller scale devices can provide for smaller switching voltages.
  • field emission may occur when a voltage gradient in excess of 10 9 V/m is present.
  • voltage gradients can be enhanced by geometry, such as pointed tips. Surface irregularities may also provide for enhancement of field emission.
  • Geometric and other enhancement factors can provide for field emission at voltage gradients 10 to 100, or even 1000 times lower than 10 9 V/m. Accordingly, for emitter to collector gaps on the order of 1 micrometer or less, current flow may occur at voltages of less than 200 volts, less than 100 volts, or even less than 50 volts.
  • the P-type device gate can include a portion 2209 that extends into the insulating extension 2224, although this is not essential. Extending the gate into the insulating extension may help to increase the efficiency of the gate in affecting electron flow.
  • FIG. 13 illustrates schematic symbols for an N- type nano emission transistor 1302, P-type nano emission transistor 1304, a nano emission diode 1306, and a bidirectional nano emission switch 1308. These symbols, while schematic, are suggestive of a particular structure of nano emission devices discussed herein. It will be understood, however, that devices using any of the various structures illustrated, described, or suggested herein for the individual nano emission transistors may be used in implementing the logic devices.
  • Nano emission devices can be combined into a variety of other logic devices, such as AND, OR, XOR, XAND, adders, encoders/multiplexers, decoders/demultiplexers, latches, flip flops, shift registers, counters, complex logic functions, processors, memory arrays, switching systems and the like. Nano emission devices can also be used to construct components such as linear circuits, amplifiers, logarithmic amplifiers, voltage comparators, analog multipliers, mixers, analog to digital converters, digital to analog converters, voltage multipliers, power conditioners and the like.
  • the inverter 1408 (FIG. 14) can be biased (e.g., with negative feedback) to operate as a linear amplifier.
  • Complex electronic circuits can be constructed from nano emission devices similarly as is currently done using semiconductor transistors.
  • Patterning can be performed by lithographic processes. For example, a layer of material can be deposited, a photoresist layer applied and exposed through a mask, exposed (positive photoresist) or unexposed (negative photoresist) portions of the photoresist washed away by a developer solution to reveal portions of the material layer, and the revealed portions of the material removed using etching or other processing.
  • Patterning includes changing the shape of deposited materials, for example by using lithography.
  • lithography the device is coated with a photoresist, the photoresist exposed through a mask, unexposed regions washed away by a developer solution, and etching or other processing used to remove the deposited material from the unexposed regions.
  • lithography techniques are known and used in the semiconductor processing arts and can vary from the above sequence.
  • one alternate method 750 of fabrication can include depositing 754 a conductive material on a substrate, patterning 756 emitter, collector, and gate terminals, and forming a channel cavity, for example, by depositing 758 and patterning 760 a sacrificial layer and depositing 762 an insulating layers to define the channel cavity and other features of the device. Fabrication steps may be performed in alternate orders or using alternate techniques which will occur to one of ordinary skill the art based on the above disclosure.
  • nano emission devices can provide sensors as described further below.
  • An array of sensor devices can be disposed on an uppermost layer of a three- dimensional integrated circuit, and processing for the sensors implemented in lower layers.
  • An integrated sensing/processing device as just described may achieve higher performance than currently known devices. For example, reduced interconnect length between analog sensors and analog to digital conversion can help to reduce noise pickup. Increased interconnection between the sensors and processing is possible, so processing can be more tightly coupled to the sensing.
  • one application can include a single chip which includes imaging (e.g., similar to the function of a charge coupled device), distortion correction, image processing effects (e.g., digital zoom), and image encoding (e.g., JPEG). Such a device may significantly reduce the cost and complexity of a digital camera.
  • a shift to interfacing at the chip or wafer level may occur.
  • the two- dimensional arrangement of vias on the top layer of an integrated circuit may be defined and published. This can enable different business organizations to fabricate additional circuitry on top of a completed device.
  • one organization may fabricate one integrated circuit on a wafer or substrate, and a second organization may fabricate a second integrated circuit onto the same wafer or substrate, interfacing the second integrated circuit to the first integrated circuit to provide a functional system.
  • Many different integrated circuits may be vertically stacked in such a manner, providing an entire complex system on a single device.
  • integrated circuit devices may be interfaced directly by fabricating them on top of each other.
  • the second interconnection layer and custom circuitry layer may be fabricated by a third business organization.
  • the memory layer may include various pass-through vias, which allow connection between processor layer and the custom circuitry layer.
  • the completed three-dimensional integrated circuit may provide complex system functionality, such as the electronics for a computer system. Standardization of the interface arrangements (both top and bottom) of devices may occur to improve the economy of stacked integrated circuits.
  • a first organization may define base circuit functionality and interface map, and a second organization may fabricate a customizable integrated circuit wafer.
  • the customizable integrated circuit wafer may include a plurality of nano emission devices having interconnect vias on a top surface corresponding to the interface map.
  • nano emission devices can also be constructed on top of a conventional semiconductor wafer already having a plurality of semiconductor devices as illustrated in FIG. 24.
  • an electronic circuit 2400 can include both semiconductor devices and nano emission devices.
  • a conventional semiconductor wafer 2402 which already has a plurality of semiconductor devices 2404 can be prepared for fabrication of nano emission devices by depositing an insulating layer 2406 (e.g., silicon dioxide, silicon nitride, or other insulating material), etching for vias, metallization deposit to " form the electrical interconnection vias 2408, and a chemical mechanical polishing to planarize.
  • the nano emission devices 2410 can then be formed on top of the wafer, and interconnected to the semiconductor devices underneath through the vias. Such an arrangement can obtain the benefits of both semiconductor devices and nano emission devices.
  • Nano emission devices may be used in virtually any electronic system where conventional semiconductor devices are currently used, as well as opening up new potential uses for electronics.
  • Nano emission devices in accordance with embodiments of the present invention can be constructed from simple materials including for example as tungsten for conducting elements and silicon dioxide glass for insulating elements. Accordingly, costs associated with growing single crystal semiconductor and doping may be avoided making nano emission device based integration circuits less expensive to produce.
  • Ability to easily stack devices may overcome the barriers that have heretofore limited the use of three-dimensional integrated circuits.
  • Various advantages in speed, power consumption, and heat resistance for nano emission devices may make possible new levels of performance in electronic systems, revolutionizing the electronics industry.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Nanotechnology (AREA)
  • Chemical & Material Sciences (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Optics & Photonics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Biophysics (AREA)
  • Bipolar Transistors (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Cathode-Ray Tubes And Fluorescent Screens For Display (AREA)

Abstract

Des modes de réalisation de l'invention concernent d'une façon générale des dispositifs à nano-émission. Les dispositifs à nano-émission peuvent comporter, par exemple, des diodes (1200), des transistors du type N (100, 200, 250, 500, 600, 900), des transistors du type P (250, 300, 500, 600, 800, 900, 1500), et des transistors à nano-émission du type N et du type P (400). Les dispositifs à nano-émission peuvent comporter une pluralité d'émetteurs, de collecteurs, de grilles, et autres composants analogues formant des dispositifs à nano-émission plus complexes (1600, 1900, 2200). Les dispositifs à nano-émission peuvent être reliés entre eux pour former divers circuits, notamment des portes logiques (1402, 1404, 1408), des cellules de mémoire (1406) ou des amplificateurs. Les dispositifs à nano-émission peuvent être fabriqués dans des circuits intégrés à deux et à trois dimensions (1700, 2300, 2400). L'invention concerne également des procédés de fabrication (700, 750, 1100, 2500, 2600) de dispositifs à nano-émission et de circuits électroniques.
PCT/US2007/009829 2006-04-19 2007-04-19 Dispositifs à nano-émission, circuits intégrés utilisant des dispositifs à nano-émission, et procédés associés WO2008051300A2 (fr)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US79334306P 2006-04-19 2006-04-19
US60/793,343 2006-04-19
US83232006P 2006-07-21 2006-07-21
US60/832,320 2006-07-21
US90156107P 2007-02-14 2007-02-14
US60/901,561 2007-02-14

Publications (2)

Publication Number Publication Date
WO2008051300A2 true WO2008051300A2 (fr) 2008-05-02
WO2008051300A3 WO2008051300A3 (fr) 2008-10-02

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9431354B2 (en) 2014-11-06 2016-08-30 International Business Machines Corporation Activating reactions in integrated circuits through electrical discharge
US9859227B1 (en) 2016-06-30 2018-01-02 International Business Machines Corporation Damaging integrated circuit components

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5204588A (en) * 1991-01-14 1993-04-20 Sony Corporation Quantum phase interference transistor
US6864162B2 (en) * 2002-08-23 2005-03-08 Samsung Electronics Co., Ltd. Article comprising gated field emission structures with centralized nanowires and method for making the same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5204588A (en) * 1991-01-14 1993-04-20 Sony Corporation Quantum phase interference transistor
US6864162B2 (en) * 2002-08-23 2005-03-08 Samsung Electronics Co., Ltd. Article comprising gated field emission structures with centralized nanowires and method for making the same

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9431354B2 (en) 2014-11-06 2016-08-30 International Business Machines Corporation Activating reactions in integrated circuits through electrical discharge
US9991214B2 (en) 2014-11-06 2018-06-05 International Business Machines Corporation Activating reactions in integrated circuits through electrical discharge
US10262955B2 (en) 2014-11-06 2019-04-16 International Business Machines Corporation Activating reactions in integrated circuits through electrical discharge
US10388615B2 (en) 2014-11-06 2019-08-20 International Business Machines Corporation Activating reactions in integrated circuits through electrical discharge
US9859227B1 (en) 2016-06-30 2018-01-02 International Business Machines Corporation Damaging integrated circuit components
US10043765B2 (en) 2016-06-30 2018-08-07 International Business Machines Corporation Damaging integrated circuit components

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WO2008051300A3 (fr) 2008-10-02

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