CN110326099A - 半导体集成电路装置 - Google Patents

半导体集成电路装置 Download PDF

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CN110326099A
CN110326099A CN201880011883.2A CN201880011883A CN110326099A CN 110326099 A CN110326099 A CN 110326099A CN 201880011883 A CN201880011883 A CN 201880011883A CN 110326099 A CN110326099 A CN 110326099A
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岩堀淳司
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Socionext Inc
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Abstract

单元(1)是逻辑单元，且包括三维晶体管器件(P11、P12、N11、N12)。单元(2)是延迟单元，且包括三维晶体管器件(P21‑P24、N21‑N24)。单元(2)中局部布线(31)从立体扩散层部(21a、21b)朝远离电源线(VDD)的方向突出的长度(D2)大于单元(1)中局部布线(16)从立体扩散层部(11)朝远离电源线(VDD)的方向突出的长度(D1)。在使用三维晶体管器件的半导体集成电路装置中，实现每单位面积的延迟值较大的延迟单元。

Description

半导体集成电路装置
技术领域
本公开涉及一种半导体集成电路装置，该半导体集成电路装置使用了鳍式FET(场效应晶体管：Field Effect Transistor)、纳米线FET等三维晶体管器件。
背景技术
标准单元方式是在半导体衬底上形成半导体集成电路的一种已知方法。标准单元方式指的是下述方式，即：事先将具有特定逻辑功能的基本单元(例如反相器、锁存器、触发器、全加器等)作为标准单元准备好，然后将多个标准单元布置在半导体衬底上，再用布线将这些标准单元连接起来，这样来设计LSI芯片。
近年来，在半导体器件这一领域，有人提议采用鳍式构造的FET(以下称为鳍式FET)。图9是示意图，示出鳍式FET的简略构造。与二维构造的FET不同，鳍式FET的源极和漏极具有被称为鳍的凸起来的立体构造。并且，以包围该鳍的方式布置有栅极。根据该鳍式构造，沟道区域由鳍的三个面形成，因此相比现有技术，沟道的控制性得到大幅度改善。因此，能够获得减少漏电功耗、提高导通电流、进而降低工作电压等效果，从而提高半导体集成电路的性能。需要说明的是，鳍式FET是一种具有立体扩散层部的所谓的三维晶体管器件。除此之外，三维晶体管器件还有例如被称作纳米线FET的构造。
另一方面，延迟单元用于对电路动作进行定时调节等，例如用缓冲器等来实现。专利文献1示出了这样的延迟调节单元的示例。
专利文献1：日本公开专利公报特开2003-60487号公报
发明内容
-发明要解决的技术问题-
当封装三维晶体管器件时，一般使用局部布线(Local Interconnect)。局部布线是指与晶体管的扩散层、栅极不经由触点而直接接触的布线。
在使用所述局部布线的半导体集成电路装置中，如何实现每单位面积的延迟值较大的延迟单元是一个问题。
本公开在使用鳍式FET、纳米线FET等三维晶体管器件的半导体集成电路装置中，实现每单位面积的延迟值较大的延迟单元。
-用以解决技术问题的技术方案-
在本公开的第一方面中，一种半导体集成电路装置包括第一标准单元和第二标准单元，所述第一标准单元为逻辑单元，且具有三维晶体管器件，所述第二标准单元为延迟单元，且具有三维晶体管器件。所述第一标准单元包括：沿第一方向延伸的一个第一立体扩散层部、或者沿该第一方向延伸的多个第一立体扩散层部，其中，多个所述第一立体扩散层部沿与所述第一方向垂直的第二方向排列；以及第一局部布线，其沿所述第二方向延伸，且连接所述第一立体扩散层部与电源线，所述电源线沿所述第一方向延伸且供给规定的第一电源电压。所述第二标准单元包括：沿所述第一方向延伸的一个第二立体扩散层部、或者沿所述第一方向延伸的多个第二立体扩散层部，其中，多个所述第二立体扩散层部沿所述第二方向排列；第二局部布线，其沿所述第二方向延伸，且连接所述第二立体扩散层部与所述电源线；以及栅极布线，其沿所述第二方向延伸而在俯视时与所述第二立体扩散层部相交，且形成为包围所述第二立体扩散层部，并且规定的第二电源电压被施加在该栅极布线上。所述第二标准单元中所述第二局部布线从所述第二立体扩散层部朝向远离所述电源线的方向突出的长度，大于所述第一标准单元中所述第一局部布线从所述第一立体扩散层部朝向远离所述电源线的方向突出的长度。
根据上述方面，延迟单元即第二标准单元中局部布线从立体扩散层部朝远离电源线的方向突出的长度，大于逻辑单元即第一标准单元中局部布线从立体扩散层部朝远离电源线的方向突出的长度。即，在延迟单元中，与三维晶体管器件的立体扩散层部相连的局部布线从立体扩散层部延伸得较长。这样一来，局部布线与栅极布线之间的寄生电容就会更大，因此能够实现每单位面积的延迟值较大的延迟单元。
-发明的效果-
根据本公开，在使用三维晶体管器件的半导体集成电路装置中，能够实现每单位面积的延迟值较大的延迟单元。因此，能够提高半导体集成电路装置的性能。
附图说明
图1是俯视图，其示出第一实施方式所涉及的半导体集成电路装置所包括的标准单元的布局结构示例。
图2(a)、图2(b)是图1的结构的剖视图。
图3(a)、图3(b)是图1的标准单元的电路图。
图4(a)、图4(b)是延迟单元的其它电路示例。
图5是俯视图，其示出图1的标准单元2中金属布线的形状。
图6是俯视图，其示出图5的比较例。
图7是俯视图，其示出图1的标准单元2的变形例。
图8是俯视图，其示出图1的标准单元2的变形例。
图9是示意图，其示出鳍式FET的简略构造。
图10是示意图，其示出纳米线FET的简略构造。
图11是示意图，其示出纳米线FET的简略构造。
具体实施方式
下面，参照附图对实施方式进行说明。在以下实施方式中，半导体集成电路装置包括多个标准单元，该多个标准单元中的至少一部分使用鳍式FET(Field EffectTransistor)。需要说明的是，鳍式FET是三维晶体管器件的一例，构成鳍式FET的鳍是立体扩散层部的一例。
(第一实施方式)
图1是俯视图，其示出第一实施方式所涉及的半导体集成电路装置所包括的标准单元的布局结构示例。在图1中，将图中横向定为X方向(相当于第一方向)，将图中纵向定为Y方向(相当于第二方向)。之后的布局俯视图亦同。在图1中，标准单元1、2布置在沿X方向延伸的同一单元列中。CF是单元框。图2(a)是沿图1的A1-A1线剖开的剖视图，图2(b)是沿图1的A2-A2线剖开的剖视图。
图3(a)、图3(b)是电路图，分别示出标准单元1、2的电路结构。如图3(a)所示，标准单元1构成二输入NAND电路。标准单元1是有助于实现电路的逻辑功能的逻辑单元之一例。如图3(b)所示，标准单元2构成延迟单元。该延迟单元具有串联的四个反相器。
在图1中，沿X方向延伸的电源线VDD、VSS形成在金属布线层M1中。在标准单元1、2中，P型晶体管区域PA与N型晶体管区域NA沿Y方向排列着布置在电源线VDD与电源线VSS之间。就标准单元1而言，在P型晶体管区域PA具有沿X方向延伸的两个鳍11，在N型晶体管区域NA具有沿X方向延伸的两个鳍12。就标准单元2而言，在P型晶体管区域PA具有沿X方向延伸的两个鳍21a和沿X方向延伸的两个鳍21b，在N型晶体管区域NA具有沿X方向延伸的两个鳍22a和沿X方向延伸的两个鳍22b。鳍21a和鳍21b布置在同一条直线上，鳍22a和鳍22b布置在同一条直线上。在图1和其他俯视图中，由鳍和形成在其上的栅极布线构成鳍式FET。栅极布线从三个方向将鳍包围。需要说明的是，在图1和其他俯视图中，为了使图示清楚明了，用灰色示出鳍。
在与鳍层直接接触的布线层LI中，设有局部布线。局部布线的当俯视时与鳍或栅极布线重叠的部分是以与鳍或栅极布线的上层接触的方式形成的，局部布线与鳍或栅极布线电连接。金属布线位于局部布线的上层，并经由触点与局部布线相连。
标准单元1包括栅极布线13、14，栅极布线13、14横跨P型晶体管区域PA和N型晶体管区域NA地沿Y方向延伸。由鳍11和栅极布线13、14分别构成鳍式FET P11、P12。由鳍12和栅极布线13、14分别构成鳍式FET N11、N12。15a、15b是虚拟栅极布线。在鳍11、12的两端和栅极布线13、14之间，分别设有沿Y方向延伸的局部布线16。鳍11的两端经由局部布线16和触点17与电源线VDD相连。鳍12的一端(图中左侧端)经由局部布线16和触点17与电源线VSS相连。栅极布线13经由局部布线16和触点17与金属布线18a相连，其中，输入A被施加在金属布线18a上；栅极布线14经由局部布线16和触点17与金属布线18b相连，其中，输入B被施加在金属布线18b上。金属布线18c将输出Y输出，金属布线18c经由局部布线16和触点17与栅极布线13、14之间的鳍11以及鳍12的另一端(图中右侧端)相连。
标准单元2包括栅极布线23、24、25、26，栅极布线23、24、25、26横跨P型晶体管区域PA和N型晶体管区域NA地沿Y方向延伸。在P型晶体管区域PA，由鳍21a和栅极布线23构成鳍式FET P21，由鳍21a和栅极布线24构成鳍式FET P22。鳍式FET P21、P22共用一个源极，该源极经由沿Y方向延伸的局部布线31和触点28与电源线VDD相连。由鳍21b和栅极布线25构成鳍式FET P23，由鳍21b和栅极布线26构成鳍式FET P24。鳍式FET P23、P24共用一个源极，该源极经由沿Y方向延伸的局部布线31和触点28与电源线VDD相连。
在N型晶体管区域NA，由鳍22a和栅极布线23构成鳍式FET N21，由鳍22a和栅极布线24构成鳍式FET N22。鳍式FET N21、N22共用一个源极，该源极经由沿Y方向延伸的局部布线31和触点28与电源线VSS相连。由鳍22b和栅极布线25构成鳍式FET N23，由鳍22b和栅极布线26构成鳍式FET N24。鳍式FET N23、N24共用一个源极，该源极经由沿Y方向延伸的局部布线31和触点28与电源线VSS相连。
27a、27b、27c是虚拟栅极布线。虚拟栅极布线27c沿Y方向延伸，且穿过鳍21a与鳍21b之间以及鳍22a与鳍22b之间。虚拟栅极布线27c与鳍21a、21b、22a、22b保持间距地设置。
在标准单元2中，设有金属布线29a～29e。金属布线29a与栅极布线23相连。即，金属布线29a与鳍式FET P21、N21的栅极相连，且与标准单元2的输入C对应。金属布线29b将鳍21a、22a的一端(图中左侧端)连接到栅极布线24上。即，金属布线29b将鳍式FET P21、N21的漏极与鳍式FET P22、N22的栅极连接起来。金属布线29c将鳍21a、22a的另一端(图中右侧端)连接到栅极布线25上。即，金属布线29c将鳍式FET P22、N22的漏极与鳍式FET P23、N23的栅极连接起来。金属布线29d将鳍21b、22b的一端(图中左侧端)连接到栅极布线26上。即，金属布线29d将鳍式FET P23、N23的漏极与鳍式FET P24、N24的栅极连接起来。金属布线29e将鳍21b的另一端(图中右侧端)与鳍22b的另一端(图中右侧端)连接起来。即，金属布线29e将鳍式FET P24、N24的漏极彼此连接起来，且与标准单元2的输出Z对应。
此处，着重看一下将鳍与电源线连接起来的局部布线。
在标准单元2的P型晶体管区域PA，局部布线31与鳍21a、21b相连且沿Y方向延伸，局部布线31越过鳍21a、21b而向单元内侧进一步延伸较长的距离。即，局部布线31从鳍21a、21b朝远离电源线VDD的方向突出的长度(突出长度)D2大于标准单元1的P型晶体管区域PA中局部布线16从鳍11朝远离电源线VDD的方向突出的长度(突出长度)D1。同样，在标准单元2的N型晶体管区域NA，局部布线31与鳍22a、22b相连且沿Y方向延伸，局部布线31越过鳍22a、22b而向单元内侧进一步延伸较长的距离。
在一般的标准单元中，为了抑制寄生电容增大，将局部布线的长度设定成最小限度。例如，标准单元1中的局部布线16的突出长度D1优选为制造工艺允许的最小值。相对于此，在本实施方式中，在延迟单元即标准单元2中，为了增大布线电容而进一步增大延迟，使局部布线31越过鳍21a、21b、22a、22b而向单元内侧进一步延伸较长的距离。通过使局部布线31延伸较长的距离，而使得局部布线31与栅极布线23、24、25、26之间的寄生电容变得更大，因而能够增大延迟值。因此，能够实现每单位面积的延迟值较大的延迟单元即标准单元2。
需要说明的是，在图1的结构下，在标准单元1、2中，鳍11的个数等于鳍21a、21b的个数，且鳍11在Y方向上的位置与鳍21a、21b在Y方向上的位置相同。不过，本公开不限于此，鳍11的个数也可以不等于鳍21a、21b的个数，并且，鳍11在Y方向上的位置与鳍21a、21b在Y方向上的位置也可以不同。不管是哪种情况，只要将局部布线从鳍的靠单元内侧的一端突出的长度作为突出长度进行比较即可。
在图1的结构下，标准单元1、2布置在沿X方向延伸的同一单元列中，不过本公开不限于此，标准单元1、2还可以布置在不同的单元列中。
此外，延迟单元的电路结构不限于图3(b)所示的结构。例如，串联的反相器的个数也可以是四个以外的其它数量，例如两个或六个。或者，延迟单元的电路结构也可以是图4所示的电路结构。在图4(a)中，采用将反相器与开关电路串联起来的结构，该开关电路由P型晶体管和N型晶体管这一组晶体管构成。需要说明的是，在图4(a)中，使两个由开关电路和反相器构成的部分电路F1连接起来，不过也可以使N个(N是偶数)部分电路F1连接起来。还可以采用将两个以上的开关电路串联起来的结构。在图4(b)中，P型晶体管和N型晶体管两两纵向堆叠而构成反相器，由该反相器构成部分电路F2。需要说明的是，在图4(b)中，使两个部分电路F2连接起来，不过也可以使N个(N是偶数)部分电路F2连接起来。构成部分电路F2的反相器也可以由三个以上P型晶体管和三个以上N型晶体管纵向堆叠构成。即，延迟单元只要具有使输入信号延迟后再输出的电路结构即可，可以具有任意的电路结构。
(金属布线的形状)
图5是俯视图，其示出图1的标准单元2中金属布线的形状。需要说明的是，在图5中，为简化图示而省略了鳍和栅极布线。如上所述，在标准单元2中设有金属布线29a～29e，利用所述金属布线29a～29e进行用以构成标准单元2的逻辑的连接。
在本实施方式中，在进行用以构成标准单元2的逻辑的连接的金属布线中，增加了冗余部(图5中带黑点的部分)，冗余部是构成逻辑时用不到的部分。利用该冗余部，能够增大信号线的布线电容，从而能够进一步增大延迟。
具体而言，金属布线29c具有主部40a和冗余部41、42。主部40a(金属布线29c中不带黑点的部分)进行用以构成标准单元2的逻辑的连接，具体而言，主部40a将鳍式FET P22、N22的漏极与鳍式FET P23、N23的栅极连接起来。另一方面，冗余部41、42从主部40a向与主部40a的延伸方向(此处为Y方向)不同的方向(此处为X方向)分支，且仅与主部40a电连接。
同样，金属布线29d具有主部40b和冗余部43、44。主部40b(金属布线29d中不带黑点的部分)进行用以构成标准单元2的逻辑的连接，具体而言，主部40b将鳍式FET P23、N23的漏极与鳍式FET P24、N24的栅极连接起来。另一方面，冗余部43、44从主部40b向与主部40b的延伸方向(此处为Y方向)不同的方向(此处为X方向)分支，且仅与主部40b电连接。金属布线29e具有主部40c和冗余部45、46。主部40c(金属布线29e中不带黑点的部分)进行用以构成标准单元2的逻辑的连接，具体而言，主部40c将鳍式FET P24、N24的漏极彼此连接起来。另一方面，冗余部45、46从主部40c向与主部40c的延伸方向(此处为Y方向)不同的方向(此处为X方向)分支，且仅与主部40c电连接。
图6是示出作为比较例，当金属布线中不包括冗余部的情况下标准单元2的布局结构的图。由图6可知，即使从图5的布局中去掉冗余部41～46，对于构成标准单元2的逻辑而言也不会成为问题。
如上所述，在进行用以构成标准单元2的逻辑的连接的金属布线29c、29d、29e中，设置构成逻辑时用不到的冗余部41～46，从而能够增大信号线的布线电容，从而能够进一步增大延迟。
在图5的结构下，与第一布线对应的金属布线29d具有冗余部43，与第二布线对应的金属布线29e具有冗余部45，冗余部43与冗余部45沿同一方向(此处为X方向)延伸，且在与该同一方向垂直的方向(此处为Y方向)上，冗余部43与冗余部45之间没有其他的金属布线而相邻。同样，金属布线29d具有冗余部44，金属布线29e具有冗余部46，冗余部44与冗余部46沿同一方向(此处为X方向)延伸，且在与该同一方向垂直的方向(此处为Y方向)上，冗余部44与冗余部46之间没有其他的金属布线而相邻。根据上述构成方式，能够进一步增大信号线的布线电容，从而能够进一步增大延迟。
而且，就由鳍式FET P24、N24构成的反相器而言，金属布线29d与该反相器的输入端相连，金属布线29e与该反相器的输出端相连。这样一来，在同一反相器的输入信号线和输出信号线即金属布线29d、29e中，通过使冗余部43、45相邻，并使冗余部44、46相邻，而能够进一步增大信号线的延迟。需要说明的是，就反相器以外的逻辑门而言，在成为该逻辑门的输入信号线和输出信号线的金属布线中，也可以使冗余部相邻。
(变形例)
图7示出图1的标准单元2的布局结构的变形例。需要说明的是，在图7中，为简化图示而省略了鳍的图示。在图7的结构下，虚拟栅极布线27c经由局部布线51(带黑点的部分)与栅极布线25和金属布线29c相连。即，虚拟栅极布线27c与信号线相连，以构成电容。其中，该信号线将由鳍式FET P22、N22构成的反相器和由鳍式FET P23、N23构成的反相器连接起来。这样一来，能够增大信号线的布线电容，从而能够进一步增大延迟。
图8示出图1的标准单元2的布局结构的变形例。需要说明的是，在图8中，为简化图示而省略了鳍的图示。在图8的结构下，虚拟栅极布线27c经由局部布线61(带黑点的部分)与金属布线29c相连，且经由局部布线62(带黑点的部分)与栅极布线25相连。即，连接有虚拟栅极布线27c，以构成信号线的一部分。其中，该信号线将由鳍式FET P22、N22构成的反相器和由鳍式FET P23、N23构成的反相器连接起来。这样一来，虚拟栅极布线27c就会有助于信号线的延迟和布线电容的增大这两方面，从而能够进一步增大信号线的延迟。
(三维晶体管器件的另一例)
在上述各实施方式中，以鳍式FET为例进行了说明，不过也可以构成为采用了鳍式FET以外的三维晶体管器件，例如纳米线FET。
图10是示意图，其示出纳米线FET的基本构造示例(也称为环栅(GAA：Gate AllAround)型构造)。纳米线FET是使用了供电流流动的细线(纳米线)的FET。纳米线例如由硅形成。如图10所示，纳米线在衬底上沿着水平方向延伸，即平行于衬底延伸，其两端连接在构成纳米线FET的源极区域和漏极区域的构造物上。在本申请说明书中，将纳米线FET中连接在纳米线的两端上且构成纳米线FET的源极区域和漏极区域的构造物称为焊盘(pad)。在图10中，在硅衬底上形成有STI(浅槽隔离：Shallow Trench Isolation)结构，硅衬底在纳米线的下方(带斜线的部分)露出。需要说明的是，实际存在带斜线的部分被热氧化膜等覆盖的情况，但在图10中，为简化图示而省略了热氧化膜等的图示。
纳米线隔着氧化硅膜等绝缘膜而被例如由多晶硅形成的栅极电极绕一圈包围起来。焊盘和栅极电极形成在衬底的表面上。根据该构造，因为纳米线的沟道区域的上部、两侧部以及下部全部被栅极电极围起来，所以能够在沟道区域产生均匀的电场。这样一来，FET就会有良好的开关特性。
需要说明的是，焊盘中的至少连接有纳米线的部分构成源极区域/漏极区域，但有时候，比连接有纳米线的部分靠下的部分未必会构成源极区域/漏极区域。而且，有时候，纳米线的一部分(未被栅极电极围起来的部分)构成源极区域/漏极区域。
在图10中，沿纵向即与衬底垂直的方向布置有两条纳米线。不过，沿纵向布置的纳米线的条数并不限于两条，可以是一条，也可以是沿纵向排列着布置有三条以上。在图10中，最上面一条纳米线的上端与焊盘的上端高度齐平。不过，并非需要使它们的高度齐平，焊盘的上端也可以比最上面一条纳米线的上端高。
也存在图11所示的情况，即在衬底的上表面上形成有BOX(埋氧层：BuriedOxide)，并在该BOX上形成有纳米线FET。
需要说明的是，在上述实施方式中，用纳米线FET代替鳍式FET来构成半导体集成电路装置时，下述部分会与鳍式FET的鳍对应，所述部分为：纳米线FET中的一条纳米线或沿与衬底垂直的方向布置的多条纳米线；以及与该纳米线的两端相连的焊盘。例如，能够将图1的标准单元2中的两个鳍21a分别变更为下述构造：使沿X方向延伸的一条或沿与衬底垂直的方向布置的多条纳米线、与焊盘交替连接而成的构造。即，在采用纳米线FET的构成方式中，纳米线及与其两端相连的焊盘相当于立体扩散层部。局部布线与相当于立体扩散层部的构造中的焊盘相连。
需要说明的是，在不脱离发明主旨的范围内，可以将多个实施方式中的各构成要素任意组合。
-产业实用性-
根据本公开，在使用三维晶体管器件的半导体集成电路装置中，能够实现每单位面积的延迟值较大的延迟单元。因此，有利于提高半导体集成电路装置的性能。
-符号说明-
1 第一标准单元
2 第二标准单元
11、12、21a、21b、22a、22b 鳍(立体扩散层部)
13、14、23、24、25、26 栅极布线
16、31 局部布线
P11、P12、N11、N12、P21、P22、P23、P24、N21、N22、N23、N24
鳍式FET(三维晶体管器件)
27c 虚拟栅极布线
29a～29e 金属布线
40a、40b、40c 主部
41～46 冗余部
VDD 电源线
VSS 电源线

Claims (9)

1.一种半导体集成电路装置，其特征在于：
所述半导体集成电路装置包括第一标准单元和第二标准单元，
所述第一标准单元为逻辑单元，且具有三维晶体管器件，
所述第二标准单元为延迟单元，且具有三维晶体管器件，
所述第一标准单元包括：
沿第一方向延伸的一个第一立体扩散层部、或者沿该第一方向延伸的多个第一立体扩散层部，其中，多个所述第一立体扩散层部沿与所述第一方向垂直的第二方向排列；以及
第一局部布线，其沿所述第二方向延伸，且连接所述第一立体扩散层部与电源线，所述电源线沿所述第一方向延伸且供给规定的第一电源电压，
所述第二标准单元包括：
沿所述第一方向延伸的一个第二立体扩散层部、或者沿所述第一方向延伸的多个第二立体扩散层部，其中，多个所述第二立体扩散层部沿所述第二方向排列；
第二局部布线，其沿所述第二方向延伸，且连接所述第二立体扩散层部与所述电源线；以及
栅极布线，其沿所述第二方向延伸而在俯视时与所述第二立体扩散层部相交，且形成为包围所述第二立体扩散层部，并且规定的第二电源电压被施加在该栅极布线上，
所述第二标准单元中所述第二局部布线从所述第二立体扩散层部朝远离所述电源线的方向突出的长度，大于所述第一标准单元中所述第一局部布线从所述第一立体扩散层部朝远离所述电源线的方向突出的长度。
2.根据权利要求1所述的半导体集成电路装置，其特征在于：
所述第一立体扩散层部的个数等于所述第二立体扩散层部的个数，且所述第一立体扩散层部在所述第二方向上的位置与所述第二立体扩散层部在所述第二方向上的位置相同。
3.根据权利要求1所述的半导体集成电路装置，其特征在于：
所述第二标准单元包括金属布线，所述金属布线形成在所述第二局部布线的上层，
所述金属布线包括第一布线，
所述第一布线具有主部和冗余部，
所述主部进行用以构成该第二标准单元的逻辑的连接，
所述冗余部从所述主部向与所述主部的延伸方向不同的方向分支，且仅与所述主部电连接。
4.根据权利要求3所述的半导体集成电路装置，其特征在于：
所述金属布线包括第二布线，所述第二布线具有所述主部和所述冗余部，
所述第一布线所具有的所述冗余部与所述第二布线所具有的所述冗余部沿同一方向延伸，且在与该同一方向垂直的方向上，所述第一布线所具有的所述冗余部与所述第二布线所具有的所述冗余部之间没有其他的金属布线而相邻。
5.根据权利要求4所述的半导体集成电路装置，其特征在于：
所述第二标准单元包括由三维晶体管器件构成的逻辑门，
所述第一布线与所述逻辑门的输入端相连，
所述第二布线与所述逻辑门的输出端相连。
6.根据权利要求5所述的半导体集成电路装置，其特征在于：
所述逻辑门是反相器。
7.根据权利要求1所述的半导体集成电路装置，其特征在于：
所述第二标准单元包括虚拟栅极布线，所述虚拟栅极布线沿所述第二方向延伸，且与所述第二立体扩散层部保持间距地设置，
所述虚拟栅极布线与下述布线相连，该布线进行用以构成该第二标准单元的逻辑的连接。
8.根据权利要求7所述的半导体集成电路装置，其特征在于：
所述虚拟栅极布线构成下述布线的一部分，该布线进行用以构成该第二标准单元的逻辑的连接。
9.根据权利要求1到8中任一项权利要求所述的半导体集成电路装置，其特征在于：
所述三维晶体管器件是鳍式场效应晶体管或纳米线场效应晶体管。
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