WO2008038360A1 - Écran plasma et procédé de fabrication correspondant - Google Patents

Écran plasma et procédé de fabrication correspondant Download PDF

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Publication number
WO2008038360A1
WO2008038360A1 PCT/JP2006/319267 JP2006319267W WO2008038360A1 WO 2008038360 A1 WO2008038360 A1 WO 2008038360A1 JP 2006319267 W JP2006319267 W JP 2006319267W WO 2008038360 A1 WO2008038360 A1 WO 2008038360A1
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WO
WIPO (PCT)
Prior art keywords
protective layer
partition wall
discharge
plasma display
electrode
Prior art date
Application number
PCT/JP2006/319267
Other languages
English (en)
Japanese (ja)
Inventor
Fumiaki Yoshino
Takashi Sasaki
Tatsuhiko Kawasaki
Original Assignee
Hitachi Plasma Display Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Plasma Display Limited filed Critical Hitachi Plasma Display Limited
Priority to JP2008536242A priority Critical patent/JPWO2008038360A1/ja
Priority to PCT/JP2006/319267 priority patent/WO2008038360A1/fr
Publication of WO2008038360A1 publication Critical patent/WO2008038360A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J11/00—Gas-filled discharge tubes with alternating current induction of the discharge, e.g. alternating current plasma display panels [AC-PDP]; Gas-filled discharge tubes without any main electrode inside the vessel; Gas-filled discharge tubes with at least one main electrode outside the vessel
    • H01J11/20—Constructional details
    • H01J11/34—Vessels, containers or parts thereof, e.g. substrates
    • H01J11/40—Layers for protecting or enhancing the electron emission, e.g. MgO layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J11/00—Gas-filled discharge tubes with alternating current induction of the discharge, e.g. alternating current plasma display panels [AC-PDP]; Gas-filled discharge tubes without any main electrode inside the vessel; Gas-filled discharge tubes with at least one main electrode outside the vessel
    • H01J11/10—AC-PDPs with at least one main electrode being out of contact with the plasma
    • H01J11/12—AC-PDPs with at least one main electrode being out of contact with the plasma with main electrodes provided on both sides of the discharge space
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J9/00—Apparatus or processes specially adapted for the manufacture, installation, removal, maintenance of electric discharge tubes, discharge lamps, or parts thereof; Recovery of material from discharge tubes or lamps
    • H01J9/24—Manufacture or joining of vessels, leading-in conductors or bases
    • H01J9/241—Manufacture or joining of vessels, leading-in conductors or bases the vessel being for a flat panel display
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2211/00—Plasma display panels with alternate current induction of the discharge, e.g. AC-PDPs
    • H01J2211/20—Constructional details
    • H01J2211/34—Vessels, containers or parts thereof, e.g. substrates
    • H01J2211/36—Spacers, barriers, ribs, partitions or the like
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2211/00—Plasma display panels with alternate current induction of the discharge, e.g. AC-PDPs
    • H01J2211/20—Constructional details
    • H01J2211/34—Vessels, containers or parts thereof, e.g. substrates
    • H01J2211/42—Fluorescent layers

Definitions

  • the present invention relates to a plasma display panel and a method for manufacturing the same, and more particularly to a plasma display panel having a wide viewing angle and improved luminous efficiency and a method for manufacturing the same.
  • the surface discharge type PDP a display electrode pair is provided on the front substrate, and address electrodes, barrier ribs for dividing the discharge space, and a phosphor layer for color display are provided on the rear substrate.
  • the surface discharge PDP is suitable for extending the life compared to the counter discharge type in which the X and Y display electrodes are separately arranged on the front and back substrates.
  • the rear substrate is provided with strip-like or grid-like barriers that divide phosphors of different emission colors, and the front substrate has a dielectric layer covering the display electrodes, MgO, etc.
  • the protective layer is provided, and the protective layer and the top of the partition wall are in contact with each other. Since the barrier rib on the back substrate is also an insulator such as glass and is a kind of dielectric, a part of the electric field formed in the discharge space by the voltage applied to the display electrode also goes to the barrier rib. For this reason, a part of the electric charge generated by the discharge collides with the partition wall.
  • a protective layer such as MgO that covers the dielectric layer on the display electrode, in addition to the function of protecting the dielectric layer from the impact of the discharge ions, prevents secondary electrons from colliding with the discharge ions. It has a function of releasing a large amount to grow a discharge.
  • force-formed barriers such as glass materials have a lower secondary electron emission coefficient than MgO, and the amount of secondary electrons emitted by ions colliding with the barriers is much less than that of MgO protective layers. For this reason, the discharge during the display period is hindered by the barrier ribs on the rear substrate side, which reduces the discharge scale and is one of the causes of the decrease in PDP emission efficiency.
  • Patent Document 1 A structure in which the emission efficiency is increased by increasing the amount of secondary electron emission has been proposed (Patent Document 1).
  • Patent Document 1 the entire surface of the phosphor layer of the back substrate is covered with MgO as a protective layer to increase the amount of secondary electron emission.
  • a phosphor layer is formed on the surface of the back substrate and the lower side region of the barrier rib, and only the protective layer of MgO is formed on the upper side region of the barrier rib without forming the phosphor layer.
  • the phosphor layer should be covered with a protective layer. By preventing the protective layer from covering the phosphor layer, the phosphor layer is prevented from being degraded by the MgO formation process.
  • Patent Document 1 Japanese Patent Laid-Open No. 2002-110046
  • Patent Document 1 since the entire phosphor layer is covered with a protective layer, the amount of secondary electron emission increases due to the presence of the MgO protective layer above the barrier ribs. Although the discharge scale increases, there is a problem that the amount of ultraviolet light that reaches the phosphor layer is reduced when the protective layer absorbs the ultraviolet light generated by the ionization of the discharge gas, and the luminous efficiency does not increase.
  • the MgO protective layer is formed only on the side wall of the barrier rib, and the phosphor layer is formed on the lower region on the side wall of the barrier rib and on the address electrode on the back substrate.
  • the phosphor layer is formed in the upper region of the side wall of the barrier rib, and therefore corresponds to the upper side of the barrier rib in the cell space sandwiched between the barrier ribs. At both ends, there is a problem that the amount of light emission decreases and the viewing angle decreases.
  • an object of the present invention is to provide a PDP having a wide viewing angle and improved luminous efficiency.
  • Another object of the present invention is to provide a PDP having an increased emission scale by increasing the amount of secondary electron emission while suppressing a decrease in viewing angle.
  • Another object of the present invention is to provide a method for producing the PDP.
  • a front substrate and a back substrate are provided.
  • a display electrode group, a dielectric layer on the display electrode, and a secondary layer covering the dielectric layer are formed on the front substrate.
  • a first protective layer having a material strength with a high electron emission coefficient is formed on the back substrate.
  • an address electrode group, barrier ribs arranged on both sides of the address electrode, and an upper side of the address electrode are formed.
  • the phosphor layer reaching the top of the lower side of the side wall of the partition wall and the phosphor layer on the address electrode and the lower region of the side surface of the partition wall are not covered, and the phosphor layer near the top of the side surface of the partition wall And a second protective layer made of the above-described material for covering the substrate.
  • the phosphor layer is formed so as to reach the top of the side wall of the partition wall, so that a reduction in viewing angle can be suppressed, and the lower region on the side surface of the partition wall is excluded.
  • the discharge scale can be increased by secondary electron emission from the second protective layer.
  • the second protective layer covers a part of the phosphor layer, so that part of the ultraviolet light is absorbed by the protective layer.
  • the ultraviolet light reaches the phosphor layer near the top of the barrier rib and emits light, the viewing angle is reduced. The decrease can be suppressed.
  • a method for manufacturing an AC plasma display panel having a discharge space in which a discharge gas is sealed between a front substrate and a back substrate Forming a display electrode group on the front substrate, a dielectric layer thereon, and a first protective layer made of a material having a high secondary electron emission coefficient that covers the dielectric layer, and an address on the rear substrate.
  • Cover nearby phosphor layers Characterized by a step of forming a second protective layer made of sea urchin said material mosquitoes ⁇ al.
  • the second protective layer can be deposited only in the vicinity of the top of the side wall of the partition wall, the amount of secondary electrons emitted can be reduced while suppressing the absorption of ultraviolet rays into the phosphor layer. Increased PDP can be formed.
  • FIG. 1 is a cross-sectional view of a PDP in a first embodiment.
  • FIG. 2 is a perspective view showing the basic structure of a PDP.
  • FIG. 3 is a block diagram showing a configuration of a PDP drive circuit.
  • FIG. 4 is a diagram showing a PDP drive sequence.
  • FIG. 5 is a diagram showing a driving waveform of a PDP.
  • FIG. 6 is a cross-sectional view of a PDP in a second embodiment.
  • FIG. 7 is a diagram showing a production method in the present invention.
  • FIG. 8 is a diagram showing the viewing angle dependency in a cell in the present embodiment.
  • FIG. 9 is a diagram showing the discharge mechanism of PDP.
  • FIG. 2 is a perspective view showing a general configuration of the PDP.
  • the PDP shown in Fig. 2 is an AC-driven three-electrode surface discharge PDP for color display.
  • the front substrate 1 and the rear substrate 9 are placed facing each other across the discharge gas space.
  • a plurality of display electrodes 2X and a display electrode 2Y extending in the horizontal direction are arranged in parallel.
  • the display line is completely between the adjacent display electrode 2X and display electrode 2Y.
  • This PDP is a PDP with a V-type ALIS structure in which the display electrode 2X and the display electrode 2Y are arranged at equal intervals, and all the display lines between the adjacent display electrodes 2X and 2Y become display lines.
  • the present invention can also be applied to a PDP having a structure in which the pair of display electrodes 2X and 2Y is arranged with a non-discharge gap that does not generate discharge.
  • Each display electrode 2X, 2Y includes a transparent electrode 10 made of ITO, Sn02, etc. and, for example, Ag, Au, Al, Cu, Cr formed thereon and a laminate thereof (for example, a stack of CrZCuZCr).
  • the structure is composed of a metal nose electrode 11 that also has force.
  • the display electrodes 2X and 2Y use thick film formation technology such as screen printing for Ag and Au, and thin film formation technology such as vapor deposition and sputtering and etching technology for other metals. It is formed with a specified number, thickness, width and spacing.
  • the transparent electrode 10 is mainly formed of a light-transmitting material so that it can contribute to the discharge and the light emission of the phosphor can be seen from the front substrate 1 side.
  • the nose electrode 11 should have low resistance in order to allow the current during discharge to flow.
  • a dielectric layer 3 is formed on the display electrodes 2X and 2Y so as to cover the display electrodes 2X and 2Y.
  • Dielectric layer 3 is made of glass paste mainly composed of low melting point glass powder, It is formed by applying it on the substrate 1 by screen printing and baking at high temperature. There is also a method of attaching and firing a sheet-like dielectric layer. Furthermore, the dielectric layer 3 may be formed by forming a Si02 film by plasma CVD.
  • a protective film 4 is formed on the dielectric layer 3 in order to protect the dielectric layer 3 from the impact force caused by the collision of ions generated by the discharge.
  • This protective film 4 is made of a material having a high secondary electron emission coefficient when ions collide, and, for example, MgO or MgF is used.
  • the protective film 4 is formed by a thin film formation process known in the art, such as electron beam evaporation or sputtering.
  • a plurality of address electrodes 8 are formed in a direction intersecting the display electrodes 2X and 2Y when viewed in plan, and a dielectric layer 7 is formed covering the address electrodes 8. ing.
  • the address electrode 8 generates an address discharge for selecting a light emitting cell at the intersection with the display electrode 2Y, and is formed of, for example, a three-layer structure of CrZCuZCr.
  • the address electrode 8 can be formed of Ag, Au, Al, Cu, Cr, or the like.
  • the address electrode 8 uses a thick film formation technique such as screen printing for Ag and Au, and a thin film formation technique such as vapor deposition and sputtering and an etching technique for other metals. By using it, it is formed with a predetermined number, thickness, width and spacing.
  • the dielectric layer 7 can be formed using the same material and the same method as the dielectric layer 3 on the front substrate 1. The dielectric layer 7 is not necessarily provided.
  • partition walls 5 are formed between adjacent address electrodes 8, respectively.
  • the shape of the partition wall 5 in this example is a stripe shape parallel to the address electrode, but it may be a lattice shape surrounding the cell region at the intersection of the address electrode and the display electrode.
  • the partition wall 5 is formed by a sand blast method, a photo etching method, or the like.
  • a sand blast method for example, a low-melting-point glass powder, a binder resin, a solvent-based glass base such as a solvent is applied on the dielectric layer 7 and dried, and then a partition wall pattern is formed on the glass paste layer.
  • the partition wall 5 is formed by spraying cutting particles with the cutting mask having the above-mentioned opening, cutting the glass paste layer exposed at the opening of the mask, and further baking.
  • photosensitive paste method instead of cutting with cutting particles, photosensitive resin is used as binder resin for glass paste, and after exposure and development using a mask, baking is performed. It is formed from Kotoko.
  • the red (R), green (G), and blue (B) phosphor layers 6R, 6G, and 6B are formed on the side and bottom surfaces of the discharge space partitioned by the barrier ribs 5, respectively.
  • Phosphor layers 6R, 6G, and 6B are coated with a phosphor paste containing phosphor powder, binder resin, and solvent in the discharge space separated by the barrier ribs by a method using screen printing or a dispenser. However, this is repeated for each color and then formed by firing.
  • the phosphor layers 6R, 6G, and 6B use a sheet-like phosphor layer material containing a phosphor powder, a photosensitive material, and a binder resin, a so-called green sheet, and are formed by photolithography technology. It can also be formed. In this case, a phosphor sheet 6 of each color is formed between the corresponding barrier ribs 5 by applying a sheet of a predetermined color to the entire display area on the substrate, exposing and developing, and repeating this for each color. To do.
  • the phosphor layers 6R, 6G, and 6B are formed on the address electrode 8, that is, on the dielectric layer when the dielectric layer 7 is provided, and on the address electrode when the dielectric layer 7 is not provided. Further, it is formed up to the side wall of the partition wall.
  • the front substrate and the rear substrate are placed facing each other so that the display electrodes 2X, 2Y and the address electrode 8 intersect, the periphery is sealed, and the discharge space surrounded by the barrier ribs 5 is Xe It is made by filling discharge gas mixed with Ne.
  • the discharge space at the intersection of the display electrodes 2X and 2Y and the address electrode 8 is one cell (unit emission region), which is the smallest unit of display.
  • One pixel consists of three cells, R, G, and B.
  • FIG. 3 is a block diagram showing an overall configuration of an example of a plasma display module.
  • display electrodes XI, X2, X3,... That perform sustain discharge and display electrodes Y1, Y2, Y3,... That are also scan electrodes are alternately arranged to form a display line.
  • a display cell in the form of a matrix is formed by the electrodes and address electrodes Al, A2, A3,... Perpendicular to these electrodes.
  • the address drive circuit 15, scan driver 16, Y drive circuit 17, and X drive circuit 18 are connected to the corresponding electrodes.
  • a control circuit 19 for controlling them is also provided.
  • the scan driver 16 selects scan electrodes (display lines) by sequentially applying scan pulses to the scan electrodes Y during the address period, and selects the scan electrodes selected with the address electrodes A connected to the address drive circuit 15. Address discharge to select whether the cell is lit or not Z is lit with electrode Y Cause it to occur.
  • the Y drive circuit 17 and the X drive circuit 18 generate the number of sustain discharges corresponding to the weight of each subfield for the cells selected by the address discharge during the display period.
  • the control circuit 19 controls a predetermined image display by outputting a control signal suitable for each drive circuit from image data inputted from an external device such as a TV tuner or a computer, a synchronization signal, and a control signal.
  • FIG. 4 is a diagram showing an example of a gradation drive sequence in the PDP of FIG.
  • the grayscale drive sequence in the plasma display device consists of one field (frame) 20 consisting of multiple subfields (subframes) 21 (SFl to SFn) each having a predetermined luminance weight.
  • a predetermined gradation is displayed by combining the subfields.
  • the ratio of the number of sustain discharges is set to 1: 2: 4: 8: 16: 32: 64: 128 and has a luminance weight of power of 2 8
  • the 256 sub-fields SF1 to SF8 display 256 gray levels.
  • the number of subfields and the weight of each subfield can be combined in various ways!
  • each subfield is selected by an initialization process (reset period 22) for uniforming wall charges of all cells in the display area, an address process (address period 23) for selecting a lighted cell, and a selection process. It consists of a display process (sustain discharge period 24) in which the cells are discharged and turned on the number of times corresponding to the luminance (weight of each subfield). Then, for each subfield, the cell is turned on according to the brightness, and display control of one field is performed by controlling display of, for example, eight subfields SF1 to SF8.
  • FIG. 5 shows an example of the drive waveform.
  • Figures 5 (a) to 5 (e) show the drive waveforms applied to the display electrodes XI, Yl, Y3, Y2, and the address electrode A during the period from the reset period 22 to the sustain discharge period 24, respectively.
  • the numbers attached to ⁇ and ⁇ indicate the number of rows, and this waveform shows the case of discharge between two electrodes with the same number.
  • Yl, ⁇ 3 is an example representing ⁇ odd rows and ⁇ 2 is an even row.
  • the Y write obtuse wave 32 and the X voltage 25 for forming wall charges in all the cells are applied to the electrodes XI and Y1 in FIGS. 5 (a) and 5 (b).
  • the Y compensation blunt wave 33 and the X compensation voltage 26 are applied to erase the wall charges formed in the cell while leaving a necessary amount.
  • the voltage waveform applied in the next address period 23 is an odd-numbered scan scan 34 for discharging to determine display cells in the row direction, and an X voltage 27 for forming charges by this discharge. .
  • the scanning pulse 34 is applied at a different timing for each row. In the subsequent sustain discharge period 24, the first sustain pulse 28, 35, repeated sustain pulse 29, 30, 31, 36, 37, 38 force S is applied.
  • Fig. 5 (c) shows the voltage waveform applied to electrode Y3, which is the same as the voltage waveform applied to electrode Y1 shown in Fig. 5 (b) except for the timing of scan pulse 39. If no cell on the electrode Y3 line is lit, the scan pulse 39 is unnecessary and can be thinned out. Thereby, drive time can be shortened. At this time, no voltage is applied to all the address electrodes, and they can be thinned out in the same way. Since the voltage applied to the display electrode is also a constant value, similar time reduction is easy.
  • the Y write blunt wave 40 that forms charges in all cells is applied to the electrode Y2 in Fig. 5 (d). Subsequently, a Y compensation blunt wave 41 is applied to erase the charge formed in the cell while leaving a necessary amount.
  • the voltage waveform applied in the next address period 23 is the scan pulse 42 of the even-numbered row that performs the discharge that determines the display cell in the row direction. This scan pulse 42 is also applied while shifting the timing for each row.
  • a first sustain pulse 44, repeated sustain pulses 44, 45, and a discharge pulse adjusting pulse 46 are applied.
  • the voltage waveform applied to the address electrode A in FIG. 5 (e) during the address period is the address pulses 47 and 48 for performing discharge that determines the cells to be displayed in the column direction.
  • the address pulse is applied at the timing when a discharge is generated in the cell to be displayed located at the intersection of the scan electrode and the address electrode A in synchronization with the scan pulse applied for each row.
  • a voltage waveform for erasing wall charges may be added at the end of the display period 24.
  • FIG. 1 shows a cross-sectional view of the PDP in the first embodiment.
  • the front glass substrate 1 has a display electrode 2 made of a transparent electrode material, a dielectric layer 3 covering the display electrode 2, and a dielectric layer.
  • a first protective film 4-1 having a high secondary electron emission coefficient and containing any of MgO, MgF, and SrO to be coated is formed. These forming methods are as described above.
  • the rear glass substrate 9 has a plurality of address electrodes 8 extending in a direction intersecting with the display electrodes, a dielectric layer 7 covering the address electrodes 8, and a stripe shape that divides the discharge space into cell arrays.
  • a grid-like partition wall 5 is formed. As described above, this partition wall 5 is formed by sandblasting using glass paste.
  • a phosphor layer 6 is formed on the dielectric layer 7 on the address electrodes 8 and on the side surfaces of the barrier ribs 5. As described above, this phosphor layer 6 is formed of phosphor materials that emit RGB light separately. If the dielectric layer 7 is not provided, the phosphor layer 6 is formed on the address electrode 8.
  • the phosphor layer 6 is applied to reach the top of the lower region force on the side surface of the partition wall 5 of the back glass substrate 9. Then, a second protective layer 4-2 having a high secondary electron emission coefficient such as MgO, MgF, or SrO is formed so as to cover the phosphor layer 6 in the vicinity of the top of the side wall of the partition wall 5.
  • a second protective layer 4-2 having a high secondary electron emission coefficient such as MgO, MgF, or SrO is formed so as to cover the phosphor layer 6 in the vicinity of the top of the side wall of the partition wall 5.
  • FIG. 8 is a diagram showing the spread of PDP discharge.
  • the protective layer 41 on the front substrate side and the protective layer 4-2 on the top of the partition wall of the rear substrate are shown enlarged.
  • charged particles (electrons) that exist in the discharge space move due to the electric field, collide with the gas molecules 49 of the discharge gas, and are separated into positive ions 50 and electrons 51.
  • the positive ions 50 generated at this time move by the electric field and collide with the scanning electrode (Y electrode), which is the cathode.
  • the protective layer 4-1 covering the Y electrode of the cathode emits secondary electrons.
  • the emitted secondary electrons collide with gas molecules 49 and are separated into positive ions 50 and electrons 51.
  • gas molecules are ionized, ultraviolet rays are emitted, and the ultraviolet rays collide with the phosphor to excite the phosphor and induce light emission.
  • the phosphor layer 6 is formed on the side surface of the partition wall 5 partitioning the cells of the rear glass substrate 9 until the lower region force reaches the top, that is, the height of the side surface of the partition wall is full.
  • the protective layer 4-2 was deposited to cover the phosphor layer 6 only near the top of the side wall of the partition wall 5.
  • the phosphor layer 6 is formed to reach the top surface of the dielectric layer 7 on the address electrode 8 and the top of the lower region force on the side wall of the partition wall, it is high in the cell region. Emission brightness can be achieved and the viewing angle can be kept wide.
  • the phosphor layer 6 is covered with the protective film 4-2 in the vicinity of the top of the partition wall, so that the ultraviolet rays are partially absorbed by the protective layer 4-2, but the remaining ultraviolet rays reach the phosphor layer 6. Exciting and contributing to light emission, it is possible to widen the high emission luminance region in the cell region.
  • the phosphor layer 6 near the top of the barrier rib affected by the ion bombardment due to the discharge is protected by the protective layer 42, so that the lifetime of the phosphor layer 6 can be extended.
  • FIG. 9 is a graph showing the correlation between the cell center distance and the luminance in the present embodiment, and showing the viewing angle dependence of the luminance.
  • the solid line shows the emission intensity ratio of the present embodiment
  • the broken line shows the emission intensity ratio of Patent Document 1 described above.
  • the phosphor layer 6B is not formed only up to the lower side region of the partition wall 5 but the phosphor layer is formed up to the top of the side surface as shown by the broken line. ⁇ ⁇ For this reason, the emission brightness decreases as the cell centering force moves away.
  • the solid line As shown, since the phosphor layer 6A is applied to the vicinity of the top of the side wall of the partition wall 5, the emission luminance hardly decreases even when the cell center force is separated.
  • the protective layer 42 since only the phosphor layer 6 near the top of the side surface of the partition wall 5 is covered with the protective layer 42, the ultraviolet rays generated by the discharge are absorbed by the protective layer 4-2, and the phosphor layer It is possible to minimize the failure to reach 6. Therefore, the decrease in phosphor emission due to the provision of protective layer 4-2 can be minimized. From the above, in this embodiment, it is possible to improve the discharge near the top of the partition wall while preventing the viewing angle and the luminance from being lowered.
  • FIG. 7 is an explanatory diagram of the PDP manufacturing method in the present embodiment.
  • a protective layer having MgO force is formed only near the top of the side wall of the partition wall on the back glass substrate.
  • MgO pellets 13 placed on the hearth 12 as the deposition source were placed on the rear glass substrate 9 on which the partition walls 5 were formed in the deposition apparatus.
  • MgO is deposited while holding it diagonally and exposing only one side of partition wall 5 to the deposition source.
  • the MgO pellet 13 placed on the hearth 12 is irradiated with the electron beam 14 to sublimate the pellet 13, and the sublimated MgO is blown in the direction of arrow 11. Therefore, in this embodiment, the rear glass substrate 9 is tilted and the state in which only one side surface of the partition wall faces the deposition source is passed through the rear glass substrate 9 through the vapor deposition apparatus. In this way, MgO is deposited on one side of the side wall of the partition wall on the inclined rear glass substrate. At this time, MgO is not deposited on the lower region of the side wall of the partition wall and the address electrode, which is behind the adjacent partition wall 5.
  • the MgO film is also deposited near the top of the side wall on the opposite side of the partition wall by changing the tilt direction to the opposite side and passing it over the MgO pellet again.
  • MgO can be deposited only near the tops of both sides of the partition wall 5 by changing the inclination direction of the back glass substrate 9 and reciprocating the MgO pellets 13 as the deposition source. .
  • the force can be easily realized by simply tilting the rear glass substrate 9 in a predetermined direction.
  • the protective layer 42 is formed from the vicinity of the top of the partition wall side surface to the top.
  • FIG. 6 is a cross-sectional view of the PDP in the second embodiment of the present invention.
  • the parts other than the protective layer 42 on the top of the partition wall 5 on the rear glass substrate 9 are shown in FIG. This is the same as the first embodiment.
  • a protective layer 42 is formed near the top of the partition wall 5 of the rear glass substrate 9, whereas in the second embodiment of FIG.
  • a protective layer 42 that covers the phosphor layer 6 is provided only in the vicinity of the top of the side surface excluding the top of the partition wall 5 of the substrate 9.
  • the top of the barrier rib 5 is in contact with the protective layer 4-1 on the front substrate side, so it does not contribute to secondary electron emission during discharge.
  • the protective layer that also has MgO power is hygroscopic in itself and causes deterioration of the discharge characteristics after sealing the panel. Therefore, it is desirable not to form an MgO protective layer on top of unnecessary barrier ribs.
  • MgO is deposited near the top of the partition wall 5 by vapor deposition or the like, and then MgO on the top of the partition wall is polished.
  • the protective layer 4-2 can be formed only on the phosphor layer 6 near the top of the barrier rib.
  • MgO may be formed by covering the top of the barrier rib with a mask and covering the portion of the phosphor layer surface except the vicinity of the top of the barrier rib with a mask.

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Abstract

La présente invention concerne un procédé qui, afin d'améliorer l'efficacité d'émission tout en supprimant la détérioration de l angle de vue, forme une couche fluorescente à partir de la portion inférieure du haut haut d'une paroi séparatrice de la région cellule d'un substrat arrière, et une couche protectrice composée de MgO ou de son équivalent, ayant un coefficient élevé d'émission secondaire d'électron se forme ainsi dans le voisinage du haut de la paroi séparatrice. Puisque l'efficacité de l'émission est améliorée par l'augmentation de l'émission secondaire de l'électron dans le voisinage du haut de la paroi séparatrice, ce qui augmente l'échelle de décharge, et que la couche fluorescente est formée à partir de la portion inférieure vers le haut de la paroi séparatrice, il est possible de parvenir à une haute luminance d'émission sur la région entière de la cellule.
PCT/JP2006/319267 2006-09-28 2006-09-28 Écran plasma et procédé de fabrication correspondant WO2008038360A1 (fr)

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Application Number Priority Date Filing Date Title
JP2008536242A JPWO2008038360A1 (ja) 2006-09-28 2006-09-28 プラズマディスプレイパネル及びその製造方法
PCT/JP2006/319267 WO2008038360A1 (fr) 2006-09-28 2006-09-28 Écran plasma et procédé de fabrication correspondant

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PCT/JP2006/319267 WO2008038360A1 (fr) 2006-09-28 2006-09-28 Écran plasma et procédé de fabrication correspondant

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WO2008038360A1 true WO2008038360A1 (fr) 2008-04-03

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JPH05342992A (ja) * 1992-06-05 1993-12-24 Fujitsu Ltd 面放電型プラズマディスプレイパネル
JPH08185802A (ja) * 1994-12-28 1996-07-16 Noritake Co Ltd 放電表示装置
JPH08212929A (ja) * 1995-02-09 1996-08-20 Dainippon Printing Co Ltd Ａｃ型プラズマディスプレイパネル及びその製造方法
JPH10302645A (ja) * 1997-04-22 1998-11-13 Matsushita Electric Ind Co Ltd ガス放電パネル
JP2001052614A (ja) * 1998-09-08 2001-02-23 Matsushita Electric Ind Co Ltd 表示パネル及び表示パネルの製造方法
JP2000311614A (ja) * 1999-04-27 2000-11-07 Matsushita Electric Ind Co Ltd Ａｃ型プラズマディスプレイ装置
JP2001035385A (ja) * 1999-07-16 2001-02-09 Kyocera Corp プラズマディスプレイパネルおよびその製造方法
JP2002110046A (ja) * 2000-09-27 2002-04-12 Matsushita Electric Ind Co Ltd 面放電型プラズマ・ディスプレイ・パネル
WO2004038753A1 (fr) * 2002-10-22 2004-05-06 Matsushita Electric Industrial Co., Ltd. Ecran d'affichage a plasma
JP2004200040A (ja) * 2002-12-19 2004-07-15 Pioneer Electronic Corp プラズマディスプレイパネル
JP2004214049A (ja) * 2003-01-06 2004-07-29 Matsushita Electric Ind Co Ltd ガス放電パネルおよびその製造方法
WO2006038654A1 (fr) * 2004-10-05 2006-04-13 Matsushita Electric Industrial Co., Ltd. Panneau d’affichage plasma et méthode de production de celui-ci

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Publication number Priority date Publication date Assignee Title
JP2010073508A (ja) * 2008-09-19 2010-04-02 Hitachi Ltd プラズマディスプレイパネル及びそれを備えた画像表示装置

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