WO2008027802A2 - Electrostatic discharge protection circuit for compound semiconductor devices and circuits - Google Patents

Electrostatic discharge protection circuit for compound semiconductor devices and circuits Download PDF

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Publication number
WO2008027802A2
WO2008027802A2 PCT/US2007/076724 US2007076724W WO2008027802A2 WO 2008027802 A2 WO2008027802 A2 WO 2008027802A2 US 2007076724 W US2007076724 W US 2007076724W WO 2008027802 A2 WO2008027802 A2 WO 2008027802A2
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WO
WIPO (PCT)
Prior art keywords
transistor
series
terminal
circuit
coupled
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2007/076724
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English (en)
French (fr)
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WO2008027802A3 (en
Inventor
Andrew T. Ping
Dominic J. Ogbonnah
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Qorvo US Inc
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Triquint Semiconductor Inc
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Priority to JP2009526823A priority Critical patent/JP5497437B2/ja
Publication of WO2008027802A2 publication Critical patent/WO2008027802A2/en
Publication of WO2008027802A3 publication Critical patent/WO2008027802A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
    • H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
    • H02H9/046—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere responsive to excess voltage appearing at terminals of integrated circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/811—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using FETs as protective elements

Definitions

  • Embodiments of the present invention relate generally to semiconductor devices and more specifically, to an electrostatic discharge protection circuit for compound semiconductor devices and circuits.
  • ESD electrostatic discharge
  • an ESD event may occur either during the assembly and packaging of these devices and circuits, or during normal operation of these devices and circuits in an end product.
  • An ESD event occurs when a high potential voltage and current are rapidly discharged into the device or circuit, which typically results in the destruction of devices and circuits that are not protected from ESD events.
  • FIG. 1 shows a schematic diagram of an ESD protection circuit according to the prior art.
  • ESD protection circuit 100 includes an input/output pad 1 10, an internal circuit 120, and a multiplicity of diodes 130 and 140 coupled in series to ground.
  • an ESD event is typically dissipated through a series of diode elements. This can be seen in ESD protection circuit 100, where diodes 130 and 140 are used to dissipate an ESD event, thereby protecting internal circuit 120 from the ESD event.
  • ESD protection circuit 100 uses large diodes (i.e., diodes that have large widths) in order to effectively dissipate an ESD event. This is particularly true for diodes in compound semiconductor field effect transistor (FET) technology.
  • FET field effect transistor
  • large diodes consume a relatively large amount of area in the component that contains the ESD protection circuit. Consequently, the component must be larger, which, among other things, increases the cost of the component.
  • Figure 2 illustrates a plot 200 of the transmission line pulse characteristic 210 of current versus voltage for an ESD protection circuit according to the prior art.
  • the transmission line pulse characteristic 210 reflects the presence of diodes in the discharge path of the ESD protection circuit. A large series resistance in the discharge path can be seen in transmission line pulse characteristic 210 in that the dissipation of current has an increasing effect on voltage.
  • U.S. Patent No. 4,930,036 illustrates a prior art ESD protection circuit that attempts to address some of the disadvantages described above.
  • the ESD protection circuit in the '036 patent uses a transistor and a resistor, rather than a multiplicity of diodes, in the discharge path.
  • the resistor adds resistance to the discharge path. Consequently, the use of the transistor and resistor, rather than a multiplicity of diodes, is still disadvantageous for the reasons described above.
  • the ESD protection circuit in the '036 patent requires two power supplies, including a low-level voltage supply and a high-level voltage supply.
  • the need for power supplies increases the complexity, and therefore the cost, of the ESD protection circuit, because additional terminals are needed to connect the power supplies to the ESD protection circuit.
  • U.S. Patent Application Publication Number 2004/0057172 illustrates another prior art ESD protection circuit.
  • the ESD protection circuit in the '172 patent application is implemented using heterojunction bipolar transistor (HBT) technology.
  • HBT heterojunction bipolar transistor
  • One disadvantage of such an ESD protection circuit is that it requires two separate discharge paths, one to dissipate a positive ESD event and another to dissipate a negative ESD event.
  • the presence of two discharge paths adds complexity to the ESD protection circuit, consumes space, and increases the cost of the ESD protection circuit.
  • the ESD protection circuit in the '172 patent application uses at least one diode in series with a transistor in the discharge path. This increases the series resistance in the discharge path, which, as described above, is a disadvantage for ESD protection circuits.
  • FIG. 1 illustrates a schematic diagram of an electrostatic discharge (ESD) protection circuit according to the prior art
  • Figure 2 illustrates a plot of the transmission line pulse characteristic of current versus voltage for an ESD protection circuit according to the prior art
  • Figure 3 illustrates a block diagram of an ESD protection circuit according to one embodiment of the present invention
  • Figure 4 illustrates a plot of the transmission line pulse characteristic of current versus voltage according to embodiments of the present invention
  • FIGS 5A through 5I illustrate the ESD protection circuit of Figure 3 according to embodiments of the present invention
  • Figure 6 illustrates an ESD protection circuit according to another embodiment of the present invention.
  • Figure 7 illustrates a flow chart of a process for ESD protection for compound semiconductor devices and circuits according to embodiments of the present invention.
  • FIG. 3 illustrates a block diagram of an electrostatic discharge (ESD) protection circuit 300 according to an embodiment of the present invention.
  • ESD protection circuit 300 comprises terminals 310 and 320, a triggering element 330, a shut-off element 340, a series element 350, and a transistor shunt element 360.
  • Triggering element 330, shut-off element 340, series element 350 and transistor shunt element 360 provide a minimal resistance discharge path, so that an ESD event does not damage devices or integrated circuits that may be coupled with terminals 310 and 320.
  • triggering element 330 activates transistor shunt element 360 to dissipate the ESD event.
  • Triggering element 330 provides the ability to set the value of a turn-on voltage of transistor shunt element 360, i.e., the voltage at which transistor shunt element 360 turns-on and is activated to dissipate an ESD event.
  • the number of diodes in triggering element 330 can be used to establish the turn-on voltage level.
  • Shut-off element 340 keeps the ESD discharge path turned-off during normal operation, so that it is not used until such time as the turn-on voltage of transistor shunt element 360 is reached.
  • Series element 350 provides the ability to limit the gate current into transistor shunt element 360.
  • Transistor shunt element 360 provides a bi-directional discharge path, through, for example, the drain and source of transistor shunt element 360, to dissipate an ESD event.
  • Embodiments of the present invention operate in connection with either a positive ESD event, where the potential of terminal 310 is higher than the potential of terminal 320, or a negative ESD event, where the potential of terminal 320 is higher than the potential of terminal 310.
  • the polarity of the ESD event determines the discharge direction between terminals 310 and 320. For example, if a positive ESD event occurs, triggering element 330 is the element that turns-on transistor shunt element 360, but if a negative ESD event occurs, shut-off element 340 becomes the element that turns-on transistor shunt element 360.
  • ESD protection circuit 300 provides for a bi-directional discharge path for an ESD event across terminals 310 and 320.
  • series element 350 provides the ability to limit the gate current into transistor shunt element 360 during a negative ESD event.
  • ESD protection circuit 300 is fabricated using pseudomorphic high electron mobility transistor (pHEMT) technology, which is a compound semiconductor field effect transistor (FET) technology.
  • pHEMT pseudomorphic high electron mobility transistor
  • FET compound semiconductor field effect transistor
  • ESD protection circuit 300 may be fabricated using other compound semiconductor FET technologies, including, for example, but not limited to, metal semiconductor field effect transistor (MESFET), junction field effect transistor (jFET), high electron mobility transistor (HEMT), metamorphic high electron mobility transistor (mHEMT), heterostructure field effect transistor (HFET), modulation-doped field effect transistor (MODFET), or any other suitable compound semiconductor FET technologies.
  • MESFET metal semiconductor field effect transistor
  • jFET junction field effect transistor
  • HEMT high electron mobility transistor
  • mHEMT metamorphic high electron mobility transistor
  • HFET heterostructure field effect transistor
  • MODFET modulation-doped field effect transistor
  • Compound semiconductor materials used to fabricate ESD protection circuit 300 may include materials, such as, for example, Gallium Arsenide (GaAs), Indium Phosphide (InP), Gallium Nitride (GaN), and derivatives of the foregoing, such as Aluminum Gallium Arsenide (AIGaAs), Indium Gallium Arsenide (InGaAs), Indium Gallium Phosphide (InGaP), Indium Aluminum Arsenide (InAIAs), Aluminum Gallium Nitride (AIGaN), Indium Gallium Nitride (InGaN), Gallium Arsenide Antimonide (GaAsSb), Indium Gallium Arsenide Nitride (InGaAsN), and Aluminum Arsenide (AIAs), for example.
  • GaAs Gallium Arsenide
  • GaN Gallium Nitride
  • AIAs Aluminum Arsenide
  • ESD protection circuit 300 is formed on a Gallium Arsenide (GaAs) substrate.
  • GaAs Gallium Arsenide
  • ESD protection circuit 300 may be formed on other types of substrates, such as, for example, Indium Phosphide (InP) and Gallium Nitride (GaN).
  • terminal 310 may be coupled with a device or an integrated circuit to be protected from an ESD event, and terminal 320 may be coupled with a ground.
  • terminal 320 may be coupled with a reference potential other than ground.
  • the reference potential may provide an additional voltage potential to increase or decrease the level of the turn-on voltage, as will be explained below in greater detail.
  • terminal 310 may be coupled with a bond pad, input/output pin or any other connection associated with ESD protection circuit 300, and terminal 320 may be coupled with another bond pad, input/output pin or any other connection within ESD protection circuit 300.
  • transistor shunt element 360 is an enhancement-mode pHEMT.
  • transistor shunt element 360 is described as an enhancement-mode pHEMT, embodiments of the present invention contemplate any suitable enhancement-mode FET such as, for example, MESFET jFET, HEMT, mHEMT, HFET, MODFET or any other suitable compound semiconductor FET.
  • Embodiments of the present invention activate transistor shunt element 360 on a voltage-controlled basis, in connection with a gate-to-source voltage. That is, voltage is applied to the gate of transistor shunt element 360, and if the magnitude of the gate-to-source voltage is less than the threshold voltage of transistor shunt element 360, then transistor shunt element 360 is turned-off. Shut-off element 340 holds the gate-to-source voltage of transistor shunt element 360 below the threshold voltage of transistor shunt element 360 until the turn-on voltage established based on triggering element 330 is reached.
  • the turn-on voltage of ESD protection circuit 300 can be set using diodes in triggering element 330.
  • no diodes or resistors are used in the discharge path.
  • Embodiments of the present invention use transistor shunt element 360 to discharge the ESD event. Among other things, this reduces the series resistance in the discharge path of embodiments of the present invention, which enables embodiments of the present invention to dissipate an ESD event as rapidly as possible.
  • diodes are not used in the discharge path since they do not dissipate an ESD event, smaller diodes may be used relative to those used in prior art ESD protection circuits that use diodes in the discharge path. Among other things, this reduces the size of ESD protection circuit 300 relative to such prior art ESD protection circuits.
  • embodiments of the present invention have one discharge path for both positive and negative ESD events, rather than two discharge paths like some prior art ESD protection circuits.
  • this reduces the complexity of embodiments of the present invention, reduces the amount of space consumed, and reduces the cost of the component that includes the ESD protection circuit of embodiments of the present invention.
  • the use of a power supply is not required with embodiments of the present invention.
  • this reduces the complexity, and therefore the cost, of ESD protection circuits in accordance with embodiments of the present invention.
  • FIG. 4 illustrates a plot 400 of the transmission line pulse characteristic 410 of the current versus voltage according to embodiments of the present invention.
  • ESD protection circuit 300 provides a discharge path so that the ESD event does not damage devices and/or integrated circuits.
  • the discharge path in ESD protection circuit is a low resistance path to ground that allows for a rapid dissipation of an ESD event through transistor shunt element 360. Accordingly, it can be seen in Figure 4 that ESD protection circuit 300 dissipates increasing current with only a minimal effect on voltage.
  • triggering element 330 provides a turn-on voltage of approximately 10 volts. Once the turn-on voltage has been exceeded, the transmission-line pulse characteristic 410 is shown to "snap back," in this case to a voltage of 10 volts. The "snap-back" voltage is determined by the construction of the transistor shunt element 360.
  • Figures 5A through 51 illustrate the ESD protection circuit 300 of Figure 3 according to embodiments of the present invention. As described above, ESD protection circuit 300 comprises terminals 310 and 320, triggering element 330, shut-off element 340, series element 350, and transistor shunt element 360. In addition, the drain of transistor shunt element 360 is coupled with terminal 310, the source of transistor shunt element 360 is coupled with terminal 320, and the gate of transistor shunt element 360 is coupled with series element 350.
  • triggering element 330 comprises a plurality of diodes D1 , D2, through DN coupled in series from terminal 310 to shut-off element 340 and series element 350.
  • diodes D1 , D2, through DN may be any diode, for example, but not limited to, a Schottky diode.
  • diodes D1 , D2 to DN in Figures 5A through 5I may be implemented using a transistor connected in a diode configuration, i.e., the gate of the transistor connected to the drain of the transistor.
  • a component such as, for example, but not limited to, a resistor as shown in Figure 5I, may be coupled in series with diodes D1 , D2 to DN.
  • shut-off element 340 comprises a resistor R1 coupled with a gate-source-coupled transistor 370 (wherein gate-source-coupled transistor 370 has its gate coupled with its source) coupled in series between triggering element 330 and series element 350 to terminal 320.
  • gate-source-coupled transistor 370 is a depletion-mode FET.
  • Series element 350 comprises a series resistor R2 coupled with the gate of transistor shunt element 360 and triggering element 330 and shut-off element 340.
  • triggering element 330 comprises a plurality of diodes D1 , D2, through DN coupled in series from terminal 310 to shut-off element 340 and series element 350.
  • Shut-off element 340 comprises a resistor R1 coupled with a gate-source- coupled transistor 370 coupled in series between triggering element 330 and series element 350 to terminal 320.
  • Series element 350 comprises a short circuit that provides a direct connection between the gate of transistor shunt element 360 to triggering element 330 and shut-off element 340.
  • triggering element 330 comprises a plurality of diodes D1 , D2, through DN coupled in series from terminal 310 to shut-off element 340 and series element 350.
  • Shut-off element 340 comprises a resistor R1 coupled in series between triggering element 330 and series element 350 to terminal 320.
  • Shut-off element 340 may also comprise a gate-source-coupled transistor 370 coupled in series between triggering element 330 and series element 350 to terminal 320, as shown in Figure 5H.
  • Series element 350 comprises a series resistor R2 coupled with the gate of transistor shunt element 360 and triggering element 330 and shut-off element 340.
  • triggering element 330 comprises a plurality of diodes D1 , D2, through DN coupled in series from terminal 310 to shut-off element 340 and series element 350.
  • Shut-off element 340 comprises a resistor R1 coupled in series between triggering element 330 and series element 350 to terminal 320.
  • Series element 350 comprises a short circuit that provides a direct connection between the gate of transistor shunt element 360 to triggering element 330 and shut-off element 340.
  • triggering element 330 comprises a plurality of diodes D1 , D2, through DN coupled in series from terminal 310 to shut-off element 340 and series element 350.
  • Shut-off element 340 comprises a source-resistor-coupled transistor 380, wherein the source of source-resistor-coupled transistor 380 is coupled with a resistor R1 in series between triggering element 330 and series element 350 to terminal 320, and wherein the gate of source-resistor-coupled transistor 380 is coupled with terminal 320.
  • source-resistor-coupled transistor 380 is a depletion-mode FET.
  • Source-resistor-coupled transistor 380 being a depletion-mode FET.
  • Series element 350 comprises a short circuit that provides a direct connection between the gate of transistor shunt element 360 to triggering element 330 and shut-off element 340.
  • triggering element 330 comprises a plurality of diodes D1 , D2, through DN coupled in series from terminal 310 to shut-off element 340 and series element 350.
  • Shut-off element 340 comprises a resistor R1 coupled with a gate-source- coupled transistor 370 coupled in series between triggering element 330 and series element 350 to terminal 320.
  • Series element 350 comprises a plurality of diodes E1 through EN coupled in series from the gate of transistor shunt element 360 to triggering element 330 and shut-off element 340.
  • triggering element 330 comprises a gate-source-coupled transistor 370 coupled with a plurality of diodes D1 , D2, through DN coupled in series from terminal 310 to shut-off element 340 and series element 350.
  • Shut-off element 340 comprises a resistor R1 coupled with a gate-source-coupled transistor 370 coupled in series between triggering element 330 and series element 350 to terminal 320.
  • Series element 350 comprises a series resistor R2 coupled with the gate of transistor shunt element 360 and triggering element 330 and shut-off element 340.
  • the plurality of diodes D1 , D2, through DN, of triggering element 330 provide for controlling or setting the turn-on voltage of transistor shunt element 360.
  • the turn-on voltage may be adjusted and controlled.
  • the turn-on voltage may be increased by increasing the number of diodes coupled in series, or in the alternative, the turn-on voltage may be decreased by reducing the number of diodes coupled in series.
  • Embodiments of the present invention contemplate the use of any type of diode, including, for example, but not limited to, a Schottky diode.
  • shut-off element 340 keeps the ESD discharge path, and in particular transistor shunt element 360, turned-off during normal operation (i.e., when the operating voltage is less than the turn-on voltage). However, during a negative ESD event, shut-off element 340 becomes the element that turns-on transistor shunt element 360, thereby providing bi-directional ESD discharge protection.
  • series element 350 can be used to limit the gate current into transistor shunt element 360.
  • ESD protection circuit 300 is shown and described as having a particular arrangement of components, embodiments of the present invention contemplate any arrangement of components herein and/or any combination of components herein to perform ESD protection.
  • Figure 6 illustrates ESD protection circuit 600 according to an embodiment of the present invention.
  • ESD protection circuit 600 comprises terminals 310 and 320, shut-off element 340, series element 350, and transistor shunt element 360.
  • Shut-off element 340 comprises a resistor R1 in series between series element 350 and terminal 320.
  • Series element 350 comprises a short circuit that provides a direct connection between the gate of transistor shunt element 360 and shut- off element 340.
  • ESD protection circuit 600 the voltage at which transistor shunt element 360 dissipates an ESD event is determined by characteristics of transistor shunt element 360 and resistor R1 of shut-off element 340.
  • shut-off element 340 and series element 350 are shown and described as comprising particular components, embodiments of the present invention contemplate any arrangement of components herein and/or any combination of components herein to perform ESD protection.
  • any shut-off element 340 and/or series element 350 described above in connection with Figures 5A-5I can be used with ESD protection circuit 600.
  • FIG. 7 illustrates a flow chart 700 of a process for ESD protection for compound semiconductor devices and circuits according to embodiments of the present invention.
  • terminal 310 may be coupled with a device or an integrated circuit to be protected from an ESD event
  • terminal 320 may be coupled with a ground or other reference potential other than ground.
  • flow chart 700 starts at 702, with ESD protection circuit operating in normal operation (i.e., when the operating voltage is less than a turn-on voltage).
  • ESD protection circuit 300 experiences an ESD event and detects a voltage at, for example, terminal 310 above a turn-on voltage.
  • the turn-on voltage may be adjusted and controlled.
  • triggering element 330 turns-on and at 708, transistor shunt element 360 turns-on.
  • transistor shunt element 360 provides a minimal resistance discharge path to dissipate the ESD event, so that the ESD event does not damage the device or integrated circuit coupled with terminals 310 and 320.
  • ESD protection circuit 300 provides for a bi-directional discharge path for either a positive or negative ESD event occurring at either terminal 310 or terminal 320.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Junction Field-Effect Transistors (AREA)
PCT/US2007/076724 2006-08-30 2007-08-24 Electrostatic discharge protection circuit for compound semiconductor devices and circuits Ceased WO2008027802A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009526823A JP5497437B2 (ja) 2006-08-30 2007-08-24 化合物半導体素子および回路のための静電放電保護回路

Applications Claiming Priority (2)

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US11/512,951 US8144441B2 (en) 2006-08-30 2006-08-30 Electrostatic discharge protection circuit for compound semiconductor devices and circuits
US11/512,951 2006-08-30

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WO2008027802A2 true WO2008027802A2 (en) 2008-03-06
WO2008027802A3 WO2008027802A3 (en) 2008-05-02

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JP (1) JP5497437B2 (enExample)
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US8144441B2 (en) 2012-03-27
WO2008027802A3 (en) 2008-05-02

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