WO2008026283A1 - Circuit de surveillance d'horloge, appareil de traitement d'informations et procédé de surveillance d'horloge - Google Patents

Circuit de surveillance d'horloge, appareil de traitement d'informations et procédé de surveillance d'horloge Download PDF

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Publication number
WO2008026283A1
WO2008026283A1 PCT/JP2006/317220 JP2006317220W WO2008026283A1 WO 2008026283 A1 WO2008026283 A1 WO 2008026283A1 JP 2006317220 W JP2006317220 W JP 2006317220W WO 2008026283 A1 WO2008026283 A1 WO 2008026283A1
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WO
WIPO (PCT)
Prior art keywords
data
unit
clock
output
change
Prior art date
Application number
PCT/JP2006/317220
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English (en)
Japanese (ja)
Inventor
Tomoo Shirota
Yoshihiko Sano
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to JP2008531937A priority Critical patent/JP4962497B2/ja
Priority to PCT/JP2006/317220 priority patent/WO2008026283A1/fr
Publication of WO2008026283A1 publication Critical patent/WO2008026283A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy
    • G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
    • G06F11/0757—Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information

Definitions

  • the present invention relates to a clock monitoring circuit that monitors a clock of a device that operates in synchronization with a clock.
  • the present invention relates to an information processing apparatus and a clock monitoring method, and particularly to a clock monitoring circuit, an information processing apparatus, and a clock monitoring method capable of monitoring a clock at a high speed with a small amount of hardware.
  • FIG. 6 is an explanatory diagram for explaining mutual timeout monitoring. As shown in the figure, in mutual timeout monitoring, one unit A activates the other unit B between units A and B operating at different clocks, and the unit B that has been activated is activated for a certain period of time. Report the response to Unit A within.
  • unit A checks whether or not there is a response of unit B after starting and sending, and if it fails to detect a response within a certain time, it detects unit B as a timeout. To do.
  • unit A detects an error in unit B due to a timeout, for example, as shown in FIG. 7, unit A that has generated the error is disconnected and switched to unit C, which is an alternative unit.
  • FIG. 7 shows a case where unit B and unit C are memories, and unit A and unit D share data on unit B or unit C.
  • Patent Document 2 detects a data transmission area for the purpose of grasping the data propagation status between registers when the internal clock is stopped. Technology is disclosed.
  • Patent Document 1 Japanese Patent Laid-Open No. 10-143390
  • Patent Document 2 Japanese Patent Laid-Open No. 62-115544
  • unit B can accept a disconnection command with the power of unit A when the FF of the unit B shown in Fig. 7 that receives activation from unit A cannot operate normally due to a failure. No state.
  • Unit A detects the error in Unit B, so the power that can be switched to another unit C that does not use the data in Unit B)
  • Unit D is the unit B detected by Unit A If unit B is used continuously without knowing the failure, a situation will occur. This situation can be dealt with by duplicating the nose Z circuit that transmits the disconnection instruction from unit A to units B and C, but this increases the amount of hardware, and so on. There's a problem.
  • the present invention has been made to solve the above-described problems in the prior art, and includes a clock monitoring circuit, an information processing apparatus, and a clock that can monitor a clock at high speed with less software.
  • the purpose is to provide a monitoring method.
  • a clock monitoring circuit includes a data output unit that outputs data whose value is inverted when a clock signal is input, and the data output unit.
  • a data receiving means for receiving the output data; a data change detecting means for detecting a change in the data received by the data receiving means; and the data received within a predetermined time by the data change detecting means is changed. If not, it has an error detection means for detecting as an error.
  • data whose value is inverted by inputting a clock signal is output, the output data is received, a change in the received data is detected, and the received data within a predetermined time is If it does not change, it is configured to detect as an error. Locks can be monitored.
  • the data change detecting means of the clock monitoring circuit includes a data holding means for holding data by inputting a clock signal, and an exclusive OR operation between the input and output of the data holding means. It may be configured to have logic operation means for performing
  • the data is held by inputting the clock signal, and the exclusive OR operation between the input and output of the holding means is performed, so that the data can be changed with a simple mechanism. Can be detected.
  • the information processing apparatus is an information processing apparatus having a first unit and a second unit, wherein the first unit is a data whose value is inverted by input of a clock signal.
  • Data output means for outputting data to the second unit, data receiving means for receiving data output from the second unit by the data output means of the second unit, and the data receiving means
  • a data change detecting means for detecting a change in received data, and an error in the second unit when the received data does not change within a predetermined time by the data change detecting means. Error detecting means for performing the above.
  • the first unit outputs data whose value is inverted by the input of the clock signal to the second unit, and receives and receives the data output from the second unit. If a change in data is detected and the received data does not change within a predetermined time, it is detected as an error in the second unit, so the clock can be monitored with a simple mechanism.
  • the information processing apparatus is an information processing apparatus having a plurality of units, and one of the plurality of units has data whose value is inverted by an input of a clock signal. Output from any one of the plurality of units by means of a data output means for outputting to any one of the plurality of units and data output means possessed by any unit of the plurality of units Data receiving means for receiving the received data, data change detecting means for detecting a change in the data received by the data receiving means, and the data change detecting means for receiving the data within a predetermined time If the data does not change, the error of the unit that output the received data And an error detecting means for performing detection.
  • one unit among the plurality of units outputs data whose value is inverted from the input signal of the clock signal to any one of the plurality of units.
  • Receives data output from one of the units detects changes in the received data, and if the received data does not change within the specified time, detects the received data as an error in the unit that output the data
  • the clock can be monitored with a simple mechanism.
  • the clock monitoring method is a clock monitoring method for monitoring a circuit that operates in synchronization with a clock signal, and outputs data whose value is inverted by the input of the clock signal; Receiving the output data; detecting a change in the received data; detecting if the received data does not change within a predetermined time; It is characterized by having.
  • data whose value is inverted by the input of a clock signal is output, the output data is received, a change in the received data is detected, and the data received within a predetermined time is received. If it does not change, it is configured to detect as an error, so the clock can be monitored with a simple mechanism.
  • the data output means outputs the most significant bit of an incrementer that operates as a clock.
  • the error detection means performs error detection using an incrementer that is reset by inversion of the value of the data received by the data reception means.
  • the error detection since the error detection is performed using the incrementer that is reset by the inversion of the value of the received data, the error detection can be performed with a simple mechanism.
  • the data output means further includes synchronization means for receiving the data and sending the received data to the data reception means so as to be synchronized with the data reception means. .
  • synchronization means for receiving the data and sending the received data to the data reception means so as to be synchronized with the data reception means.
  • the circuit that operates in synchronization with the clock signal is composed of a plurality of parts, and in the data receiving step, the data that has also been transmitted with a partial force by the data output step is transferred to other parts.
  • the certain part receives the data that has been propagated and returned.
  • the circuit that operates in synchronization with the clock signal is composed of a plurality of parts, and the data transmitted from one part is propagated to the other part and the data returned is a part. Therefore, it is possible to monitor the clock by propagating data in the circuit.
  • the circuit that operates in synchronization with the clock signal includes a plurality of units that operate with different clocks, and the data reception step receives data transmitted from another unit and detects the error.
  • the step is characterized in that the clock of the other unit is monitored by detecting whether or not the value of the data received in the data receiving step is reversed within the predetermined time.
  • the circuit that operates in synchronization with the clock signal is composed of a plurality of units that operate with different clocks, receives data sent by other units, and receives the value of the received data. Since it is configured to detect whether the clock is inverted within a predetermined time and to monitor the clock of the other unit, the clock of the other unit can be monitored with a simple mechanism.
  • data for clock monitoring is output with a simple mechanism. /, It has the effect of being able to monitor the clock at high speed with no software.
  • the error detection of the data for clock monitoring is performed with a simple mechanism, so that it is possible to monitor the clock at a high speed with a small amount of hardware.
  • the clock is monitored by propagating data in the circuit.
  • the clock can be monitored at high speed with less hardware.
  • FIG. 1 is an explanatory diagram for explaining a clock monitoring mechanism according to the first embodiment.
  • FIG. 2 is a functional block diagram illustrating the configuration of the check circuit according to the first embodiment.
  • FIG. 3 is an explanatory diagram for explaining the clock monitoring mechanism according to the second embodiment.
  • FIG. 4 is a diagram showing output circuit 211 and check circuit 222 shown in FIG.
  • FIG. 5 is a diagram showing clock mutual monitoring in three units.
  • FIG. 6 is an explanatory diagram for explaining mutual timeout monitoring.
  • FIG. 7 is a diagram illustrating an example of processing after error detection.
  • FIG. 8 is a timing chart showing normal operation of the second embodiment.
  • FIG. 9 is a timing chart illustrating an operation at the time of error according to the second embodiment.
  • FIG. 10 is a timing chart showing normal operation of the first embodiment.
  • FIG. 11 is a timing chart illustrating an operation at the time of error according to the first embodiment.
  • FIG. 1 is an explanatory diagram for explaining the clock monitoring mechanism according to the first embodiment. As shown in the figure, this clock monitoring mechanism divides the unit W that operates on the monitored clock into functional blocks or area blocks (X, Y, and Z in Fig. 1).
  • X inverts the data held in the clocked FF and sends it to Y at regular intervals.
  • the data held in FF is inverted at regular intervals and sent to Z.
  • the data held in FF is inverted at regular intervals and sent to X.
  • X sends the inverted data to Y every fixed time, and at the same time checks whether the data from Z changes within a certain time. If the data from Z does not change within a certain time, it is determined that the clock is abnormal. The same applies to Y and Z.
  • FIG. 2 is a block diagram illustrating the configuration of the check circuit according to the first embodiment.
  • the check circuit 100 includes FF1 to FF4, EOR5 and 6, FF10, and an error detection circuit 20.
  • FF1 to FF4 are flip-flops (Flip-Flop) that are connected in series and operate as a clock, and are provided to synchronize a signal input to each block with a clock signal.
  • the input of FF4 and the output of FF4 are connected to two inputs of EOR5 which performs exclusive OR operation to detect the change of data (edge trigger).
  • EOR5 which performs exclusive OR operation to detect the change of data (edge trigger).
  • FF10 is a flip-flop that operates as a clock, and data held for each clock is inverted and output by EOR6 that performs an exclusive OR operation.
  • the error detection circuit 20 is a circuit that detects a clock error by detecting whether or not the FF10 value changes within a certain time, and the FF10 value does not change within a certain time. It is determined that an error has occurred.
  • FIG. 2 shows the check circuit 100 of the unit X.
  • the unit Y and the unit Z also have a similar check circuit, and all FFs on the check circuit are initially “0”.
  • To start error checking set '1' to FF10 of unit X.
  • “1” propagates to unit Y, and “1” is set to FF10 of unit Y.
  • '1' is set to FF10 of unit Z and unit X is returned.
  • FF10 is set to '0' next, and after that, FF10 of unit X, unit Y and unit Z has' 0 ' ⁇ ' Continues changing from 1 'to' 0 '.
  • each unit is divided into a plurality of functional blocks or area blocks, and the FF10 and the check circuit 100 that perform a clock operation are provided in each functional block or each area block. Is inverted every time a clock signal is input and transmitted in a loop between functional blocks or between area blocks, and an error detection circuit determines whether the value of the shifted data changes within a predetermined time.
  • the clock can be monitored by checking. 10 and 11 show the operation of the clock monitoring mechanism according to the first embodiment at the normal time and when an error occurs.
  • the clock is monitored by propagating data that changes with the input of the clock signal in a loop between units. As described above, the clocks can be monitored between the units. Therefore, in the second embodiment, a case where the clocks are mutually monitored between the units will be described.
  • FIG. 3 is an explanatory diagram for explaining the clock monitoring mechanism according to the second embodiment. This figure shows a case where a unit U operating with an oscillator U clock and a unit V operating with an oscillator V clock different from the oscillator U mutually monitor the clock.
  • the unit U has an output circuit 211 and a check circuit 212
  • the unit V similarly has an output circuit 221 and a check circuit 222.
  • the output circuit 211 of the unit U sends out a bit that is inverted at regular intervals
  • the check circuit 222 of the unit V checks the bit sent out by the output circuit 211, while the output circuit 221 of the unit V is also fixed. Bits that are inverted every time are sent, and the check circuit 212 of the U-U checks the bit sent by the output circuit 221 so that the unit U and the unit V can be output from each other by the oscillator U or the oscillator V. Monitor the power of the clock signal for correct operation.
  • FIG. 4 is a diagram showing the output circuit 211 and the check circuit 222 shown in FIG.
  • the output circuit 211 and the check circuit 222 each include an SR (set reset) latch 21 la and an SR latch 222a that hold a check circuit valid flag indicating the start of operation.
  • SR latch 211a for check circuit valid flag of output circuit 211
  • SR latch 222a for check circuit valid flag of receiver circuit 222 Set to "1".
  • the output circuit 211 is equipped with a 3-bit incrementer 211b, and this incrementer 211b increments as long as the clock is input when the SR latch 211a for the check circuit valid flag is "1".
  • the check circuit valid flag SR latch 211a is "0" or when a change in data such as unit V force is detected, RESET is continued and increment is not performed.
  • the increment condition of the incrementer 21 lb is that the SR latch 21 lb value for the check circuit valid flag is 1 ", and the reset condition is the unit V A change in data is detected, or the value of the SR latch 211 b for the check circuit valid flag is “0”. Note that the required number of bits for the incrementer 21 lb varies depending on the period difference between oscillator U and oscillator V.
  • the output circuit 211 sends the output of the most significant bit of the incrementer 211b to the unit V via the synchronization circuit 230. Therefore, if the unit U clock is normal, the data sent to unit V will change every 4 clocks that carry the most significant bit of the incrementer 21 lb.
  • the synchronization circuit 230 is a circuit in which flip-flops that operate with a clock are directly connected, and is a circuit provided to synchronize with the clock signal of the most significant bit output of the incrementer 21 lb. The reason for synchronization is to prevent FF malfunction due to metastable phenomenon. Metastable is a phenomenon in which the output of FF stays at a potential near the threshold for a long time.
  • a metastable occurs, it will not only cause malfunction but also cause deterioration of the element.
  • the metastable phenomenon occurs at the output. Can be reduced to a practically acceptable level.
  • the check circuit 222 of the unit V also has a 3-bit incrementer 222b.
  • the incrementer 222b is incremented as long as the SR latch 222a for the check circuit valid flag is "1", and the SR latch 222a for the check circuit valid flag is "0". Or, if a change in data from unit U is detected, it will continue to be reset and will not increment.
  • the increment condition of the incrementer 222b is a value 1 ”of the SR latch 222b for the check circuit valid flag, and the reset condition is that a change in the unit U force data is detected or the check circuit valid flag This means that the value of SR latch 222b is 0.
  • the number of bits required for incrementer 222b varies depending on the period difference between oscillator U and oscillator V.
  • the error detection circuit 222c is a circuit that detects an error by decoding that the value of the incrementer 222b is "111". When an error is detected, the error detection circuit 222c has no relation to the oscillator U and the oscillator V. Report the error to a circuit that can operate in
  • the incrementer 21 lb of the output circuit 211 of the unit U increments based on the clock input and sends the most significant bit to the check circuit 22 2, so that the output circuit 211
  • the incrementer 222b of the check circuit 222 is reset when the data sent from the controller changes, and the error detection circuit 222c reports an error when the value of the incrementer 222b reaches "111". Can be monitored.
  • FIG. 5 is a diagram showing mutual monitoring of clocks in three units. As shown in the figure, in the three units of unit p, unit Q, and unit R, the data sent by the output circuit of unit P is checked by the check circuit of unit Q, and the data sent by the output circuit of unit Q By checking the unit R check circuit and checking the data sent by the unit R output circuit by the unit P check circuit, the clock operation can be monitored between the three units.
  • FIG. 8 is a timing chart showing the normal operation
  • FIG. 9 is a timing chart showing the operation when an error occurs.
  • output clock is the output of oscillator U in FIG. 3
  • output circuit start-flag is the output of SR latch 21 la for the check circuit valid flag on unit 211 in FIG. If the value is 0, the 3BIT incrementer 21 lb counts. If the value is 1, the 3B IT incrementer 21 lb continues to be reset to stop counting.
  • Out CT refers to the value of 21 lb of 3BIT incrementer in unit 211 which is the output side counter of FIG. “CTO, CT1, 012” indicates the bit 0 output, bit 1 output, and bit 2 output of 381 Cincrementer 2111), respectively.
  • “Receiver clock” is the output of oscillator V in Fig. 3.
  • “Synchronization” is due to multistage FFs. 4 represents the process of signal synchronization in the synchronization circuit 230 of FIG. 4, and the waveforms of the first, second, third, and fourth stages from the top are respectively the first stage of the synchronization circuit 230 Synchronized FF, second-stage synchronization FF, third-stage synchronization FF, and fourth-stage synchronization FF.
  • the waveform in the fifth row from the top represents the output of the reception FF in the reception-side unit 222 in FIG.
  • the up force in the “Synchronization” column also shows the edge trigger operation by the EOR circuit of unit 222 in FIG. In other words, the exclusive OR operation of the input and output of the fifth synchronization FF is performed by EOR, so that the rising edge of the waveform and the falling edge of the waveform are detected, and the count value of the 3BIT incrementer 222b To reset.
  • Check start flag is the output of SR latch 2 22b for check circuit valid flag on unit 222 side in FIG. 4.
  • 3BIT incrementer 222b performs a count operation and the value is 1 In this case, the count operation is stopped by continuing to reset the 3BIT incrementer 222b.
  • the unit 211 outputs the bit 2 which is the most significant bit signal of 21 lb of the 3BIT incrementer, and the most significant bit output signal is synchronized by the 4-stage FF of the “synchronization circuit 230”.
  • the “sending clock” in FIG. 9 stops (at the time of “ ⁇ ” in FIG. 9). Then, although the check circuit valid flag SR latch 21 la in Fig. 4 is set to '1', the count operation of the 3BIT incrementer 21 lb is stopped. Then, the most significant bit 2, that is, the output of “CT2” in the timing chart is fixed to “0” or “1”, and the result of the exclusive OR operation of the EOR in the receiving unit 222 Is always '0', the 3BIT incrementer 222b is not reset, and every time the oscillator V clock in Figure 3 is input, the count operation of the 3BIT incrementer 222b is performed. “010”, “CT1”, and “CT2” in the above are counted up to “111”, and as a result of decoding the counter value “111” by the error detection circuit 222c, an error is detected.
  • the present invention is not limited to this, and an abnormality in the FF control system that operates with the clock is not limited thereto. The same applies to monitoring.
  • the clock monitoring circuit, the information processing apparatus, and the clock monitoring method according to the present invention are useful for detecting an abnormality in the information processing apparatus, and particularly when the clock monitoring is required with a small amount of hardware. Suitable for! / Speak.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Manipulation Of Pulses (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

L'invention concerne un circuit de vérification (100) dans lequel, afin de surveiller les horloges d'un appareil fonctionnant en synchronisation avec ces horloges, des unités effectuant chacune une opération d'horloge sont divisées en une pluralité d'unités fonctionnelles ou régionales, dont chacune comprend un FF respectif (10) effectuant une opération d'horloge. La valeur du FF (10) du circuit de vérification (100) est inversée à des intervalles constants et transmise sur une boucle entre une unité fonctionnelle ou régionale et une autre. Un circuit (20) de détection d'erreur vérifie si la valeur renvoyée du FF (10) varie ou non dans une période de temps prédéterminée. Si aucun changement ne se produit dans la période de temps prédéterminée, ceci est considéré comme une erreur.
PCT/JP2006/317220 2006-08-31 2006-08-31 Circuit de surveillance d'horloge, appareil de traitement d'informations et procédé de surveillance d'horloge WO2008026283A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2008531937A JP4962497B2 (ja) 2006-08-31 2006-08-31 クロック監視回路、情報処理装置およびクロック監視方法
PCT/JP2006/317220 WO2008026283A1 (fr) 2006-08-31 2006-08-31 Circuit de surveillance d'horloge, appareil de traitement d'informations et procédé de surveillance d'horloge

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Application Number Priority Date Filing Date Title
PCT/JP2006/317220 WO2008026283A1 (fr) 2006-08-31 2006-08-31 Circuit de surveillance d'horloge, appareil de traitement d'informations et procédé de surveillance d'horloge

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WO2008026283A1 true WO2008026283A1 (fr) 2008-03-06

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101323940B1 (ko) 2012-04-18 2013-10-31 엘에스산전 주식회사 에이치엠아이 시스템의 알람 처리 장치 및 방법
CN112965588A (zh) * 2021-02-02 2021-06-15 核芯互联科技(青岛)有限公司 时序分批复位方法及系统

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS634365A (ja) * 1986-06-24 1988-01-09 Nec Corp マルチマイクロプロセツサにおける相互監視方式
JPH0425948A (ja) * 1990-05-22 1992-01-29 Nec Corp ウォッチドッグ・タイマ
JPH11212663A (ja) * 1998-01-29 1999-08-06 Ando Electric Co Ltd クロック信号断検出回路

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001256178A (ja) * 2000-03-14 2001-09-21 Toshiba Corp 同期式インターフェースを有する半導体集積回路およびそれを用いた同期制御システム

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS634365A (ja) * 1986-06-24 1988-01-09 Nec Corp マルチマイクロプロセツサにおける相互監視方式
JPH0425948A (ja) * 1990-05-22 1992-01-29 Nec Corp ウォッチドッグ・タイマ
JPH11212663A (ja) * 1998-01-29 1999-08-06 Ando Electric Co Ltd クロック信号断検出回路

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101323940B1 (ko) 2012-04-18 2013-10-31 엘에스산전 주식회사 에이치엠아이 시스템의 알람 처리 장치 및 방법
CN112965588A (zh) * 2021-02-02 2021-06-15 核芯互联科技(青岛)有限公司 时序分批复位方法及系统

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