WO2008018258A1 - Dispositif de stockage - Google Patents

Dispositif de stockage Download PDF

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Publication number
WO2008018258A1
WO2008018258A1 PCT/JP2007/063363 JP2007063363W WO2008018258A1 WO 2008018258 A1 WO2008018258 A1 WO 2008018258A1 JP 2007063363 W JP2007063363 W JP 2007063363W WO 2008018258 A1 WO2008018258 A1 WO 2008018258A1
Authority
WO
WIPO (PCT)
Prior art keywords
volatile memory
storage device
data
management information
file management
Prior art date
Application number
PCT/JP2007/063363
Other languages
English (en)
Japanese (ja)
Inventor
Masahiro Matsumoto
Takayuki Okinaga
Shuichiro Azuma
Shigeru Takemura
Yasuyuki Koike
Kazuki Makuni
Original Assignee
Hitachi Ulsi Systems Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ulsi Systems Co., Ltd. filed Critical Hitachi Ulsi Systems Co., Ltd.
Priority to US12/376,665 priority Critical patent/US8205034B2/en
Priority to JP2008528754A priority patent/JP4472010B2/ja
Publication of WO2008018258A1 publication Critical patent/WO2008018258A1/fr
Priority to US13/486,132 priority patent/US8504762B2/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1415—Saving, restoring, recovering or retrying at system level
    • G06F11/1441—Resetting or repowering
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7211—Wear leveling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0614—Improving the reliability of storage systems
    • G06F3/0616—Improving the reliability of storage systems in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0656—Data buffering arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Definitions

  • the present invention relates to a storage device, and relates to a technology that is effective when used for a storage device configured using, for example, a flash memory and used as a file memory.
  • Patent Document 1 discloses a storage device configured to configure a file memory having a storage capacity for a plurality of pages using a flash memory.
  • Patent Document 1 Japanese Patent Application Laid-Open No. 7-44468
  • a semiconductor non-volatile memory such as a flash memory is used as a storage medium as a replacement product of a hard disk drive (hereinafter referred to as "HDD") used as a storage device of embedded devices for consumer applications and industrial applications.
  • HDD hard disk drive
  • FMD Flash Memory Drive
  • semiconductor non-volatile memory such as flash memory has a certain limit in the number of rewrites, and when used for the file memory as described above, the number of rewrites occurs frequently in a specific storage area.
  • the access life of the magnetic head of the HDD is about 300,000 times
  • the flash memory NAND type, AND type
  • the lifetime of the storage device depends on the lifetime of the storage unit.
  • the lifetime of the storage device is a problem due to deterioration due to access to the storage unit, and determines the maximum lifetime of the storage unit.
  • NAND flash memory with a large write block size has multiple data of a size smaller than the write block size, If it occurs frequently, the write life will be reached in a short period of time.
  • the file management unit on the OS frequently rewrites, and in recent OSs, the location information is written frequently so that the history can be traced even if a failure occurs, so the storage device life is extremely short. Become.
  • an object of the present invention is to provide a storage device that realizes the improvement of the rewrite resistance of the non-volatile memory and the improvement of the data transfer rate of the writing and reading.
  • a storage device includes a non-volatile memory including a file management information unit and a data unit, a volatile memory storing file management information of the non-volatile memory, the non-volatile memory, and
  • the controller includes a controller that controls volatile memory, and a power supply holding unit that supplies power to the non-volatile memory, the volatile memory, or the controller when the power is shut off.
  • the file management information of the file management information unit in the memory is read and written to the volatile memory, and the controller is configured to read the volatile memory and read the data from the nonvolatile memory. Read and write based on the file management information of the Reading said file management information in the memory is characterized in that the writing in the nonvolatile memory.
  • FIG. 1 is a block diagram showing a schematic configuration of a storage device according to an embodiment of the present invention.
  • FIG. 2 is a memory map diagram showing an address space of a storage device according to an embodiment of the present invention. is there.
  • FIG. 4 is a block diagram showing a schematic configuration of a circuit that detects large-capacity capacitor deterioration in a storage device according to an embodiment of the present invention.
  • FIG. 5 is a flowchart showing an operation of a circuit for detecting large capacity capacitor deterioration in the storage device according to one embodiment of the present invention.
  • FIG. 6 is an explanatory view showing a determination method in a circuit for detecting large-capacity capacitor deterioration in the storage device according to one embodiment of the present invention.
  • FIG. 7 is an explanatory view showing a determination method in a circuit for detecting a large capacity capacitor deterioration in the storage device according to one embodiment of the present invention.
  • FIG. 8 is an explanatory view showing a determination method in a circuit for detecting large capacity capacitor deterioration in the storage device according to one embodiment of the present invention.
  • a storage device according to an embodiment of the present invention is a flowchart showing an operation of an emergency power-off sequence.
  • FIG. 11 is a flowchart showing an operation of power-on power supply in a storage device according to an embodiment of the present invention.
  • FIG. 12 is a block diagram showing a schematic configuration of a storage device according to an embodiment of the present invention.
  • a storage apparatus according to an embodiment of the present invention is a flowchart showing an operation of distribution by a controller.
  • a storage device is a flowchart showing an operation example of the leveling process when a 4-fold difference in the number of times of rewriting occurs.
  • FIG. 15 is an explanatory diagram showing an operation example of the leveling process in the storage device according to one embodiment of the present invention.
  • a storage device is a flowchart showing an operation example of data addition.
  • FIG. 17 is a plan view showing a layout on a substrate of a storage device according to one embodiment of the present invention.
  • FIG. 18 is a back view showing the layout on the substrate of the memory according to the embodiment of the present invention.
  • FIG. 19 is a diagram showing an example of fixing a capacitor by a spacer in the storage device according to one embodiment of the present invention.
  • FIG. 20 is a view showing an example of fixing of a capacitor by a spacer in the storage device according to one embodiment of the present invention.
  • FIG. 1 is a block diagram showing a schematic configuration of a storage device according to an embodiment of the present invention.
  • the storage device of the present embodiment is, for example, an HDD compatible storage device (Flash Memory Drive: FMD) 100, which is not particularly limited, but a non-volatile memory (flash memory etc.) 101 having a storage capacity of 512 Mbits. A large number of 32 or 64 files are installed in one package to form a file memory having a storage capacity for a plurality of pages.
  • Flash Memory Drive: FMD Flash Memory Drive
  • FMD Flash Memory Drive
  • flash memory etc. non-volatile memory
  • non-volatile memories 101 are connected to internal bus 102 through non-volatile memories IF (not shown).
  • the internal bus 102 is connected to the controller 103.
  • the controller 103 includes a control unit such as a one-chip microcomputer and an interface such as an ATA (Attachment) or a SCSI (Small Computer System Interface). Therefore, the controller 103 exchanges data, that is, writes and reads data, between the driver provided in the interface and the nonvolatile memory 101.
  • a control unit such as a one-chip microcomputer and an interface such as an ATA (Attachment) or a SCSI (Small Computer System Interface). Therefore, the controller 103 exchanges data, that is, writes and reads data, between the driver provided in the interface and the nonvolatile memory 101.
  • the package includes a power detection unit 104 for detecting a power interruption, a large capacity capacitor for securing an operating voltage at the time of power interruption, and a switch equal power.
  • a source holding unit 105 and a volatile memory (DRAM, SRAM, etc.) 106 are further provided.
  • the large capacity capacitor in the power supply holding unit 105 supplies voltage to the non-volatile memory 101, the controller 103, the volatile memory 106, and the power detection unit 104 by the accumulated charge even if an unexpected power interruption occurs on the system side. Then, the nonvolatile memory 101 operates to maintain the operating voltage until the normal termination of the nonvolatile memory 101 is possible.
  • an electric double layer capacitor is used as the large capacity capacitor.
  • non-volatile memory 101 if power is shut off on the system side due to a power failure, operation or mishandling during writing, the writing operation is interrupted.
  • data to be stored in file format storage is written as error detection and correction codes are added to a part of a group of data for the purpose of detection and correction of error bits. If it is interrupted on the way, it will become a mixed data of new and old data, so the error detection and correction code will not match either the new or old one, and reading this always results in an error. Destruction takes place. Even during the erase operation, a similar error will occur if the erase is left incomplete.
  • the large capacity capacitor has a relatively large capacity of, for example, about 0.1 F to ensure an operating voltage at which normal termination is always performed in the non-volatile memory 101 by preventing such malfunction as described above. Be made to have a value.
  • Power supply detection unit 104 receives power supply voltage V CC from the side of host 107 such as a microcomputer or the like, and detects power activation and shutoff.
  • the power detection unit 104 causes the controller 103 and the nonvolatile memory 101 to store a large capacity capacitor in the power supply holding unit 105.
  • the interface circuit in controller 103 is controlled not to respond to the above-mentioned system side power signal, and in order to maintain the signal state immediately before the power shutoff, If writing is in progress For example, the write operation can be normally completed because the write is continuously performed. Similarly, even during the erase operation, the erase operation is continued as it is, and the erase operation is normally ended.
  • the storage device 100 has, for example, the same external dimensions (70.0 ⁇ 100.0 ⁇ 9.5 mm) as the hard disk drive of 2.5 inches or the hard disk drive of 3.5 inches.
  • the connector pins mounted in the package size (101.6 x 146.0 x 25. 4 mm) and connected to the interface circuit in the controller 103 are also the above 2.5-inch hard disk drive unit or 3.5-inch
  • the same type of hard disk drive is used.
  • the storage device 100 of this embodiment is an HDD (node disk drive) compatible storage device.
  • the semiconductor non-volatile memory 101 such as a flash memory has a certain limit in the number of times of rewriting, and therefore, the semiconductor non-volatile memory 101 is rewritten when used for the file memory as described above. Focusing on the concentration of file management information such as FAT1, FAT2 and DIR in the case of PBR and FAT systems as described above, the number of rewrites in semiconductor nonvolatile memory 101 is limited. Volatile memory (RAM) 106 is used to prevent the occurrence of a specific area.
  • RAM volatile memory
  • the controller 103 determines that the address of the data input from the host 107 (1) power is 20h, which is determined as file management information, and the head address of the volatile memory 106 also accesses the area up to 20h. Is performed to update the shadow information (1).
  • the file system is a method of managing data stored in the storage device, and the management information such as software for managing and a management area provided on the recording medium is also a file system. And there is a case. Methods for creating, moving and deleting files and folders (directories) on storage devices, methods for recording data, locations of management areas and usage methods, etc. are defined.
  • a file system is provided as one of the functions of the operating system (operating system), and uses a different file system for each OS.
  • FAT File Allocation Table
  • FAT32 can handle disks of 2GB or more.
  • the same eye system as described above is applied to the non-volatile memory 101 as well.
  • data (1) in volatile memory 106 is replaced as file management information (2) to nonvolatile memory 101. That is, the data (1) of the volatile memory 106 is read out and is rewritten as the data (2) of the non-volatile memory 101. Due to such rewriting, in the non-volatile memory 101, the data recorded at the time of the power on is erased as soon as it is stored, and the shadow held in the volatile memory 106 before the power is shut off. Information (1) is written to the non-volatile memory 101 as file management information (2). By adopting such memory access, the file memory of the present invention can The file management information is updated using the volatile memory 106 each time the memory is accessed, and is transferred to the non-volatile memory 101 and held as non-volatile data before the power is shut off.
  • file management is performed each time to nonvolatile memory at the time of normal reading (at the time of reading) or updating (at the time of writing).
  • Information rewriting (erasing, writing) does not occur, and the above-mentioned limitation on the number of rewrites is not reached.
  • the management information is read and rewritten (updated) using the volatile memory, the memory access time to the non-volatile memory 101 via the internal bus 102 and the non-volatile memory interface (not shown) is compared.
  • read time and write can be shortened, and high-speed memory access as a storage device becomes possible.
  • the number of times of writing to the non-volatile memory can be reduced, or the system performance can be improved by eliminating the waiting time for writing.
  • the file management information may be transferred between the non-volatile memory 101 and the volatile memory 106 at the time of power activation and power interruption.
  • the updated file management information of the volatile memory may be transferred to the non-volatile memory 101 by a control signal inputted from the host 107 through the control line.
  • the file management information is also transferred to the non-volatile memory 101 so that the volatile information is transferred to the non-volatile memory to shut down the power supply.
  • the file control information may be transferred from the volatile memory 106 to the non-volatile memory 101 by generating the control signal at regular time intervals to update the information. In this case, when there is no update of file management information at the time of power shutdown, the power can be shut down as it is.
  • the non-volatile memory 101 is stably stabilized by the power detection unit 104 and the power holding unit 105 including a large capacity capacitor.
  • the operation for transferring and recording the updated file management information of the volatile memory 106 to the non-volatile memory 101 is included. Thereby, the reliability as the nonvolatile memory 101 can be secured. Also on It is also possible to omit the large capacity capacitors.
  • the operating voltage (VDD) of the non-volatile memory 101 and the volatile memory 106 is a low voltage in the system
  • the power supply (VCC) of the system is shut off and the non-volatile memory 101 and the volatile memory 106 also have power.
  • the non-volatile memory 101 can be terminated normally or file management information can be transferred to the non-volatile memory 101 using the time until the lower limit voltage is reached.
  • the file management information which frequently rewrites, is expanded to the volatile memory, the number of times of rewriting of the non-volatile memory can be reduced, and the number of times of writing can be reduced, whereby the life of the device can be extended. And, system performance can be improved to exchange frequently accessed file management information from volatile memory.
  • FIG. 4 is a block diagram showing a schematic configuration of a circuit that detects large-capacity capacitor deterioration in the storage device according to one embodiment of the present invention.
  • VCC is a power supply voltage supplied from the outside, and the voltage value is 5 V, for example.
  • VDD is an internal power supply voltage inside the storage device, and the voltage value is, for example, 3.5 V.
  • a current 'and voltage detection circuit 401 detects the remaining capacity of the large capacity capacitor by monitoring the current and voltage flowing into the large capacity capacitor in the power supply holding unit 105. By monitoring the current-voltage detection circuit 401, a failure mode such as a capacity decrease due to deterioration of the capacitor or a short circuit is detected.
  • the current / voltage detection circuit 401 calculates the fluctuation value of the voltage for a predetermined time, using a so-called gauge IC or the like which outputs a voltage value as a digital value.
  • the judgment is made by (1) a large potential difference when power is turned on or when power is shut off, or (2) no current flows. Do.
  • the current / voltage detection circuit 401 detects the deterioration of the large capacity capacitor, it outputs a detection signal 402 to the controller 103. In response to this signal, the controller 103 switches to a mode in which the data is not stored in the volatile memory 106.
  • a reset signal is sent to the non-volatile memory 101 to generate a sudden power consumption, and the same determination as in (1) and (2) is performed. Good.
  • FIG. 5 is a flowchart showing an operation of a circuit for detecting large capacity capacitor deterioration.
  • the current 'voltage detection circuit 401 performs power supply maintenance. The amount of current flowing into the large capacity capacitor in the holder 105 and the voltage are measured.
  • the current 'voltage detection circuit 401 outputs a detection signal 402 to the controller 103 in step S503 to report the deterioration of the large capacity capacitor. Do.
  • the controller 103 switches the operation mode. For example, data may not be stored in the volatile memory 106, or read / write may be limited.
  • the operation of the volatile memory 106 is turned on.
  • step S506 If no degradation is detected !, then in step S506, the normal mode is selected. Then, in step S505, the operation of the volatile memory 106 is turned on.
  • FIG. 6, FIG. 7, and FIG. 8 are explanatory diagrams showing determination methods in a circuit that detects large-capacity capacitor deterioration.
  • FIG. 6 shows the time variation of the voltage of the large capacity capacitor at the time of power on.
  • a waveform 601 is a waveform when the large capacity capacitor is normal
  • a waveform 602 is a waveform when the large capacity capacitor (hereinafter referred to as “capacitor”) is deteriorated.
  • tl, t2 and t3 are times indicating the timings of calculating the potential difference.
  • the voltage waveform of the capacitor at power-on changes from waveform 601 to waveform 602.
  • the potential difference with VDD is calculated at each time of tl, t2 and t3.
  • the time for achieving a predetermined potential difference is determined. That is, the deterioration of the capacitor is judged by the rise time and the potential difference.
  • FIG. 7 shows a temporal change of the voltage of the large capacity capacitor at the time of power supply cutoff (OFF).
  • a waveform 701 is a waveform when the capacitor is normal
  • a waveform 702 is a waveform when the capacitor is deteriorated.
  • tl and t2 are times indicating the timing for calculating the potential difference.
  • FIG. 8 shows the time variation of the voltage of the above-mentioned large capacity capacitor in the case of judging the deterioration of the capacitor by causing the power to be consumed suddenly by inputting the reset signal to the nonvolatile memory at the time of the read 'write operation. It shows.
  • a waveform 801 is a waveform when the capacitor is normal
  • a waveform 802 is a waveform when the capacitor is deteriorated.
  • tl and t2 are times indicating the timing for calculating the potential difference.
  • the potential difference with VDD is calculated at each timing of time tl and t2.
  • the time for which a predetermined potential difference is obtained is determined. That is, the deterioration of the capacitor is judged by the rise time and the potential difference.
  • FIG. 9 is a block diagram showing a schematic configuration of a storage device according to one embodiment of the present invention.
  • the storage device according to the present embodiment has the same configuration as that of FIG. 1, so detailed description will be omitted.
  • the address of the non-volatile memory 101 to which data is to be written is determined in advance, and is stored in the memory.
  • the memory for storing the address is the memory in the controller 103, the volatile memory 106 or the non-volatile memory 101. It has the data storage address (emergency storage address) at the time of emergency power off separately from general data.
  • the emergency storage addresses are equally allocated to the memory buses of the plurality of nonvolatile memories 101 so that data can be stored in parallel and at high speed.
  • overhead processing becomes unnecessary and processing can be performed at high speed.
  • FIG. 10 is a flowchart showing the operation of the emergency power-off sequence.
  • Step S1 If an unexpected power off occurs at 001, the process proceeds to an emergency power off sequence at step S1002.
  • step S1003 the data stored in the internal RAM or volatile memory 106 is moved to the Flash memory or non-volatile memory 101. At this time, data is moved to a predetermined emergency storage address in the plurality of nonvolatile memories 101 in a distributed manner.
  • the controller 103 moves the file management information in the non-volatile memory (Flash memory) 101 managed in a block separate from the data to the volatile memory 106 (RAM) and saves it. Do. At the time of memory operation, file management information is managed in the volatile memory 106, and is written back to the nonvolatile memory 101 at the time of power off (power off).
  • Flash memory non-volatile memory
  • data that is expected to be frequently accessed is also moved from the nonvolatile memory 101 to the volatile memory 106 when the controller 103 is powered on.
  • non-defective non-defective product of the sector of the corresponding non-volatile memory (2) logical address, (3) in-chip address, (4) number of rewrites, (5) ECC information , (6) Location of data, (7) Failure occurrence history, etc.
  • FIG. 11 is a flowchart showing an operation of the power on Z power off sequence.
  • step S 1101 When the power is turned on at step S 1101, the file management information of the flash, ie, the nonvolatile memory 101 is moved to the RAM, ie, the volatile memory 106 and stored at step S 1102. In step S 1103, normal operations such as memory read / write are performed. In step S 1104, when the power is turned off, ie, the power is turned off, the file management information in the RAM, ie, the volatile memory 106 is moved to the Flash, ie, the non-volatile memory 101 and saved in step S 1105. At the time of data storage, the power of the capacitor in the power supply holding unit 105 is also obtained.
  • FIG. 12 is a block diagram showing a schematic configuration of a storage device according to one embodiment of the present invention. Ru.
  • the storage device according to the present embodiment has the same configuration as that of FIG. 1, so detailed description will be omitted.
  • the controller 103 has a mechanism for distributing the write destination to the volatile memory 106 or the nonvolatile memory 101 when a write (write) command is generated from the host 107. Determination of distribution by the controller 103 is performed based on the following criteria.
  • FIG. 13 is a flowchart showing the operation of distribution by the controller 103.
  • the controller 103 determines the data size in step S1302. At this time, in addition to the data size, determination of the data rewrite frequency, the sufficiency rate in block units, etc. is also performed according to the determination criteria of (1) to (3) above. Then, if the data size is, for example, 1Z2 block or more, after adding the ECC in step S1306, the process proceeds to step S1303, and the data is stored in Flash, ie, the nonvolatile memory 101. If the data size is smaller than, for example, 1/2 block, ECC is added in step S1307, and then the process proceeds to step S1304, where the data is stored in the RAM, ie, the volatile memory 106.
  • the controller 103 determines the number of rewrites from the file management data of the non-volatile memory 101 stored in the RAM, that is, the volatile memory 106, and performs equalization processing, that is, equalization processing. That is, the data is moved between the volatile memory 106 and the non-volatile memory 101 according to the number of times data is rewritten in the non-volatile memory 101, the number of ECC correction bits, etc., and the controller 103 carries out the leveling process.
  • FIG. 14 is a flow chart showing an operation example of the leveling process when there is a 4-fold difference in the number of rewrites.
  • an arbitrary block is selected in step S1401. Specifically, the center address block is selected by (Timer) X (RANDOM) in the corresponding chip area in the area of the file management information.
  • (RANDOM) is an arbitrary random number.
  • step S 1402 based on the information on the number of times of rewriting of the file management information in the RAM, ie, the volatile memory 106, 2 blocks for every 256 blocks, for a total of 16 blocks, are selected and written. Check if there is a replacement block or not.
  • step S 1403 If there is no rewrite block, the block with the least rewrite is selected in step S 1403, and the data is written to the non-volatile memory 101. If there is an already rewritten block, the parameter is confirmed in step S 1404, and “Do not rewrite already written block” is selected to confirm whether or not it is possible.
  • step S 1405 compare (the number of rewrites of already written blocks) X 4 with (unwritten blocks). And select the block with the least writing. If this block is a write-in block, equalization processing is performed, data is moved to the RAM, ie, volatile memory 106, and data is written after erasure. Next, the already written data is written back to the unwritten area where rewriting is less.
  • FIG. 15 is an explanatory view showing an operation example of the leveling process.
  • RAM is volatile memory 106
  • Flash is non-volatile memory 101.
  • the leveling process is performed according to the following procedure.
  • the controller 103 searches for 16 rewrite destinations.
  • the controller 103 When writing data to the non-volatile memory 101, the controller 103, in one block of the non-volatile memory 101, free pages of the non-volatile memory 101 in page units only for data to be added instead of rewriting the entire block. And update the file management information in the volatile memory 106. By refraining from rewriting the entire block of the non-volatile memory 101, the rewriting resistance can be improved.
  • the above-mentioned additional writing writes and arranges only the latest page of the same address when the block occupancy rate rises (for example, when 100 KB of 128 KB is written, 56 pages of 64 pages, etc.)
  • FIG. 16 is a flow chart showing an operation example of data addition in the storage device according to one embodiment of the present invention.
  • the controller 103 checks whether the additional writing to the non-volatile memory 101 is possible based on the file management information. If appending is not possible, in step S1603, the controller 103 executes the normal rewriting sequence without appending to the non-volatile memory 101. If additional writing is possible, the controller 103 writes data to a free page in the same block of the non-volatile memory 101 in step S 1604. Then, in step S1605, the sufficiency rate in the block is confirmed.
  • step S1606 For example, in the case of 100 KBZ 128 KB or more, in step S1606, only the latest page is written and organized. Then, in step S1607, the file management information in the RAM, that is, the volatile memory 106 is updated. On the other hand, if the filling rate power in the block is, for example, 100 KB, 128 KB or less, the process proceeds to step S1608, and the appending operation is finished.
  • the storage device has a function of outputting the number of remaining blocks. That is, in response to a request command from the host 107, the controller 103 calculates the number of remaining blocks based on the file management information in the volatile memory 106, and returns it to the host 107. The host 107 can recognize the lifetime of the non-volatile memory 101 by returning the number of remaining blocks.
  • FIG. 17 is a plan view showing a layout on a substrate of a storage device according to one embodiment of the present invention
  • FIG. 18 is a rear view thereof.
  • the storage device includes a 2.5-inch (70.0 ⁇ 100.0 ⁇ 9.5 mm) outer shape, a large capacity capacitor 1705 (power holding unit 105) for holding a power supply, a flash (nonvolatile memory 101), With controller 103, RAM (volatilization '14 memo! J 106).
  • a 2.5-inch (70.0 ⁇ 100.0 ⁇ 9.5 mm) outer shape a large capacity capacitor 1705 (power holding unit 105) for holding a power supply
  • a flash nonvolatile memory 101
  • RAM volatile memory
  • FIG. 17 eight non-volatile memories 101 and four electric double layer capacitors 1705 constituting a power supply holder 105 are disposed on the surface of a substrate 1700.
  • eight non-volatile memories 101, a controller 103 and a volatile memory (RAM) 106 are disposed on the back surface of the substrate 1700.
  • the capacitor 1705 of the power supply holding unit 105 is structured to maintain vibration resistance by a spacer.
  • the spacer has a structure that can be fixed to the substrate by screwing or the like, or a non-fixed shape that can only be inserted into the substrate.
  • FIG. 19 and FIG. 20 are diagrams showing an example of fixing of a capacitor by a spacer.
  • FIG. 19 shows an array of sandwiching an optical fiber 1705 between a substrate 1700, an outer race 1901 and a spacer 1902.
  • FIG. 20 shows an example in which a capacitor 1705 is sandwiched between a die 2001, a spacer 1902, a substrate 1700 and a nut 2002. Insert the protrusions of the spacer 1902 into the boss holes of the substrate 1700 and fix them.
  • the material of the spacer 1902 is liquid crystal resin, polycarbonate, non-conductive material or the like. By adopting such a structure, the vibration resistance of the capacitor is improved.
  • Erasable non-volatile memory can be used as the non-volatile memory 101, in addition to the above-described FlasM flash memory.
  • the address when loading a certain amount of data from the non-volatile memory to the volatile memory from the start address Oh at the time of startup may be any address compatible with the file system such as 100 h (128 KB) other than the 2 Oh.
  • the package can be applied to smaller and thin card in addition to the same as the external size of the HDD.
  • the present invention can be widely used as a storage device adopting a file system using a non-volatile memory.

Abstract

L'invention concerne un dispositif de stockage permettant d'améliorer la tolérance d'écriture d'une mémoire non volatile et le taux de transfert de données pour des opérations d'écriture et de lecture. Ce dispositif mémoire comprend une mémoire non volatile (5), une mémoire volatile (106) destinée à stocker des informations de gestion de fichiers de la mémoire non volatile (101), un contrôleur (103) destiné à commander la mémoire non volatile (5) et la mémoire volatile (106), et une unité de conservation de puissance permettant d'alimenter en énergie la mémoire volatile (106) ou le contrôleur (103) lorsqu'une source électrique est coupée. Le contrôleur (103) lit les informations de gestion de fichiers stockées dans la mémoire non volatile (5) et écrit ces informations dans la mémoire volatile (106) lorsque la source électrique alimente. Quant aux opérations de lecture et d'écriture, ces opérations sont effectuées conformément aux informations de gestion de fichiers stockées dans la mémoire volatile (106). Lorsque la source électrique est coupée, les informations de gestion de fichiers stockées dans la mémoire volatile (106) sont lues et écrites dans la mémoire non volatile (101).
PCT/JP2007/063363 2006-08-09 2007-07-04 Dispositif de stockage WO2008018258A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US12/376,665 US8205034B2 (en) 2006-08-09 2007-07-04 Flash memory drive having data interface
JP2008528754A JP4472010B2 (ja) 2006-08-09 2007-07-04 記憶装置
US13/486,132 US8504762B2 (en) 2006-08-09 2012-06-01 Flash memory storage device with data interface

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JP2006217436 2006-08-09
JP2006-217436 2006-08-09

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US12/376,665 A-371-Of-International US8205034B2 (en) 2006-08-09 2007-07-04 Flash memory drive having data interface
US13/486,132 Continuation US8504762B2 (en) 2006-08-09 2012-06-01 Flash memory storage device with data interface

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US8205034B2 (en) 2012-06-19
JP4472010B2 (ja) 2010-06-02
US20100180068A1 (en) 2010-07-15
JPWO2008018258A1 (ja) 2009-12-24
US8504762B2 (en) 2013-08-06
US20120239865A1 (en) 2012-09-20

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