WO2011081168A1 - Dispositif de disque électronique, et procédé de sauvegarde / rétablissement d'informations de gestion de mise à niveau - Google Patents

Dispositif de disque électronique, et procédé de sauvegarde / rétablissement d'informations de gestion de mise à niveau Download PDF

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Publication number
WO2011081168A1
WO2011081168A1 PCT/JP2010/073670 JP2010073670W WO2011081168A1 WO 2011081168 A1 WO2011081168 A1 WO 2011081168A1 JP 2010073670 W JP2010073670 W JP 2010073670W WO 2011081168 A1 WO2011081168 A1 WO 2011081168A1
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Prior art keywords
management information
data
leveling management
storage unit
chip
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PCT/JP2010/073670
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English (en)
Japanese (ja)
Inventor
譲 高橋
雅裕 白石
西村　卓真
松田　光司
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株式会社日立製作所
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1415—Saving, restoring, recovering or retrying at system level
    • G06F11/1441—Resetting or repowering

Definitions

  • the present invention provides a solid state drive device (hereinafter abbreviated as an SSD device) that is a storage device configured using a nonvolatile semiconductor memory, and a method for leveling the number of data rewrites in the storage area of the SSD device.
  • the present invention relates to a method for saving / restoring leveling management information used in the system.
  • An SSD device that replaces a hard disk device using a flash memory, which is a nonvolatile semiconductor memory.
  • An SSD device is generally considered to be fast and highly reliable because it does not require any movable parts essential for a hard disk device.
  • the flash memory has a fatigue phenomenon associated with data writing and erasing, and the number of times data is rewritten to the memory cell is normally 100,000 times.
  • the number of times data is rewritten to the memory cell is normally 100,000 times.
  • it does not necessarily take a long time to rewrite data in a specific storage area of the flash memory in the SSD device 100,000 times. This impairs the merit of the SSD device that is highly reliable because there are no moving parts.
  • Patent Document 1 As shown in Patent Document 1, Patent Document 2, and the like, there are various wear leveling methods.
  • information used for wear leveling such as an address conversion table is collectively referred to as leveling management information.
  • the leveling management information is often stored in a predetermined storage area of a flash memory constituting the SSD device (see, for example, Patent Document 2).
  • the address translation table is used for high-speed DRAM (Dynamic Random Access Memory). May be remembered.
  • the SSD device needs to load the leveling management information including the address conversion table into the DRAM every time the power is turned on. Further, when the leveling management information changes from time to time, for example, with the past history, the SSD device stores the leveling management information stored in the DRAM in a nonvolatile manner every time the power is turned off. It is necessary to save it in a flash memory.
  • leveling management information is stored in a volatile memory and rewritten from time to time
  • the leveling management information is saved or restored each time the power is turned off or on. Is executed.
  • an SSD device is a large-capacity storage device of several tens GB to several hundred GB, its leveling management information may extend to several tens of MB. Also, sudden power outage must be taken into account when turning off the power. That is, in the leveling management information saving / restoring process in the SSD device, a large amount of leveling management information of several tens of megabytes is stored in the nonvolatile memory within a short time (eg, 0.3 to 0.5 seconds). Evacuation is a major issue to be solved.
  • An object of the present invention is to provide an SSD device capable of saving a large capacity leveling management information in a nonvolatile memory in a short time and a method for saving and restoring the leveling management information. .
  • a solid state drive (SSD) device includes a nonvolatile data storage unit including a plurality of nonvolatile memory chips, a control for writing external data to the nonvolatile data storage unit, and a nonvolatile data storage unit.
  • a nonvolatile data storage control unit that performs control to read out written data, and the nonvolatile data storage unit is divided into a plurality of lanes each including one or more nonvolatile memory chips.
  • each of the lanes includes a buffer storage control unit that temporarily stores data to be written to the nonvolatile memory chip belonging to the lane and data read from the nonvolatile memory chip belonging to the lane.
  • the non-volatile data storage control unit stores the leveling management information.
  • a memory unit a power supply on / off detection unit that detects on / off of power supply, and leveling management information that saves or restores leveling management information when power supply off / on is detected
  • An evacuation / recovery processing unit when the leveling management information save / restore processing unit saves the leveling management information to the non-volatile data storage unit, the leveling management information is saved in the respective lanes via the buffer storage control unit. It is characterized in that data is simultaneously written in parallel to the non-volatile memory chip to which it belongs.
  • writing data to a nonvolatile memory takes a long time compared to data reading.
  • the leveling management information read and saved from the leveling management information storage unit is stored in each of a plurality of lanes.
  • each lane can be written to the nonvolatile memory chips belonging to the lane in parallel independently of each other. Therefore, the time required for saving the leveling management information is shortened.
  • a solid-state drive device capable of saving large-capacity leveling management information in a nonvolatile memory in a short time and a method for saving and restoring the leveling management information are provided. Is possible.
  • An example of how the leveling management information data stored in the WM of the leveling management information storage unit is saved to each NVM chip when the leveling management information is saved to the NVM chip according to the basic transfer procedure shown in FIG. Figure.
  • FIG. 7 is a time chart illustrating a data transfer procedure performed in the leveling management information saving process and recovery process described with reference to FIGS. 4 and 6;
  • FIG. 1 is a diagram showing an example of the configuration of an SSD device according to an embodiment of the present invention. As shown in FIG. 1, an SSD device 1 is used by being connected to a host device 2 that is an external device for itself via a host bus 3.
  • a host device 2 that is an external device for itself via a host bus 3.
  • the host device 2 is a so-called computer, or various types of information processing devices, control devices, terminal devices, and the like using the computer.
  • the host bus 3 includes IDE (Integrated Drive Electronics), SCSI (Small Computer System Interface), SATA (Serial Advanced Technology Attachment), SAS (Serial Attached SCSI), USB (Universal Serial Bus), and the like.
  • the SSD device 1 includes a nonvolatile data storage unit 20 and a nonvolatile data storage control unit 10.
  • the nonvolatile data storage unit 20 is configured to include a plurality of NVM (Non-Volatile Memory) chips 23 composed of a flash memory which is a nonvolatile memory, and stores data supplied from the host device 2 in a nonvolatile manner.
  • the nonvolatile data storage control unit 10 basically writes data supplied from the host device 2 to the NVM chip 23 and writes to the NVM chip 23 in response to a request from the host device 2. Control to read data.
  • the nonvolatile data storage control unit 10 includes a data write / read control unit 11, a leveling management unit 12, a leveling management information storage unit 13, a leveling management information save / recovery processing unit 14, and a power on / off detection unit 15. Consists of.
  • the data write / read control unit 11 receives commands such as a data write request and a data read request to the SSD device 1 transmitted from the host device 2 via the host bus 3. If the command is a data write request, the logical address and write data transmitted from the host device 2 following the command are received, the logical address is converted into the physical address of the NVM chip 23, The received write data is written to the NVM chip 23 designated by the converted physical address. When the command is a data read request, the logical address transmitted from the host device 2 following the command is converted into the physical address of the NVM chip 23, and the NVM chip 23 specified by the converted physical address. The data is read from the host device, and the read data is transmitted to the host device 2.
  • commands such as a data write request and a data read request to the SSD device 1 transmitted from the host device 2 via the host bus 3. If the command is a data write request, the logical address and write data transmitted from the host device 2 following the command are received, the logical address is converted into the physical address of the NVM chip 23, The received write data
  • the leveling management information storage unit 13 is specified by a logical / physical conversion table used when the data writing / reading control unit 11 converts a logical address to a physical address, or a physical address of the NVM chip 23 and its physical address. Information such as the number of times data is rewritten (erased) in the storage area is stored.
  • the leveling management information storage unit 13 is assumed to be configured by a DRAM which is a volatile semiconductor memory.
  • the leveling management unit 12 monitors the command executed by the data writing / reading control unit 11 and updates the number of times data is erased in each storage area of the NVM chip 23 in the leveling management information storage unit 13. In order to equalize the number of erasures, the logical / physical conversion table is changed as appropriate.
  • the leveling management information including the logical / physical conversion table is any information as long as it is changed every predetermined time or every time a predetermined condition is satisfied. It may be. Therefore, the conditions for changing the leveling management information and the logical / physical conversion method are not particularly limited.
  • the power on / off detection unit 15 detects disconnection (off) and on (on) of the power supply supplied to the SSD device 1.
  • the SSD device 1 has a power supply circuit (not shown), and a predetermined time (for example, after the power supply on / off detection unit 15 detects the power supply off by a capacitor provided in the power supply circuit). , 0.3 to 0.5 seconds), it is assumed that a voltage and a current for the SSD device 1 to operate normally are supplied.
  • the leveling management information save / recovery processing unit 14 stores the leveling management information stored in the leveling management information storage unit 13 when the power on / off detection unit 15 detects that the power supply to the SSD device 1 is off. Information is saved in a predetermined area of the storage area of the NVM chip 23 in the nonvolatile data storage unit 20. Further, the leveling management information save / restore processing unit 14 stores the leveling management information saved in the NVM chip 23 in the leveling management information storage unit 13 when it is detected that the power supply to the SSD device 1 is turned on. Recover.
  • the buffer storage control unit 22 of each lane 21 and the NVM chip 23 belonging to the lane 21 are connected by a chip connection bus 24. Further, the buffer storage control unit 22 and the nonvolatile data storage control unit 10 of each lane 21 are connected by a lane connection bus 30.
  • the leveling management information save / recovery processing unit 14 has a defective block information table 141 and a failed chip information table 142 therein, the details of which will be described later. Further, detailed processing procedures for saving and restoring the leveling management information will be sequentially described in this specification.
  • the nonvolatile data storage unit 20 is configured to include a plurality of NVM chips 23, and the plurality of NVM chips 23 are grouped by lanes 21. In this embodiment, eight lanes 21 are provided, and each lane 21 includes a buffer storage control unit 22 and three NVM chips 23 that operate independently.
  • the buffer storage control unit 22 includes a buffer memory (BM: see FIG. 4 and the like) configured by a high-speed RAM and the like, and temporarily stores write / read data to / from the NVM chip 23 in the buffer memory. Data write / read timing adjustment to the NVM chip 23 is performed.
  • BM buffer memory
  • FIG. 2 is a diagram showing an example of the configuration of the NVM chip 23.
  • the NVM chip 23 is a so-called flash memory.
  • the storage area of one NVM chip 23 is divided into a plurality of blocks 231, and each block 231 has a plurality of pages 232 (for example, , 64 pages).
  • each page 232 is provided with a storage area for storing 4 kB of data.
  • one NVM chip 23 has approximately 16000 pieces.
  • a block is provided.
  • 14 blocks are used as a save data storage area for saving the leveling management information, and the remaining blocks are used to store external data (data supplied from the host device 2). Used as an external data storage area.
  • the configuration of the block 231 and the page 232 in these NVM chips 23 is derived from the structure of the flash memory itself and the read / write method thereof, and the following restrictions are imposed on the read / write of the data.
  • (1) Data reading / writing is performed in units of pages 232.
  • (2) Data is erased in units of block 231.
  • the writing or reading of the saved data with respect to the NVM chip 23 is performed in units of pages 232 having the format shown in FIG.
  • the page 232 includes a header 233 and eight segments 234 each including 512B of saved data.
  • a check code 235 such as a CRC (Cyclic Redundancy Check) code or a Reed-Solomon code is added to the saved data of each segment 234.
  • the header 233 is an address (hereinafter referred to as this specification) when the head data of the leveling management information for one page (4 kB) to be saved is stored in the leveling management information storage unit 13. In this case, this address is referred to as a saved data start address).
  • the page 232 has a storage area for storing 4 kB of data, but actually (physically) has a storage area of 4 kB + ⁇ .
  • + ⁇ is about 200 to 256 B, but the header 233 and the check code 235 are stored using the storage area portion of + ⁇ .
  • FIG. 3 is a diagram showing an example of the configuration of the storage areas of the leveling management information storage unit 13 and the NVM chip 23.
  • the leveling management information storage unit 13 stores additional saving information and a checksum for the combined data, and the leveling management information is saved in the NVM chip 23. When this is done, all these data are saved.
  • the additional save information refers to data stored in various registers, the defective block information table 141, the failed chip information table 142, and the like included in the leveling management information save / recovery processing unit 14.
  • the leveling management information save / restore processing unit 14 first stores the additional save information such as the defective block information table 141 in the leveling management information storage. After being stored in the unit 13, all data stored in the leveling management information storage unit 13 is saved to the NVM chip 23 as save data.
  • the total capacity of data stored in the leveling management information storage unit 13 is 48 MB, and the 48 MB of data is distributed to 24 NVM chips 23 and saved.
  • a total of 84 MB of the save data storage area is prepared for the 24 NVM chips 23 as a whole, of which 48 MB is the basic save area and 36 MB is the reserve save area. That is, for each NVM chip 23, 512 pages (8 blocks) are used as a basic save area, and 384 pages (6 blocks) are used as a reserve save area.
  • the 896 page saved data storage area is fixedly allocated to the physical page addresses (# 0) to (# 895) in each NVM chip 23.
  • the spare save area if any of the 24 NVM chips 23 is a faulty chip, the save data to be saved in the faulty chip is distributed to the spare save area of each NVM chip 23. And evacuated. In addition, when there is a defective block in the NVM chip 23 or when a page write error occurs when writing data to the NVM chip 23, an extra save area is required accordingly.
  • the leveling management information is spread and stored in the preliminary save area.
  • the leveling stored in the leveling management information storage unit 13 in the case where none of the failed chip, the defective block, and the page writing error is present in the NVM chip 23.
  • a procedure for saving or restoring the management information to the NVM chip 23 will be described.
  • the leveling management information when the leveling management information is simply referred to, not only all the data stored in the leveling management information storage unit 13, that is, the leveling management information shown in FIG. It shall include evacuation information and checksum.
  • the leveling management information when saved or restored is often referred to as saved data or restored data.
  • FIG. 4 is a diagram showing an example of the basic transfer procedure of the save data performed in the leveling management information save process when the NVM chip 23 at the save destination does not have any faulty chip, bad block, or page write error. is there.
  • the arrow indicates the transfer direction of the saved data, and the numbers in parentheses beside the arrow indicate the order in which the transfer is performed.
  • the leveling management information storage unit 13 includes a WM (wear leveling memory) 130 composed of a DRAM or the like, and the buffer storage control unit 22 has a storage capacity of one page (4 kB).
  • BM buffer memory 220.
  • the WM 130 may be substantially regarded as the leveling management information storage unit 13 itself. However, in this specification, a part made up of a volatile memory such as a DRAM that constitutes the leveling management information storage unit 13 is particularly described. , Called WM130.
  • Transfer of saved data from the WM 130 to the NVM chip 23 is performed in units of one page of data (4 kB) under the control of the leveling management information save / restore processing unit 14. That is, the leveling management information save / restore processing unit 14 first reads the saved data for the first page from the WM 130, and reads the saved data as BM 220 (hereinafter referred to as BM (#). (Referred to as transfer order (1)). At this time, the saved data for one page transferred to the BM (# 0) is temporarily stored in the BM (# 0).
  • the leveling management information save / restore processing unit 14 uses the address when the top data of the save data is stored in the WM 130 when transferring the save data for one page, that is, the save data start address. At the same time, the data is transferred to BM (# 0).
  • the leveling management information save / restore processing unit 14 sends the saved data for one page temporarily stored in the BM (# 0) to the buffer storage control unit 22 having the BM (# 0). Instruct to transfer to the NVM chip 23 described as (# 0) (hereinafter abbreviated as NVM (# 0)). Then, the buffer storage control unit 22 having the BM (# 0) having received the transfer instruction adds the header 233 (saved data start address) and the saved data for one page temporarily stored in the BM (# 0) and A check code 235 for each save data 512B is added and transferred to NVM (# 0) (see transfer order (2)). The saved data transferred to the NVM (# 0) is written in the area of the page (# 0) of the NVM (# 0).
  • the leveling management information save / restore processing unit 14 instructs the buffer storage control unit 22 having the BM (# 0) to transfer the saved data to the NVM (# 0) in the above processing
  • the process proceeds to the next process without waiting for the end of the transfer. That is, the leveling management information save / restore processing unit 14 reads the saved data for the next one page from the WM 130 and transfers the read saved data to the BM (# 1) (see transfer order (3)). .
  • the transferred save data is temporarily stored in the BM (# 1). At the time of the transfer, the saved data start address is also transferred.
  • the leveling management information save / restore processing unit 14 sends the saved data for one page temporarily stored in the BM (# 1) to the buffer storage control unit 22 having the BM (# 1). Instruct to transfer to (# 1).
  • the buffer storage control unit 22 including the BM (# 1) stores the header 233 (saved data start address) and the saved data in the saved data for one page temporarily stored in the BM (# 1).
  • a check code 235 for each data 512B is added and transferred to the NVM (# 1) (see transfer order (4)).
  • the leveling management information saving / restoring processing unit 14 and the buffer storage control unit 22 store the saved data indicated by the transfer orders (5), (6),..., (47), (48). Perform the transfer. Then, due to the transfer of the save data shown in the transfer order (1) to (48), predetermined save data is saved in each page (# 1) of NVM (# 0) to NVM (# 23). It will be.
  • FIG. 5 shows that the leveling management information stored in the WM 130 of the leveling management information storage unit 13 is transferred to each NVM chip 23 when the leveling management information is saved to the NVM chip 23 according to the basic transfer procedure shown in FIG. It is the figure which illustrated a mode that it was evacuated.
  • the WM 130 is divided by data for one page (4 kB), and the chip number and page address of the NVM chip 23 serving as a transfer destination are described in the divided section.
  • the head address of the section is described on the left side of each section. This start address is included in the header 233 of the data of the page 232 written to each NVM chip 23 as the save data start address.
  • the section of the save source WM 130 and the page of the save destination NVM chip 23 are connected by arrows.
  • the numbers in parentheses attached to the side of the arrow are the same as the numbers in parentheses in FIG. 4 and mean the data transfer order. However, in order to avoid complication of the figure, the numbers representing the transfer order are given only to some arrow lines.
  • FIG. 6 is a diagram showing an example of a recovery data basic transfer procedure performed in the recovery processing of the leveling management information in the case where none of the failed chip, the defective block, and the page write error exists in the save destination NVM chip 23. is there.
  • the recovery data refers to leveling management information saved in the NVM chip 23.
  • the arrow indicates the transfer direction of the recovery data, and the numbers in parentheses beside the arrow indicate the order in which the transfer is performed.
  • the leveling management information save / restore processing unit 14 first instructs the buffer storage control unit 22 of each lane 21 to read the recovery data from the NVM chip 23.
  • the buffer storage control unit 22 of each lane 21 reads the recovery data for one page from the NVM (# 0) to NVM (# 7), and each of the read recovery data is BM (# 0). Transfer to BM (# 7) (see transfer order (1)).
  • the transferred recovery data is temporarily stored in BM (# 0) to BM (# 7).
  • the time during which the eight buffer storage control units 22 receive the recovery data read instruction from the leveling management information saving / recovery processing unit 14 is determined by the buffer storage control unit 22 from NVM (# 0) to NVM (# 7). Since the recovery data is read out and transferred to BM (# 0) to BM (# 7), the recovery data is transferred almost simultaneously at the same time from the NVM chip 23 to the BM 220 in each lane 21.
  • the leveling management information save / restore processing unit 14 sequentially transfers the recovery data temporarily stored in the BMs (# 0) to (# 7) to the WM 130 (transfer order (2) to (9)). And store the original address of the WM 130.
  • the leveling management information save / recovery processing unit 14 can easily store the recovery data transferred from the BMs (# 0) to (# 7) at the original address of the WM.
  • the leveling management information save / restore processing unit 14 instructs the buffer storage control unit 22 of each lane 21 to read the next recovery data from the NVM chip 23, and receives the instruction,
  • the buffer storage control unit 22 of each lane 21 reads the recovery data for one page from the NVM (# 8) to NVM (# 15), and the read recovery data is BM (# 0) to BM (# 7), respectively. (Refer to the transfer order (10)) and temporarily stored in BM (# 0) to BM (# 7), respectively.
  • the leveling management information save / restore processing unit 14 sequentially transfers the recovery data temporarily stored in the BMs (# 0) to (# 7) to the WM 130 (transfer order (11) to (18)). And store the original address of the WM 130.
  • the leveling management information save / restore processing unit 14 and the buffer storage control unit 22 read the recovery data for the next one page from NVM (# 16) to NVM (# 23), and read the read data. , Transfer to WM 130 via BM (# 0) to BM (# 7) (see transfer order (19) to (27)).
  • the recovery data transfer shown in the transfer order (0) to (27) the data saved in the respective pages (# 0) of NVM (# 0) to NVM (# 23) is recovered to the WM 130. That's right. Further, by repeating the transfer of the recovery data shown in the transfer order (0) to (27) 511 times, the respective pages (# 1) to (# 511) of NVM (# 0) to NVM (# 23) are repeated. The data saved in the WM is restored to the WM.
  • FIG. 7 is a time chart showing the data transfer procedure performed in the leveling management information saving process and the recovery process described with reference to FIGS. 4 and 6, and FIG. A time chart (b) is a time chart during the recovery process.
  • the horizontal direction indicates a time axis
  • each stage in the vertical direction is a horizontal direction in which data transfer operations related to each NVM chip 23 (NVM (# 0) to (# 23)) are shaded. Shown in the bar.
  • the unit process includes [1] an operation in which the leveling management information save / restore processing unit 14 transfers save data for one page from the WM 130 to the BM 220 (using the lane connection bus 30), [2] The buffer storage control unit 22 transfers the saved data for one page to the BM 220 (using the chip connection bus 24 of each lane 21), and [3] the NVM chip 23 programs the saved data for one page (here)
  • the program is an electrical / physical write operation of data to the storage cell of the flash memory). That is, the unit saving process from reading the saving data for one page from the WM 130 to writing it to the NVM chip 23 is constituted by the operation of [1] + [2] + [3].
  • the unit processing is [4] operation in which the buffer storage control unit 22 reads recovery data for one page from the NVM chip 23 and transfers it to the BM 220 (using the chip connection bus 24 in each lane 21). ), [5]
  • the leveling management information save / restore processing unit 14 transfers the recovery data for one page from the BM 220 to the WM 130 (using the lane connection bus 30). That is, the unit recovery process from reading the recovery data for one page from the NVM chip 23 to returning it to the WM 130 is constituted by the operation of [4] + [5].
  • FIGS. 7A and 7B the numbers in parentheses described above the shaded horizontal bars represent the transfer order of save or recovery data, and FIG. 4 (save process) and FIG. This is associated with the transfer order of the numbers in parentheses in No. 6 (recovery process).
  • the operation [2] can substantially reduce the operation time to 1/8 of the original, and the operation [3] can reduce the operation time to the original 1/24.
  • the saving process is performed in the transfer order indicated by the numbers in parentheses in FIGS. 4 and 7A, and the operation times of the operations [1], [2], and [3] are respectively expressed as T1, T2, T3.
  • T2 ⁇ T1 ⁇ 8 and T2 + T3 ⁇ T1 ⁇ 24 are satisfied, the operation time of the unit saving process ([1] + [2] + [3]) is apparently The time of T1 will suffice. This means that the operation time of the unit saving process is shortened to 1/24 as the best value.
  • the transfer of the recovery data from the NVM chip 23 to the BM 220 in the recovery process operation [4] is also performed via the chip connection bus 24 provided independently for each lane 21, so that FIG. As shown in FIG. 6 (see also FIG. 6), the transfer of recovery data in each lane 21 (transfer order (1), (10),... In the figure) can be performed simultaneously and in parallel. It is.
  • the operation [4] can reduce the operation time to the original 1/8.
  • recovery processing is performed in the transfer order indicated by the numbers in parentheses in FIGS. 6 and 7A, and the operation times of operations [4] and [5] are T4 and T5, respectively, unit recovery is performed.
  • the operation time of the process ([4] + [5]) is apparently T4 / 8 + T5.
  • the time required for the leveling management information saving / restoring process is greatly reduced (the best value is reduced to 1/24 or 1/8).
  • FIG. 8 is a diagram showing an example of the configuration of a defective block information table 141 as a defective block information storage unit and a defective chip information table 142 as a defective chip information storage unit.
  • the defective block information table 141 in FIG. 8A stores “good” or “bad” state information of the block 231 used as a saving area for the leveling management information for each of the 24 NVM chips 23. It is.
  • the leveling management information save / restore processing unit 14 saves the leveling management information to the NVM chip 23
  • the bad block information table 141 is erased when the block 231 used as the save area of each NVM chip 23 is erased. Each time it is created based on the erased result. That is, the leveling management information save / restore processing unit 14 deletes a block 231 if at least part of the data of the page 232 included in the block 231 is not erased. Is determined. Then, “1” is set in the status information of the block determined to be defective in the NVM chip 23 in the defective block information table 141.
  • each of the 24 NVM chips 23 is provided with 14 blocks 231 of the save area, the block (# 2) of the NVM (# 1), and the block of the NVM (# 2). It is assumed that the block (# 1) is “bad”.
  • the failure chip information table 142 is a table for storing status information of “non-failure” or “failure” of each NVM chip 23 for each of the 24 NVM chips 23.
  • the leveling management information save / restore processing unit 14 determines that the NVM chip 23 in which page write errors frequently occur in the leveling management information save process is a faulty chip, and the status information of the NVM chip 23 in the faulty chip information table 142 Set “1” to.
  • the failed chip information table 142 “1” indicates that the NVM chip 23 is a failed chip, and “0” indicates that the block is a non-failed chip. In the example of FIG. 8B, the number of NVM chips 23 is 24, and NVM (# 2) is a failed chip.
  • FIG. 9 and FIG. 10 are diagrams showing an example of the transfer procedure of the save data when a page write error occurs during the saving process of the leveling management information.
  • FIG. 9 shows the transfer procedure of the first half
  • FIG. Shows the transfer procedure in the latter half.
  • the arrow line indicates the transfer direction of the saved data
  • the numbers in parentheses beside the arrow line indicate the order in each figure in which the transfer is performed.
  • the transfer order (16) is marked with an x, but this x indicates that the NVM (# 7) stores the saved data for one page transferred from the BM (# 7).
  • a page is programmed (written), a page write error has occurred.
  • the presence / absence of a page write error is determined when the program (write) to the page of the NVM chip 23 is completed.
  • the save data program related to the transfer order (16) is completed when the next save data is transferred to the NVM (# 7). It is a little before the start (around the transfer order (62) in FIG. 10). Therefore, the leveling management information save / restore processing unit 14 knows whether there is an error in writing the saved data transferred to the previous NVM (# 7) when the transfer in the transfer order (62) is being performed. .
  • the leveling management information save / restore processing unit 14 starts the transfer in the transfer order (63), based on the page write error presence / absence information notified from the NVM (# 7), the previously transferred save data is stored. It is determined whether or not the data has been normally written to NVM (# 7). When there is a page write error, that is, when it is determined that the saved data is not normally written to the NVM (# 7), the leveling management information save / restore processing unit 14 transferred the previous time. The save data is transferred again to the NVM (# 7) via the BM (# 7) (transfer order (63), (64)). That is, in the transfers in the transfer orders (63) and (64), the transfers in the transfer orders (15) and (16) are retried.
  • the save destination page address in NVM (# 7) is incremented by one.
  • the saved data is not rewritten (retryed) to the page 232 in which the page write error has occurred. Accordingly, in the BM (# 7) in which a page write error has occurred, the number of pages required for saving in the BM (# 7) increases by one for each retry.
  • the NVM chip 23 is determined as a failed chip, and the status information of the NVM chip 23 determined as defective in the failed chip information table 142 Set “1” to.
  • the leveling management information save / restore processing unit 14 retries the transfer that failed in the transfer orders (15) and (16) by the transfer in the transfer orders (63) and (64), the subsequent transfer order ( In 65) and (66), the saved data that was to be transferred in the transfer order (63) and (64) is transferred (see FIG. 10).
  • the transfer after the transfer order (67) thereafter returns to the transfer procedure of the normal save process when no page write error occurs.
  • FIG. 11 is a diagram showing an example of the transfer procedure in the latter half of the save data transfer procedure when there is a defective chip.
  • the first half of the save data transfer procedure when there is a faulty chip is the save data transfer procedure when there is no fault chip (for example, the procedure shown in FIG. 4). It is the same except that it is not broken.
  • the leveling management information save / restore processing unit 14 is shown in FIG. 4 except that in the first half of the save process, even if there is a faulty chip, the transfer of the save data to the faulty chip is omitted.
  • the leveling management information stored in the WM 130 is saved to the NVM chip 23 until the end.
  • all the saved data is saved to the NVM chip 23 other than the failed chip except for the saved data that was supposed to be saved to the failed chip.
  • the leveling management information save / restore processing unit 14 saves the saved data that has not been saved because it was saved to the failed chip as the latter half of the saved process according to the transfer procedure shown in FIG. Are distributed to the NVM chips 23 and saved.
  • the save data transfer procedure shown in FIG. 11 is the same as the transfer procedure shown in FIG. 4 when no defective chip exists except for the following two points.
  • FIG. 12 shows how the leveling management information that was not saved in the first half of the saving process is saved to each NVM chip 23 in the second half of the saving process in the save data transfer procedure when there is a defective chip.
  • the WM 130 is divided and shown by data for one page (4 kB). Of these, the data portion that has not been saved by the save processing of the first half portion is shown by a thick line frame. The data portion indicated by the bold line frame corresponds to the leveling management information that was to be saved to the failure chip NVM (# 2).
  • the leveling management information of the thick line frame portion that was to be saved in the NVM (# 2) is saved in a spare saving area (see FIG. 3) of the NVM chip 23 other than the NVM (# 2). That is, of the data stored in the WM 130, the data that was to be saved to the page (# 0) of the NVM (# 2) is saved to the page (# 0) of the NVM (# 0), The data that was to be saved in the page (# 1) of the NVM (# 2) is saved in the page (# 0) of the NVM (# 1) and is saved in the page (# 2) of the NVM (# 2). The data that was to be saved is saved to the page (# 0) of the NVM (# 3). Similarly, the data that was to be saved from the WM 130 to the NVM (# 2). Are sequentially read out one page at a time and are sequentially saved in NVM chips 23 other than NVM (# 2).
  • the save source data and save destination data are represented by the start point and end point of the arrow line, and the parenthesized numbers described on the start point side of the arrow line are saved to the NVM (# 2) in the WM 130.
  • the top page address of the save area of the save destination NVM chip 23 is (# 512), but the save retry due to the page write error described in FIGS. 9 and 10 is performed.
  • the top page address is a page after 512 in accordance with the number of retries.
  • FIG. 13 is a diagram for explaining how to assign a page address in the NVM chip 23 in which a defective block exists.
  • the NVM chip 23 includes a plurality of blocks 231, and each block 231 includes a plurality of pages 232. Since the page 232 is a unit for writing and reading data in the NVM chip 23, an address is assigned to each page.
  • the page address included in the NVM chip 23 passes through all the blocks 231 included in the NVM chip 23 as shown in FIG. A serial number is assigned to H.232, and the serial number is used as a page address.
  • a serial number is assigned to the page 232 included therein, and the serial number is assigned to the page. Address.
  • a block (# 1) marked with a cross is a bad block, and a serial number is assigned to the page 232 included in the block 231 excluding the block (# 1).
  • the page address Accordingly, no page address is assigned to the page 232 included in the defective block (# 1).
  • the substantial reserve save area in the NVM chip 23 is reduced by that amount.
  • the save data transfer procedure when a page write error occurs during the save process described in FIG. 12 and the save data transfer procedure when there is a defective chip can be applied as they are without considering the presence or absence of a defective block. it can.
  • the page address management in the NVM chip 23 when a bad block exists is performed by the leveling management information save / restore processing unit 14 based on the bad block information table 141.
  • FIG. 14 is a diagram illustrating an example of a processing flow of the leveling management information saving process performed by the leveling management information saving / recovering processing unit 14 and the buffer storage control unit 22.
  • the leveling management information save / restore processing unit 14 first initializes (zero clears) the WMA representing the save data start address (step S11).
  • WMA is the address of the head data when data for one page to be saved is stored in the WM 130.
  • PA (CA) represents a page address in the NVM chip 23 designated by CA.
  • the leveling management information save / restore processing unit 14 determines whether the BM (CA) can accept transfer of saved data (step S14).
  • BM (CA) means that the BM 220 is connected to the NVM chip 23 designated by CA.
  • the BM (CA) is transferring the previous save data to the NVM chip 23, it cannot accept the transfer of the new save data, and waits until the transfer ends (No in step S14).
  • the leveling management information save / restore processing unit 14 further performs the page at the previous save to the NVM chip 23 designated by the CA. It is determined whether or not there has been a write error (step S15). In this determination, if there is no page write error at the time of the previous save (No in step S15), the save data WM (WMA) for one page whose head data address is specified by WMA is read from the WM 130 and read. The saved data WM (WMA) for one page is transferred to BM (CA) (step S16).
  • the buffer storage control unit 22 having the BM (CA) that has received the transfer of the saved data for one page transfers the saved data from the BM (CA) to the NVM (CA, PA (CA)) (step S17).
  • NVM (CA, PA (CA)) represents a storage area of the page address PA (CA) of the NVM chip 23 designated by the chip number CA.
  • the NVM (CA) that is the NVM chip 23 that has received the transfer of the save data writes (programs) the save data in the area of NVM (CA, PA (CA)).
  • the leveling management information save / restore processing unit 14 increments the address WMA of the WM 130 by 4098 (4 kB) (step S18) and increments the chip number CA of the NVM chip 23 by one (step S19). Subsequently, the leveling management information saving / recovery processing unit 14 determines whether the chip number CA is any of 8, 16, and 24 (step S20), and the chip number CA is 8, 16, If it is not any of 24 (No in step S20), it is further determined whether or not the chip number CA is 24 (step S21).
  • step S23 If it is determined in step S23 that WMA does not exceed the upper limit value WMAmax (No in step S23), the leveling management information save / restore processing unit 14 returns the execution of the process to step S13. If the WMA exceeds the upper limit value WMAmax (Yes in step S23), it means that there is no more data to be saved, and the saving process in FIG. 14 is terminated. With the above processing, the save processing for the case where no page write error has occurred is performed.
  • step S15 if it is determined in step S15 that there is a page write error at the time of previous save (Yes in step S15), the leveling management information save / restore processing unit 14 is the same as the previous save data according to the following procedure. The data is saved again to the NVM chip 23 designated by the CA.
  • the saved data WM (WMA) for one page is read out, and the read saved data WM (WMA) for one page is transferred to the BM (CA) (step S32).
  • the buffer storage control unit 22 having the BM (CA) that has received the transfer of the saved data for one page transfers the saved data from the BM (CA) to the NVM (CA, PA (CA)) (step). S33).
  • the NVM (CA) which is the NVM chip 23 that has received the transfer of the save data, writes (programs) the save data in the area of NVM (CA, PA (CA)).
  • step S31 to step S36 corresponds to the transfer processing in the transfer order (63) and (64) in FIG. Therefore, in the case where a page write error has occurred in the previous saving process by the processing in steps S31 to S36, the saving of the data of the WM 130 that was supposed to be saved last time is retried. Therefore, the leveling management information save / restore processing unit 14 shifts the execution of the process to step S18 after step S36.
  • step S20 If it is determined in step S20 that the chip number CA is 8, 16, or 24 (Yes in step S20), the leveling management information saving / recovery processing unit 14 further determines that the CAE is It is determined whether or not it is “Null” (step S41). If CAE is “Null” (Yes in step S41), the chip number CA is 0 to 7, 8 to 15, or 16 to 23 In any case, it means that the retry process of the page write error has not been performed, so the process is returned to step S21 following the original step S20 without doing anything.
  • step S41 the page write is performed when the chip number CA is any of 0 to 7, 8 to 15, or 16 to 23. Since this means that an error retry process has been performed, the leveling management information save / restore processing unit 14 performs a save data save process that was not performed due to a page write error retry. In that case, the chip number of the NVM chip 23 to be saved is stored in the CAE, and the save data start address of the WM 130 is stored in the WMAE.
  • the leveling management information save / restore processing unit 14 reads the saved data WM (WMA) for one page specified by WMAE from the WM 130 and the saved data WM (WMAE) for the read one page is BM ( To CAE) (step S42). Then, the buffer storage control unit 22 having the BM (CAE) that has received the transfer of the saved data for one page transfers the saved data from the BM (CAE) to the NVM (CAE, PA (CAE)) (step). S43). Thereafter, the NVM (CAE), which is the NVM chip 23 that has received the transfer of the save data, writes (programs) the save data in the area of NVM (CAE, PA (CAE)).
  • steps S42 and S43 correspond to the transfer processes in the transfer order (65) and (66) in FIG. Subsequently, the leveling management information saving / recovery processing unit 14 returns the CAE to “Null” (step S44), and shifts the execution of the processing to step S21.
  • the recovery data transfer procedure is the same as the recovery data transfer procedure shown in FIG. 6 except as described below.
  • the saved leveling management information is stored in the page (# of the NVM chip 23). 0) to the page (# 511) are stored in the basic save area (see FIG. 3). On the other hand, when there is a defective chip, a defective block, or a page write error, the leveling management information is stored not only in the basic save area but also in the spare save area after the page (# 512).
  • the leveling management information save / recovery processing unit 14 starts the leveling management information recovery processing when the power on / off detection unit 15 detects the start of power supply. Therefore, it is impossible to know up to which page address the leveling management information has been saved in the spare save area. Therefore, in the present embodiment, the management information including the last page address of the saved data is not stored in the nonvolatile memory separate from the NVM chip 23, and the leveling management information is restored. All data from the first page (# 0) in the basic save area to the last page (# 895) in the spare save area is read.
  • the leveling management information save / restore processing unit 14 reads all data from the save data storage area of the NVM chip 23, the recovery data is transferred from the NVM chip 23 to the WM 130 in accordance with the transfer procedure of FIG. There is nothing else. However, the last page address read from the NVM chip 23 is not (# 511) but (# 895).
  • the leveling management information save data without error is written in the NVM chip 23 which has become a defective chip in the middle of the save process up to the page address in the middle.
  • the saved data that was scheduled to be saved to the NVM chip 23 is not a failed chip again by the procedure shown in FIG. It is distributed and saved in other NVM chips 23. Therefore, in such a case, the same data is duplicated and recovered to the WM 130, but there is no problem with duplicate recovery.
  • duplication recovery is performed in some cases, but this also causes no problem.
  • the leveling management information saving / recovering processing unit 14 determines whether the checksum (see FIG. 3) is correct. . If the checksum is correct, the leveling management information is restored normally. If the checksum is not correct, it means that the recovery of the leveling management information has failed. Therefore, a separate process for recovery of the leveling management information is executed.
  • the saved data start address included in the header 233 of the page 232 is used as the address when the recovery data is written to the WM 130. Therefore, if the saved data start address is saved or restored by mistake, the leveling management information recovered by the WM 130 becomes unreliable. Therefore, it is preferable to make the saved data start address highly reliable by, for example, duplicating or attaching an error code that can correct a plurality of bits.
  • the WM 130 of the leveling management information storage unit 13 is connected to the BM 220 of the buffer storage control unit 22 included in each of the plurality of lanes 21 via the lane connection bus 30.
  • the lane 21 is provided with a chip connection bus 24 that connects the BM 220 and the NVM chip 23. Accordingly, in the leveling management information saving process, the saving data can be transferred from the BM 220 to the NVM chip 23 in each lane independently and in parallel, so that the saving time can be shortened.
  • the saved data including the leveling management information for one page saved to the NVM chip 23 includes the head address when the leveling management information for that one page is stored in the WM 130.
  • the transfer procedure of the recovery data in the recovery process is simplified.
  • Nonvolatile data storage control part 11 Data writing / reading control part 12 Leveling management part 13 Leveling management information storage part 14 Leveling management information save / recovery processing part 15 Power ON / OFF detection Unit 20 Nonvolatile data storage unit 21 Lane 22 Buffer storage control unit 23 NVM chip (nonvolatile memory chip) 24 chip connection bus 30 lane connection bus 130 WM (wear leveling memory) 141 Defective block information table (defective block information storage unit) 142 Failure chip information table (failure chip information storage unit) 220 BM (buffer memory) 231 block 232 page 233 header 234 segment 235 check code

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Abstract

Selon l'invention, lorsque sont sauvegardées des informations de gestion de mise à niveau mémorisées dans une unité (13) de mémoire d'informations de gestion de mise à niveau, une unité (14) de traitement de sauvegarde / rétablissement d'informations de gestion de mise à niveau effectue une transmission séquentielle à des unités (22) de commande de mémoire tampon contenues individuellement dans huit réseaux locaux (21). Après une mémorisation temporaire dans une mémoire tampon de ces informations de gestion de mise à niveau reçues, les huit unités (22) de commande de mémoire tampon assurent un transfert de façon indépendante entre des puces (23) de mémoire non volatile (NVM), par l'intermédiaire d'un bus (30) de connexion de réseaux locaux agencé individuellement sur chacun des réseaux locaux (21).
PCT/JP2010/073670 2009-12-28 2010-12-28 Dispositif de disque électronique, et procédé de sauvegarde / rétablissement d'informations de gestion de mise à niveau WO2011081168A1 (fr)

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JP7446963B2 (ja) 2020-09-23 2024-03-11 キオクシア株式会社 メモリシステム及びメモリシステムの制御方法

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