WO2008002268A1 - Structure de substrat ltcc - Google Patents

Structure de substrat ltcc Download PDF

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Publication number
WO2008002268A1
WO2008002268A1 PCT/SG2006/000174 SG2006000174W WO2008002268A1 WO 2008002268 A1 WO2008002268 A1 WO 2008002268A1 SG 2006000174 W SG2006000174 W SG 2006000174W WO 2008002268 A1 WO2008002268 A1 WO 2008002268A1
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WO
WIPO (PCT)
Prior art keywords
holes
ltcc
filled
layer
substrate
Prior art date
Application number
PCT/SG2006/000174
Other languages
English (en)
Inventor
Arulvanan Periannan
Kai Meng Chua
Albert Lu
Original Assignee
Agency For Science, Technology And Research
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency For Science, Technology And Research filed Critical Agency For Science, Technology And Research
Priority to PCT/SG2006/000174 priority Critical patent/WO2008002268A1/fr
Priority to TW096123425A priority patent/TW200818415A/zh
Publication of WO2008002268A1 publication Critical patent/WO2008002268A1/fr

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • H05K3/4061—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in inorganic insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
    • H01L21/4807—Ceramic parts
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203—Cooling of mounted components
    • H05K1/0204—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate
    • H05K1/0206—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate by printed thermal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/64—Heat extraction or cooling elements
    • H01L33/641—Heat extraction or cooling elements characterized by the materials
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01—Tools for processing; Objects used during processing
    • H05K2203/0147—Carriers and holders
    • H05K2203/0156—Temporary polymeric carrier or foil, e.g. for processing or transferring
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/08—Treatments involving gases
    • H05K2203/082—Suction, e.g. for holding solder balls or components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/08—Treatments involving gases
    • H05K2203/085—Using vacuum or low pressure
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets

Definitions

  • the present invention relates broadly to a low temperature co-fired ceramic (LTCC) substrate structure, to a method of forming an LTCC based substrate structure, to an electronic device, and to a method of fabricating an electronic device.
  • LTCC low temperature co-fired ceramic
  • High temperature heat dissipating dies are utilised in numerous device technologies.
  • solid state lighting SSL is an emerging technology owing to the advantage of energy efficiency, compact form factor and long life.
  • high power LEDs
  • LTCC low temperature co-fired ceramic
  • Applications of high power LEDs in e.g. the automotive and outdoor lighting fields are attractive because of the improved economics of high power LEDs compared to conventional lighting technology.
  • LTCC-M technology is primarily used.
  • the high temperature heat dissipating die is mounted on a metal base, which is sandwiched to a LTCC substrate.
  • insulated via feed-through may be required in the metal base, for electrical contacting and drive control of the dies.
  • the processes associated with the formation of such insulated via feed-through, such as oxidation or thin-film deposition, must be performed and completed separately, and before the co-sintering of the metal base and the LTCC substrate.
  • the required insulation thicknesses are typically very small, e.g.
  • the thin die-electric thickness will typically also result in a capacitive loading of the signal interconnection, degrading the high-speed interconnection. In LED drive control applications, the capacitive loading will typically also impact the rate of LED modulation achievable.
  • the capacitive loading problems are further enhanced due to the difficulty of forming the thin dielectric thicknesses with a controllable thickness, making it difficult if not impossible to provide designs incorporating electrically compensating structures.
  • the existing LTCC-M technology primarily addresses thermal management, without considering or addressing the electrical interconnection.
  • materials used in existing LTCC-M technology such as Co-Mo-Cu, are typically expensive, thus adding to the overall cost of the device manufactured.
  • a method of forming a low temperature co-fired ceramic (LTCC) based substrate structure having one or more through holes, with an aspect ratio of a thickness of the LTCC substrate to a lateral dimension of the through-holes smaller than about 1 comprising the steps of forming the through-holes in a tape layer; providing an intermediate layer on a first surface of the tape layer; providing a vacuum backing paper on the intermediate layer; and filling the through-holes utilising a printer vacuum table.
  • the method may further comprise providing a support layer on a second surface of the tape layer; and forming the through-holes in the tape layer with the support layer attached.
  • the support layer may comprise a polymer based material.
  • the method may further comprise removing the support layer from the second surface of the tape layer at an elevated temperature above room temperature after the through-holes are filled.
  • the method may further comprise providing a peripheral securing layer for attaching the intermediate layer to the first surface of the tape layer.
  • the securing layer may comprise a quick release tape.
  • the intermediate layer may comprise a stretchable material.
  • the intermediate layer may comprise a polyvinyl layer.
  • the method may further comprise removing the intermediate layer and the vacuum backing tape from the first surface of the tape layer after the through-holes are filled.
  • the through-holes may have an aspect ratio of a thickness of the tape layer to a lateral dimension of the through-holes smaller than about 1.
  • a substrate structure comprising one or more though-holes formed in an LTCC based substrate, the through-holes filled with a thermally conducting material; wherein an aspect ratio of a thickness of the LTCC substrate to a lateral dimension of the through-holes smaller than about 1.
  • a electronic device comprising an LTCC based substrate; one or more though-holes formed in the LTCC based substrate, the through-holes filled with a thermally conducting material and having an aspect ratio of a thickness of the LTCC substrate to a lateral dimension of the through-holes smaller than about 1; and one or more dies mounted on the respective filled through-holes.
  • the dies may be mounted entirely on the respective filled through-holes.
  • the device may further comprise a heat spreader structure in thermal connection with the respective filled through-holes.
  • the heat spreader structure may be mounted to the LTCC substrate via an intermediate layer.
  • the filled through-holes may each comprise a first interface layer disposed adjacent the heat spreader for facilitating an interface reliability, a thermal dissipation, or both.
  • the heat spreader structure may be joined to the filled through-holes via solder balls or columns.
  • solder joints or columns may be joined entirely to the respective filled through-holes on an LTCC substrate side.
  • the heat spreader structure may comprise a plate having dimples or drill holes formed in a surface of the plate facing the LTCC substrate.
  • the plate may comprise a metal plate or a metal composite plate.
  • the filled through-holes may each comprise a second interface layer disposed adjacent the respective dies for facilitating an interface reliability, a thermal dissipation, or both.
  • the device may further comprise interconnect patterns formed on the LTCC substrate for interconnecting the respective dies.
  • a method of fabricating an electronic device comprising providing an LTCC based substrate; forming one or more though-holes in the LTCC based substrate, the through-holes filled with a thermally conducting material and having an aspect ratio of a thickness of the LTCC substrate to a lateral dimension of the through-holes smaller than about 1; and mounting one or more dies on the respective filled through-holes.
  • a substrate structure fabricated using the method defined in the first aspect.
  • Figures 1(a) to (e) are schematic cross-sectional drawings illustrating a method of forming an LTCC substrate structure.
  • Figure 2 is a schematic cross-sectional drawing of an electronic device.
  • Figure 3 is a schematic cross-sectional drawing of another electronic device.
  • Figures 4(a) and (b) are schematic top view drawings of respective electronic device layouts.
  • Figure 5 is a schematic cross-sectional drawing of an electronic device.
  • Figures 6(a) and (b) are a schematic cross-sectional drawings of respective heat spreader plates for use in the device of Figure 5.
  • Figure 7 shows a flow-chart illustrating a method of forming a low temperature co-fired ceramic (LTCC) based substrate structure.
  • LTCC low temperature co-fired ceramic
  • Figure 8 shows a flow-chart illustrating a method of fabricating an electronic device.
  • FIGs 1(a) to (e) show schematic cross sectional diagrams illustrating a manufacturing process for fabricating a substrate structure for high temperature heat dissipating dies.
  • via holes e.g. 100 are punched in a green tape 102 with a mylar backup film 104 attached to the green tape 102.
  • the green tape 102 in the described example is A6-M Tape (Ferro Electronics Materials). However, other green tapes may be used, including A6-S Tape (Ferro Electronics Materials).
  • the green tape with mylar backup film 104 is in turn attached to a fixture frame (not shown), such that the green tape 102 is exposed.
  • a polyvinyl film 108 of about 20 micron thickness is provided to cover the green tape 102.
  • the polyvinyl film 108 is attached to the green tape 102 utilising a quick release tape 110.
  • the release tape 110 is used along the periphery of the polyvinyl film 108 to attach the polyvinyl film 108 to the green tape 102, and leaving the polyvinyl film 108 inside the periphery uncovered.
  • the polyvinyl film 108 in the example described is a SiberHegner's Non silicon PVC film with acrylic adhesive Part number NSHU-859ABR PVC, adhesion after 24 hrs 50g/25mm).
  • a vacuum backing paper 112 is then provided on the polyvinyl film 108.
  • the vacuum backing paper is a porous paper chosen in the described example such that air can pass through its pores but not wet materials.
  • the printing paste 116 comprises a thermally conductive via material such as a silver composite.
  • a conductive via silver composite ink paste 116 is co- fireable, Silver via fill paste, Ferro CN33-407, with a shrinkage matched to the green tape 102.
  • the paste 116 is filled into the via holes 100, with the paste 116 applied along the green tape 102 with mylar backup film 104 and swiped across with the aid of a squeezer (not shown).
  • the polyvinyl film 108 advantageously contributes to ensuring that the paste does not get "sucked” away through the via holes 100 to the porous vacuum backing paper 112 under vacuum.
  • the printing process can be optimised to utilise a suitable squeezer material, squeeze angle, printing pressure and printing speed to ensure proper hole fill.
  • the frame together with the tape structure 118 is heated for about 15 minutes at about 7O 0 C for curing of the fill material in the via holes 100.
  • the vacuum backing paper 112 ( Figure 1(b)) and the polyvinyl film 108 ( Figure 1(b)) are removed, the removal of the polyvinyl film 108 being facilitated by removal of the quick release tape 110 ( Figure 1(b)).
  • Pattern printing of a desired pattern, indicated schematically at 120, is then carried out on the top surface 122 of the green tape 102.
  • the frame with the tape structure 124 is heated for about 15 minutes at about 7O 0 C, and the mylar back up tape 104 is removed while the tape structure 124 is hot.
  • the resulting substrate structure 126 is shown in Figure 1(e).
  • the substrate structure 126 can then be subjected to conventional LTCC processes such as stacking, laminating and sintering, to form the final LTCC substrate. It was found that with the process described above with reference to Figures
  • a low aspect ratio refers to a ratio of the thickness of the substrate to the lateral dimension of the hole being smaller than about 1.
  • a thickness of the green tape 102 is e.g. about 0.254mm and diameter of the via holes 100 is e.g. 1.8mm, giving an aspect ratio of about 0.141. It will be appreciated that an aspect ratio smaller than about 1 can be maintained in a stacked LTTC substrate built up from several substrate structures of the type of substrate structure 126.
  • a final LTCC substrate laminated and sintered with four layers, allowing for shrinkages can have a thickness of about 0.862mm and a diameter of the via holes of 1.35mm, giving an aspect ratio of about 0.64.
  • existing processes such low aspect ratio filled holes in LTCC substrates have not been successfully produced, due to problems associated with retaining the shape of the filled hole in the green tape, and due to peel-off of the filled material during removable of the porous backing paper.
  • the mylar backup film 104 was found to facilitate retaining the shape of the filled holes, while the polyvinyl film 108 was found to reduce or eliminate the peel-off problem associated with the vacuum backing paper 112. Furthermore, removing the mylar film 104 while the substrate structure 118 is at an elevated temperature above room temperature was found to further reduce or eliminate peel-off of the filled material.
  • the mylar film 104 When the mylar film 104 is heated up to around 7O 0 C, the mylar "softens” due to reduced stiffness of the polymer chains. This causes a expansion mismatch between the green tape 102 and the via holes 100 fill paste interfaces, enabling easy release of the mylar film 104 from the green tape 102 and the silver fill paste.
  • backup films including other polymer based materials, selected such that the softening effect described above can be achieved for releasing of the backup film from the green tape and the silver fill paste.
  • the fill paste is left in place in the via hole 100, because less force is required to detach the bonds at the interface between the film and the fill paste, compared to the force that is binding the fill paste inside the via holes 100.
  • Figure 2 shows a die 200 attached entirely to a via 202 and connected to an LTCC substrate 204 using wire bonds 206 connecting to interconnection patterns e.g. 207 formed on the LTCC substrate 204.
  • the die 202 can be attached using thermally conductive adhesives (not shown) or any other suitable joining process.
  • Surface treatment/coating of the material in the via 202, the substrate structure 204, or both may be performed.
  • the material in the via 202 is nickel based
  • coating of the surface with gold to protect against oxidation and to enable solder attachment may be performed.
  • the processing can be thin-film based, such as electro plating or electroless plating. Alternatively, the processing can be thick film based.
  • different coating materials may be used such as copper or copper based alloys.
  • the processing can be performed to create respective interface regions or intermediate layers for improving the reliability of the interface between die 200 and via 202 on one side and between the via 202, the substrate structure 204, or both, and an optional heat sink 304 on the other side.
  • an LED sapphire die can be attached on the top of the via with a thermally conductive adhesive.
  • FIG. 3 shows a cross sectional drawing of a via hole dies e.g. 300 mounted LTCC module 302 mounted to a heat sink 304 with spring washers 306 tightened using controlled torque cheese head screws 308.
  • an LED module can be fabricated with one or more LED dies 300 attached to the top of via hole fill material e.g. 310, and powered by wire bonding 312 from the top of the LTCC substrate 302 to interconnection patterns e.g. 313 formed on the LTCC substrate 302.
  • the LTCC substrate 302 can be attached with a thermal interface material (not shown) below each via hole and attached to the heat sink 304 with the spring washers 306.
  • Torque controlled screw 308 tightening with spring washers 306 can allow for compensation of coefficient of linear thermal expansion (CTE) mismatch between the LTCC substrate 302 and the heat sink 304.
  • CTE coefficient of linear thermal expansion
  • Figures 4(a) and (b) show the top view representations of products 400, 450 with multiple LED dies 402, 452 forming various patterns.
  • the via hole shapes can be circular 404, square 406, rectangle 408, star shaped 410, parallelogram-shaped, or a combination of any regular or irregular shape.
  • Figure 5 shows a cross-sectional schematic view of a module 500 with each die 502 attached via hole 504 connected to respective solder balls or columns 506, which in turn are connected to a metal plate 508.
  • the solder balls or columns 506 are connected entirely to the via holes 504.
  • the filled via holes 504 are filled with a thermally conductive material 514 and attach to a heat spreader in the form of e.g. the metal plate 508, by soldering or by the use of thermally conductive adhesives.
  • the heat spreader may be made of metal or metal ceramic composite materials, and may be chosen to match with the CTE of the particular LTCC substrate.
  • the metal or a composite plates 508' or 508" as shown in Figure 6(a) and (b) respectively, may have dimples 510 or drilled holes 512 to match the solder balls or columns 506 to connect to form a module with high thermal conductivity.
  • Figure 7 shows a flow-chart 700 illustrating a method of forming a low temperature co-fired ceramic (LTCC) based substrate structure having one or more through holes, with an aspect ratio of a thickness of the LTCC substrate to a lateral dimension of the through-holes smaller than about 1.
  • the though-holes are formed in a tape layer.
  • an intermediate layer is provided on a first surface of the tape layer.
  • a vacuum backing paper is provided on the intermediate layer.
  • the through-holes are filled utilising a printer vacuum table.
  • FIG. 8 shows a flow-chart 800 illustrating a method of fabricating an electronic device.
  • an LTCC based substrate is provided.
  • one or more though-holes are formed in the LTCC based substrate, the through- holes filled with a thermally conducting material and having an aspect ratio of a thickness of the LTCC substrate to a lateral dimension of the through-holes smaller than about 1.
  • one or more dies are mounted on the respective filled through-holes.
  • the described processes, substrates and devices make use of the via holes of the LTCC substrate and hence can result in lower manufacturing cost.
  • the described processes, substrates and devices can open up applications making use of low aspect ratio via holes in the power electronics field, including applications in solid state lighting, but also including applications in other device technologies such as Radio Frequency modules, Blue tooth Modules, wireless applications from GSM, CDMA, TDMA, Bluetooth and Wireless LAN at the lower microwave frequency end up to the millimeter wave region.
  • the thermally conductive vias are formed integrally with the LTCC substrate.
  • existing LTCC-M techniques involve an additional sandwich process to join a separate LTCC substrate to the metal base, the described processes, substrates and devices do not require such a sandwich processing.
  • only the via holes may be connected to other structures, such as heat sink structures, without a need to directly join the ceramic portion of the LTCC substrate to any other structure.
  • the described processes, substrates and devices can thus provide a more time efficient, cost efficient, or both, technique compared with existing LTCC-M techniques.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Laminated Bodies (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

La présente invention concerne un procédé de formation d'une structure de substrat à base de céramiques cocuites à basse température (LTCC) ayant un ou plusieurs trous traversants, avec un rapport largeur/longueur d'une épaisseur du substrat LTCC par rapport à une dimension latérale des trous traversants inférieur à environ 1, le procédé comprenant les étapes consistant à former les trous traversants dans une couche de ruban ; fournir une couche intermédiaire sur une première surface de la couche de ruban ; fournir un papier de support de vide sur la couche intermédiaire ; et remplir les trous traversants en utilisant une table de vide d'imprimante.
PCT/SG2006/000174 2006-06-27 2006-06-27 Structure de substrat ltcc WO2008002268A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/SG2006/000174 WO2008002268A1 (fr) 2006-06-27 2006-06-27 Structure de substrat ltcc
TW096123425A TW200818415A (en) 2006-06-27 2007-06-27 LTCC substrate structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/SG2006/000174 WO2008002268A1 (fr) 2006-06-27 2006-06-27 Structure de substrat ltcc

Publications (1)

Publication Number Publication Date
WO2008002268A1 true WO2008002268A1 (fr) 2008-01-03

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CN111465218A (zh) * 2020-03-19 2020-07-28 国巨电子（中国）有限公司 一种低温共烧陶瓷及其填孔方法
CN115383868B (zh) * 2022-08-24 2024-05-10 上海泽丰半导体科技有限公司 一种ltcc生瓷带及其制造方法

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DE29623190U1 (de) * 1996-11-28 1997-12-11 Siemens AG, 80333 München Mehrschichtleiterplatte
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JP2016500485A (ja) * 2012-12-21 2016-01-12 エプコス アクチエンゲゼルシャフトＥｐｃｏｓ Ａｇ コンポーネントキャリア及びコンポーネントキャリアアセンブリ
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