WO2008001644A1 - Circuit de commutation de polarité et unité d'alimentation - Google Patents

Circuit de commutation de polarité et unité d'alimentation Download PDF

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Publication number
WO2008001644A1
WO2008001644A1 PCT/JP2007/062283 JP2007062283W WO2008001644A1 WO 2008001644 A1 WO2008001644 A1 WO 2008001644A1 JP 2007062283 W JP2007062283 W JP 2007062283W WO 2008001644 A1 WO2008001644 A1 WO 2008001644A1
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WO
WIPO (PCT)
Prior art keywords
output terminal
switch
voltage
input terminal
switching element
Prior art date
Application number
PCT/JP2007/062283
Other languages
English (en)
Japanese (ja)
Inventor
Tadashi Matsumoto
Shoji Koise
Original Assignee
Panasonic Electric Works Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Electric Works Co., Ltd. filed Critical Panasonic Electric Works Co., Ltd.
Priority to CN2007800243001A priority Critical patent/CN101479907B/zh
Priority to JP2008522467A priority patent/JP4925363B2/ja
Publication of WO2008001644A1 publication Critical patent/WO2008001644A1/fr

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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H11/00—Emergency protective circuit arrangements for preventing the switching-on in case an undesired electric working condition might result
    • H02H11/002—Emergency protective circuit arrangements for preventing the switching-on in case an undesired electric working condition might result in case of inverted polarity or connection; with switching for obtaining correct connection
    • H02H11/003—Emergency protective circuit arrangements for preventing the switching-on in case an undesired electric working condition might result in case of inverted polarity or connection; with switching for obtaining correct connection using a field effect transistor as protecting element in one of the supply lines

Definitions

  • the present invention is connected to a DC power supply which applies a DC voltage to two feed conductors, and a polarity switching circuit for matching the polarity of this DC power supply with the polarity of the feed conductor, and this polarity switching circuit.
  • the present invention relates to a power supply unit provided with
  • Japanese Patent Laid-Open Publication No. Hei 5-30641 discloses a polarity switching circuit for connecting a DC voltage source with a correct polarity to a load operated by a DC power supply.
  • the polarity switching circuit is disposed between the feed line and the DC power supply, and includes a pair of input terminals connected to the DC power supply and a pair of output terminals connected to the load, and the polarity of the polarity of the input terminal is Even if it is unknown whether one of the input terminals is connected to the positive electrode or the negative electrode of the DC power supply, the polarity of the polarity is such that the positive electrode of the DC power supply is always connected to one of the output terminals. Are configured to switch.
  • one of the output terminals is set to the positive electrode terminal connected to the positive electrode of the load, and the other is set to the negative electrode terminal connected to the negative electrode of the load, and it is necessary to correctly connect to the load. Therefore, when connecting the DC power supply and load with the correct polarity when adding a DC power supply to the feed line, the person performing the work should connect the positive and negative sides of the feed conductor without mistaken output terminals. There is a problem that confirmation of this polarity is troublesome. On the other hand, when this polarity switching circuit is included in advance for all the loads, the characteristics of this polarity switching circuit can be used to add DC power without confirming the polarity.
  • the present invention has been made in view of the above problems, and an object of the present invention is to correct a DC power supply without checking the polarity of a power feeding system to which a load is connected. !, Polarity To provide a polarity switching circuit that can be added to the feed system.
  • the DC power supply is connected to two feed conductors connected to the load, interposed between the DC power supply and the load.
  • Positive input terminal IN + connected to the positive electrode of the DC power supply
  • a negative input terminal IN ⁇ connected to the negative electrode of the DC power supply
  • a first output terminal OUT1 connected to one of the two feed conductors
  • a second output terminal OUT2 connected to the other of the two feed conductors
  • a first switch SW1 inserted between the positive input terminal and the first output terminal; a second switch SW2 inserted between the positive input terminal and the second output terminal; the negative input terminal; With a third switch SW3 inserted between the first output terminal
  • a fourth switch SW4 inserted between the negative input terminal and the second output terminal is provided.
  • the first switch SW1 and the fourth switch SW4 become conductive when the voltage applied to the first output terminal OUT1 is higher than the voltage applied to the second output terminal, and the positive input is switched.
  • the terminal IN + (the positive electrode of the DC power supply) is connected to the first output terminal OUT1
  • the negative input terminal IN- (the negative electrode of the DC power supply) is connected to the second output terminal OUT2.
  • the second switch SW2 and the third switch SW3 become conductive when the voltage applied to the first output terminal OUT1 is smaller than the voltage applied to the second output terminal OUT2, and the positive switch An input terminal IN + (positive electrode of DC power supply) is connected to the first output terminal, and a negative input terminal IN ⁇ (negative electrode of DC power supply) is connected to the second output terminal.
  • this polarity switching circuit is prepared as a power supply unit in combination with a DC power supply, it can be incorporated into an existing power supply system together with a DC power supply that does not care about the polarity at the time of connection work.
  • the first switch includes a first switching element having a control end G, and the first switching element is between the control end and the positive input terminal. It is configured to conduct when a voltage less than a predetermined value is applied.
  • the second switch includes a second switching element having a control end G, and the second switching element receives a voltage less than a predetermined value between the control end and the positive input terminal.
  • the third switch includes a third switching element having a control end G. The third switching element has a voltage between the control end and the positive input terminal that exceeds a predetermined value.
  • the fourth switch is configured to conduct when applied, and the fourth switch includes a fourth switching element having a control end G, and the fourth switching element has a predetermined value between the control end and the positive input terminal. It is configured to conduct when an over voltage is applied.
  • the control end of the first switching element and the control end of the third switching element are both connected to the second output terminal OUT2, and the control end of the second switching element and the control of the fourth switching element Both ends are connected to the first output terminal OUT1.
  • the first switch applies a control voltage equal to or greater than the predetermined value of the positive electrode force to the control end of the first switching element and delays the control voltage for a predetermined time to apply a voltage less than the predetermined value to the control end.
  • a first delay circuit (Rl, C1) is provided.
  • the above second switch is the above second switch.
  • a second delay circuit (R2, C2) for applying a voltage less than the predetermined value to the control end after giving a control voltage of the positive value to the control end of the positive electrode and delaying the control time for a predetermined time .
  • the first switching element is made conductive to cut off the second switching element, whereby the positive electrode of the DC power supply is connected to the first output terminal.
  • the first switching element is cut off, the second switch element is turned on, and the second output is turned on.
  • the positive terminal of the DC power supply is connected to the terminal.
  • the first delay circuit and the second delay circuit operate together, but due to the delay by the first delay circuit
  • the delay time of the second delay circuit is also increased. That is, when the DC power supply is connected to the power supply system first, and the polarity of the feed conductor is not determined yet, the delay in the first delay circuit is shorter than that in the second delay circuit, so the first switching is performed.
  • the voltage applied to the control end of the element is accelerated to drop below a predetermined value, and the first switching element conducts earlier than the second switching element, and the DC power source positive electrode is applied to the first output terminal. It takes place preferentially.
  • a control voltage equal to or greater than a predetermined value is applied to the control end of the second switching device to shut off the second switching device, making the first output terminal positive.
  • the power supply conductor connected to the first output terminal can be preferentially used as the positive electrode, and standardization of the power supply system can be achieved and standardized.
  • a load can be connected to the feed system.
  • the first switching element and the second switching element are formed of FETs having parasitic capacitance between the gate and the source.
  • the source of the first switching element is coupled to the positive input terminal, the drain is connected to the first output terminal, and the source is turned on when the source voltage is higher than the gate voltage by a predetermined value, Connected to the first output terminal.
  • the first delay circuit is in series with the parasitic capacitance C1 and the parasitic capacitance.
  • a connection point between the first resistor R1 and the parasitic capacitance C1 is connected to the gate G, which is composed of a first resistor R1 inserted between the positive input terminal and the second output terminal.
  • the source of the second switching element is coupled to the positive input terminal, the drain is connected to the second output terminal, and the source voltage is turned on when the source voltage is higher than the gate voltage by a predetermined value,
  • the child IN + is connected to the second output terminal OUT2.
  • the second delay circuit (R2, C2) comprises the parasitic capacitance C2 and a second resistor R2 inserted in series with the parasitic capacitance between the positive input terminal IN + and the first output terminal OUT1.
  • a connection point between the second resistor and the parasitic capacitance is connected to the gate G. Since the resistance value of the first resistor R1 is smaller than the resistance value of the second resistor R2 and the time constant of the first delay circuit is smaller than the time constant of the second delay circuit, the delay by the first delay circuit is caused.
  • the delay time by the second delay circuit is longer than the delay time.
  • each delay circuit can be configured by utilizing the parasitic capacitance intrinsically provided by the FET, and the switching circuit having the above function can be configured with the minimum
  • a voltage divider resistor is used to protect the FET. That is, a first voltage dividing resistor is connected in series with the first resistor R1 between the positive input terminal IN + and the second output terminal, and between the first resistor R1 and the first voltage dividing resistor R11 The gate of the first switching element is connected to the connection point of Similarly, a second voltage dividing resistor is connected in series with the second resistor R2 between the positive input terminal IN + and the first output terminal, and between the second resistor R2 and the second voltage dividing resistor R21. The gate of the second switching element is connected to the connection point. With this configuration, the gate 'source voltage of the first switching element and the second switching element, which are FETs, can be divided to a predetermined value or less, and the FETs can be protected.
  • the first voltage dividing resistor R11 and the positive input terminal IN + Preferably, a zener diode is inserted, and a second zener diode is inserted between the second voltage dividing resistor R21 and the positive input terminal IN +.
  • FIG. 1 is a circuit diagram of a polarity switching circuit according to a first embodiment of the present invention.
  • FIG. 2 A block diagram showing a feeding unit incorporating the polarity switching circuit of the same.
  • FIG. 3 A schematic view showing one usage pattern of the above-mentioned power supply unit.
  • FIG. 4 A circuit diagram showing a modification of the polarity circuit of the above.
  • FIG. 5 A circuit diagram showing a modification of the polarity circuit of the above.
  • FIG. 6 is a circuit diagram showing a modification of the polarity circuit of the above.
  • FIG. 7 A circuit diagram showing a modification of the polarity circuit of the above.
  • FIG. 8 is a circuit diagram of a polarity switching circuit according to a second embodiment of the present invention.
  • FIG. 9 is a circuit diagram of a polarity switching circuit according to a third embodiment of the present invention.
  • the polarity switching circuit according to the present invention is used in a DC voltage feeding system for supplying a DC voltage to a load driven by a DC voltage, and when a DC power supply is added to the feeding system, the load is connected. It detects the polarity of the two feed conductors and matches the polarity of the DC power supply to the polarity of the feed conductors.
  • the polarity switching circuit 20 is generally incorporated in a power supply unit 40 including a DC power supply 10 as shown in FIG.
  • a plurality of feed units 40 are connected in parallel with each other to supply a DC voltage, for example, a voltage of 12 V, to the plurality of loads 2 connected to the feed conductors 1A and IB. .
  • DC power supply 10 in power supply unit 40 is connected to commercial AC power supply via switch 12, converts an AC voltage to a DC voltage, and converts the DC voltage through polarity switching circuit 20.
  • Power supply conductor 1A Supplied to IB.
  • the load 2 one that can perform information communication using this feeding conductor can be used.
  • the termination device 3 is connected to the feeding system, and the feeding unit 40 is connected to the feeding unit 40.
  • an impedance adjustment unit 30 is provided to separate the high frequency communication signal flowing to the feed conductors 1A and IB from the polarity switching circuit 20.
  • FIG. 1 shows a polarity switching circuit according to a first embodiment of the present invention, and is composed of four MOSFETs.
  • SW1 to SW4 force positive and negative input terminals IN + and IN ⁇ and first and second output terminals OUTl , And OUT2 are bridged.
  • the positive input terminal IN + is connected to the positive electrode of the DC power supply 10
  • the negative input terminal IN ⁇ is connected to the negative electrode of the DC power supply.
  • the first switch SW1 is inserted between the positive input terminal IN + and the first output terminal OUT1, and the source S is Connect to the positive input terminal IN + and connect the drain D to the first output terminal OUT1.
  • the second switch SW2 is inserted between the positive input terminal IN + and the second output terminal OUT2, and the source S is connected to the positive input terminal IN + and the drain D is connected to the second output terminal OUT2.
  • the third switch SW3 is inserted between the negative input terminal IN ⁇ and the first output terminal OUT1, and the source S is connected to the negative input terminal IN ⁇ and the drain D is connected to the first output terminal OUT1.
  • the fourth switch SW4 is inserted between the negative input terminal IN ⁇ and the second output terminal OUT2, and the source S is connected to the negative input terminal IN ⁇ and the drain D is connected to the second output terminal OUT2.
  • the switching elements that are M0SFETs that form the first switch SW1 and the second switch are P-type transistors that conduct when the source voltage is higher than the gate voltage, and the MOSFETs that form the third switch SW3 and the fourth switch SW4
  • the switching element is an N-type transistor that conducts when the gate voltage is higher than the source voltage.
  • the gate G of the switching element which is a MOSFET constituting the first switch SW1 is connected to the second output terminal OUT2 together with the gate G of the switching element of the third switch SW3.
  • the gate G of the switching element constituting the second switch SW2 is connected to the first output terminal OUT1 together with the gate G of the switching element of the fourth switch SW4.
  • the gate of each switching element is a control terminal to which a voltage for determining on / off of each switch is applied, and on / off control of each switch is performed based on the magnitude relationship between the source voltage and the gate voltage. Is done.
  • each switch inherently have parasitic capacitances C1 to C4 between the gate and the source, and the parasitic capacitances Cl and C2 at the first switch SW1 and the second switch SW2 are each 1000 pF, respectively.
  • the parasitic capacitances C3 and C4 at the third switch SW3 and the fourth switch SW4 are 300 pF respectively. This value is merely an example, and can be changed as necessary.
  • the magnitude relation between Cl, C2 and C3, C4 is also reversed between the P-type and N-type switches. is there.
  • each switching element resistors R1 to R4 are respectively connected in series with parasitic capacitances C1 to C4 to form a delay circuit, and a connection point between the resistance and the parasitic capacitance is connected to the gate of each switching element. Ru.
  • Each delay circuit changes the timing at which each switching element becomes conductive by adjusting the charge rate to the parasitic capacitance, and as described later, When the feed unit is first connected to the system, one of the first switch SW1 and the second switch is set to operate preferentially to determine the polarity of the feed conductor 1A, IB.
  • the voltage output to the first output terminal OUT1 and the second output terminal OUT2 is the current supplied from the power supply conductors 1A and IB. It is intended to match the voltage according to the polarity, and to facilitate the additional connection work of the feed unit 40 by eliminating the need for the operator to check in advance the polarity of the feed conductor.
  • the feeding conductor 1A is a positive electrode to which a voltage of +12 V is applied
  • the feeding conductor 1B is a negative electrode to which a voltage of 0 V is applied
  • the DC power supply supplies a DC voltage of 12 V. .
  • the positive voltage 12 V from the DC power supply is applied to the source S of the first switch SW1 and the second switch SW2, and the source S of the third switch SW3 and the fourth switch are both DC current source 0V is applied.
  • 12 V is applied to the first output terminal OUT1, and 0 V is applied to the second output terminal OUT2.
  • the first switch SW1 0 V from the second output terminal OUT2 becomes the gate voltage, and the relationship of gate voltage (0 V) ⁇ source voltage (12 V) is satisfied, and the first switch SW1 is turned on.
  • the second switch SW2 both the gate voltage and the source voltage become 12 V, and the on condition (gate voltage and source voltage) is not satisfied, and the switch SW2 is turned off, and the second switch SW2 is turned off.
  • both the source voltage and the gate voltage become 0 V, and are turned off because the on condition (gate voltage> source voltage) is not satisfied, and in the fourth switch SW4, the gate voltage (12 V) > The source voltage (0 V) is set, and the fourth switch SW4 turns on.
  • the positive voltage 12 V from the DC power supply is applied to the source S of the first switch SW1 and the second switch SW2, and the source S of the third switch SW3 and the fourth switch are both DC current source Is applied.
  • 0 V is applied to the first output terminal OUT1 from the feed system, and 12 V is applied to the second output terminal OUT2.
  • the switch SW1 in the first switch SW1, 12 V from the second output terminal OUT2 becomes the gate voltage, and the on condition (gate voltage and source voltage) is not satisfied, and the switch SW1 is turned off.
  • the second switch SW2 turns on as the gate voltage (OV) and the source voltage (12 V).
  • the gate voltage (12 V)> the source voltage (OV) is turned on.
  • both the gate voltage and the source voltage become OV, and the on condition (gate voltage> source voltage) is not satisfied, and it is turned off. Therefore, only the second switch SW2 and the third switch SW3 are turned on, the positive voltage 12V of the DC power is applied to the second output terminal OUT2, and the negative voltage OV of the DC power is applied to the first output terminal OUT2.
  • the DC power supply is added to the power supply system with the polarity according to the polarity of the power supply system already in operation.
  • the first output terminal OUT1 and the second output terminal OUT2 No substantial voltage is applied.
  • 12 V is applied to the gates G of the first switch SW1 and the second switch SW2 from the positive electrode input terminal IN + via the parasitic capacitances C1 and C2, charging of the parasitic capacitances Cl and C2 is started.
  • Ru Immediately after the connection, the first switch SW1 and the second switch SW2 both have a gate voltage of 12 V and a source voltage of 12 V, so the gate parasitic capacitances Cl and C2 are charged.
  • the fourth switch SW4 is turned off immediately after connection because both the gate voltage and the source voltage are 0 V, but the first switch SW1 turns on and the voltage of the first output terminal OUT1 becomes 12 V.
  • the gate voltage is 12 V
  • the on condition gate voltage and source voltage
  • the positive electrode 12V of the DC power supply is preferentially applied to the first output terminal OUT1.
  • the second switch SW2 turns on first immediately after connection, the second switch SW2 and the third switch SW3 turn on, and the first switch SW1 and the fourth switch (Ii)
  • the SW4 is turned off to give a positive voltage of 12 V to the second output terminal OUT2, and the negative electrode of OV to the first output terminal OUT1.
  • the first switch SW1 is set to turn on earlier than the second switch SW2 with a clear difference between the resistance values of the resistors R1 and R2, but the charge times of each switch are set. Between the paths, due to variations in resistance and parasitic capacitance, it is expected that there will be a difference in time constant. Therefore, using such variations, the pair of the first switch SW1 and the fourth switch SW4, and the fourth switch SW4 are used. It is determined that one of the pair of the 2nd switch SW2 and the 3rd switch SW3 is turned on preferentially to make either of the power supply conductors 1A and IB positive. After that, when adding the feed tube 40, as described above, the polarity of the feed conductors 1A and IB is determined, and the output polarity of the feed unit to be added matches the polarity of the existing feed system. Ru.
  • the time constants of the charging circuit of the first switch SW1 and the second switch SW2 are expected to differ depending on the variations of the resistors R1 and R2 and the parasitic capacitances Cl and C2. If the time constant of the charging circuit in the third switch SW3 and the fourth switch SW4 is different due to the variation in resistance and parasitic capacitance, the combination of the first switch SW1 and the fourth switch SW4, It is determined that one of the pair of the second switch SW2 and the third switch SW3 is turned on preferentially, and that one of the feed conductors 1A and IB is used as the positive electrode.
  • the first switch SW1 and the second switch SW2 are both temporarily turned on, and a voltage of 12 V is applied to the first output terminal OUT1 and the second output terminal OUT2.
  • this voltage is applied between the resistors R3 and R4 and the parasitic capacitances C3 and C4, respectively, between the negative input terminal IN-(0 V) to charge the parasitic capacitances C3 and C4 of each charging circuit.
  • the source voltage of the third switch SW3 and the fourth switch SW4 is OV of the same potential as that of the negative input terminal, the time constant of the charging circuit of the fourth switch SW4 is that of the charging circuit of the third switch SW3.
  • the charging speed to the parasitic capacitances C3 and C4 differs, and the gate voltage of the fourth switch SW4 rises faster than the third switch SW3, so that the fourth switch SW4 First turns on and determines the second output terminal OUT2 to be negative.
  • the gate voltage of the third switch SW3 is fixed at OV and becomes equal to the source voltage (OV), so that the third switch SW3 is turned off.
  • the gate voltage of the first switch SW1 is fixed to OV, the on state of the first switch SW1 is determined, and accordingly, the first output terminal OUT1 is fixed to 12 V, whereby the second switch SW2 is turned on.
  • the gate voltage is fixed at 12 V, and the second switch SW2 is turned off.
  • the positive terminal of the DC power supply is provided to the first output terminal OUT1.
  • the time constant of the charging circuit of the third switch SW3 is smaller than the time constant of the charging circuit of the fourth switch SW4, the charging speed to the parasitic capacitances C3 and C4 will be different.
  • the fourth switch SW4 and the first switch SW1 are turned off, the second switch SW2 is turned on, and the positive electrode from the DC power supply is applied to the second output terminal OUT2.
  • the time constant of the charging circuit of the first switch and the second switch, and the time constant of the charging circuit of the third switch and the fourth switch are due to variations in resistances R1 to R4 and parasitic capacitances C1 to C4.
  • the positive terminal of the DC power supply is output to the terminal OUTl.
  • 4 to 6 show modifications of the polarity switching circuit described above. In the modification of FIG.
  • the resistors R1 and R2 are connected only to the first switch SW1 and the second switch SW2, and charging is performed.
  • An example is shown in which the paths are formed and the values of R1 and R2 are different, and in the modification of FIGS. 5 and 6, the resistors R3 and R4 are connected only to the third switch SW3 and the fourth switch SW4, An example is shown in which the values of R3 and R4 are different.
  • the charging circuit is added to the corresponding switch using the parasitic capacitance of the switching element, but the present invention is not necessarily limited thereto.
  • FIG. 7 shows still another modification of the polarity switching circuit of the above-described embodiment.
  • R11, R21, R31 and R41 are connected to the resistors R1 to R4 that make up each charge circuit, respectively, and the voltage applied to the gate of each switching element is lowered. It is suppressed.
  • This configuration is useful for protecting the switching device when the output voltage of the DC power supply 10 is, for example, 24 V and exceeds the allowable gate voltage 'source voltage' of the MOSFET used as the switching device.
  • the first voltage dividing resistor R11 is connected in series with the first resistor R1 between the positive input terminal IN + and the second output terminal OUT2, and the first voltage dividing resistor R11 and the first resistor are connected.
  • the gate G of the switching element is connected to the connection point between R1.
  • the second voltage dividing resistor R21 is connected in series with the second resistor R2 between the positive input terminal IN + and the first output terminal OUT1, and the second voltage dividing resistor R21 and the second resistor
  • the gate G of the switching element is connected to the connection point between R2.
  • the third voltage dividing resistor R31 is connected in series with the third resistor R3 between the negative input terminal IN ⁇ and the second output terminal OUT2, and the third voltage dividing resistor R31 and the third voltage dividing resistor R31 are connected to each other.
  • the gate G of the switching element is connected to the connection point between the resistors R3.
  • the fourth voltage-dividing resistor R41 is connected in series with the fourth resistor R4 between the negative input terminal IN ⁇ and the first output terminal OUT1, and the fourth voltage-dividing resistor R41 and the fourth voltage-dividing resistor R41
  • the gate G of the switching element is connected to the connection point between the four resistors R4.
  • Zener diode ZD1, ZD2, ZD3 and ZD4 are connected in series to each voltage dividing resistance Rll, R21, R31 and R41 respectively. That is, the first Zener diode ZD1 is inserted between the first voltage dividing resistor R11 and the positive input terminal IN +, and the second Zener diode ZD2 is inserted between the second voltage dividing resistor R21 and the positive input terminal IN +.
  • the third Zener diode ZD3 is inserted between the third voltage dividing resistor R31 and the negative input terminal IN-, and the fourth Zener diode ZD4 is inserted between the fourth voltage dividing resistor R41 and the negative input terminal IN- Inserted between
  • FIG. 8 shows a polarity switching circuit according to a second embodiment of the present invention.
  • a bipolar transistor is used as each of the switches SW1 to SW4, and a control circuit 100 for detecting the potentials of the first output terminal OUT1 and the second output terminal OUT2 to control each switch is provided.
  • the first switch SW1 is an NPN type bipolar transistor, the collector is coupled to the positive input terminal IN + and the emitter is connected to the first output terminal OUT1, and becomes conductive when the base voltage exceeds the threshold, the positive input terminal Connect IN + to the first output terminal OUT1.
  • the second switch SW2 is an NPN type bipolar transistor, the collector is coupled to the positive input terminal IN +, the emitter is connected to the second output terminal OUT2, and the base voltage becomes higher than the threshold value. Connect terminal IN + to the second output terminal OUT2.
  • the third switch SW3 is a PNP bipolar transistor, which has a collector coupled to the negative input terminal IN-, a emitter connected to the first output terminal OUT1, and a conductor connected when the base voltage is below the threshold.
  • the fourth switch SW4 is a PNP bipolar transistor, the collector is coupled to the negative input terminal and the emitter is connected to the second output terminal OUT2, and becomes conductive when the base voltage becomes lower than the threshold value, and the negative input terminal Connect IN- to the 2nd output terminal.
  • the control circuit 100 is configured to detect the first potential applied to the first output terminal OUT1 and the second potential applied to the second output terminal OUT2 to control the respective switches SW1 to SW4. , To achieve the following functions.
  • a control voltage equal to or greater than the threshold is applied to each base of the first switch SW1 and the third switch SW3, and the second switch SW2 and the fourth switch SW Give each of the four bases a control voltage below the threshold.
  • the control circuit 100 detects a first potential applied to the first output terminal OUT1, and outputs a first detection signal when the first potential is equal to or higher than a predetermined value.
  • a second detection unit (a comparator) that detects a second potential applied to the detection means (comparator) 101 and the second output terminal OUT2, and outputs a second detection signal when the second potential is equal to or higher than a predetermined value.
  • logic means (NOR gate) 110 for giving a predetermined control voltage to the determination means (OR gate) 130 only when both of the first detection signal and the second detection signal are not simultaneously present.
  • the second detection voltage is commonly applied to the bases of the second switch SW2 and the fourth switch SW4, and is set to the above threshold value or more.
  • Judgment means 130 applies a drive voltage exceeding the threshold of the base voltage to the bases of the first switch SW1 and the third switch SW3 when receiving at least one of the control voltage and the first detection voltage.
  • the control circuit 100 includes a resistor R5, a capacitor C5, and a comparator 121, and is provided with a delay means 120. After delaying the control voltage output from the logic means (NOR gate) 110, this is determined. Output to
  • the output voltage of the DC power supply and the operating voltage in the power supply system are 12 V
  • the first detection unit 101, the second detection unit 102, the logic unit 110, the determination unit 130 These outputs are 12 V or 0 V, and in practice they can be different values in terms of circuit design.
  • the first output terminal OUT1 When the first output terminal OUT1 is connected to the positive feed conductor 1A, and the second output terminal OUT2 is connected to the negative feed conductor 1B Assuming that the voltage applied to the first output terminal OUTl is 12 V, the voltage applied to the second output terminal OUT2 is 0 V, and the reference values at the first detection means 101 and the second detection means 102 are less than 12 V, The first detection means 101 outputs a voltage signal of 12 V as the first detection signal, and the output of the second detection means 102 becomes 0 V and does not output the second detection signal. As a result, the output of the logic means 110 becomes 0 V and does not output the control voltage. Therefore, the delay unit 120 does not operate, and an output of 0 V is input to the determination unit 130.
  • the determination means 130 receives the first detection signal of 12 V from the first detection means 101 and applies a drive voltage of 12 V to the bases of the first switch SW1 and the third switch SW3. As a result, the first switch SW1 is turned on and the third switch SW3 is turned off. On the other hand, the second detection signal is not given to the bases of the second switch SW2 and the fourth switch SW4 because the output from the second detection means 102 is 0 V, and the second switch SW2 is turned off. Switch SW4 is turned on.
  • the output of the first detection means 101 is 0 V and does not output the first detection signal, and the second detection means 102 outputs a 12 V second detection signal.
  • the output of the logic means 110 is 0V
  • the control voltage is not output
  • the delay circuit 120 does not operate
  • one input of the determination means 130 is 0V. Since 0 V output from the first detection means 101 is input to the other input of the determination means 130, the determination means 130 outputs 0 V and the drive voltage is set to the first switch SW1 and the third switch SW3. Do not give to the base of. As a result, the first switch SW1 is turned off and the third switch SW3 is turned on.
  • the 12V second detection signal from the second detection means 102 is applied to the bases of the second switch SW2 and the fourth switch SW4, the second switch SW2 is turned on, and the fourth switch SW4 is turned off.
  • the second switch SW2 and the third switch SW3 are turned on, the positive input terminal IN + is connected to the second output terminal OUT2, and the negative input terminal IN- is connected to the first output terminal OUT1.
  • the DC power supply is added to the power supply system with a polarity according to the polarity of the power supply system. 3)
  • the first detection unit 101 and the second detection unit 102 both output OV and do not output the first detection signal and the second detection signal.
  • the logic means 110 outputs a control voltage of 12 V, and this output is sent to the judging means 130 via the delay circuit 120.
  • the delay means 120 delays the control voltage of 12 V and outputs it to the determination means 130, so that the output of 0 V from the delay means 120 and 0 V from the first detection means 101 are inputted to the determination means 130 first.
  • the determination means 130 outputs 0 V and does not give a drive voltage
  • the determination means 130 outputs a 12 V drive voltage.
  • the first switch SW1 is turned on and the third switch SW3 is turned off.
  • the third switch SW3 is turned off by the 0V output from the second detection means 102, and the fourth switch SW4 is turned on. Therefore, when the power supply unit is connected to the power supply system for the first time, only the first switch SW1 and the fourth switch SW4 are turned on to preferentially apply the positive electrode 12V of the DC power supply to the first output terminal OUT1. become.
  • FIG. 9 shows a polarity switching circuit according to a third embodiment of the present invention.
  • an electromagnetic relay is used as each of the switches SW1 to SW4, and a control circuit 100 similar to that of the second embodiment is provided.
  • the first switch SW1 is a normally open relay having a drive coil, and the common terminal (COM) is connected to the positive input terminal IN +, the NO contact is connected to the first output terminal, and the drive coil is When energized, the NO contact closes and connects the positive input terminal IN + to the first output terminal OUT1.
  • the second switch SW2 is a normally open relay having a drive coil, and the common terminal (COM) is connected to the positive input terminal IN +, the NO contact is connected to the second output terminal OUT2, and the drive coil is excited. , NO contact closes, connect positive input terminal IN + to second output terminal 0 UT2.
  • the third switch SW3 is a normally closed relay having a drive coil, the common terminal (COM) is connected to the negative input terminal IN ⁇ , the NC contact is connected to the first output terminal OUT1, and the drive coil is excited.
  • the NC contact opens and the negative input terminal IN- to the 1st output terminal Disconnect from OUT1.
  • the fourth switch SW4 is a normally closed relay having a drive coil, the common terminal (COM) is connected to the negative input terminal IN ⁇ , the NC contact is connected to the second output terminal OUT2, and the drive coil is excited. At the same time, the NC contact opens and disconnects the positive input terminal IN + from the second output terminal OUT2.
  • the control circuit 100 detects the first potential applied to the first output terminal OUT1, and outputs the first detection voltage when the first potential is equal to or higher than a predetermined value.
  • Detection means 101 and a second detection means 102 for detecting a second potential applied to the second output terminal OUT2 and outputting a second detection voltage when the second potential is equal to or higher than a predetermined value;
  • a logic means is provided for providing a predetermined control voltage to the determining means 130 only when both the detection signal and the second detection signal are not simultaneously present.
  • the control circuit 100 excites drive coils of the first switch SW1 and the third switch SW3 when the first potential is larger than the second potential, and the second potential is larger than the first potential.
  • Delay means 120 is provided to excite the drive coils of the first switch SW1 and the third switch SW3 with delay.
  • the second detection voltage from the second detection means 102 is applied to the exciting coil of the second switch SW2 and the fourth switch SW4, and the determination means 130 determines whether the control voltage and the first detection voltage described above are small. When it receives either one of them, it is configured to apply a drive voltage for exciting the exciting coil of the first switch SW1 and the third switch SW3, and the delay means 120 delays this control voltage and applies it to the determination means 130 R5, C5) are provided.
  • the output voltage of the DC power supply and the operating voltage in the power supply system are 12 V
  • the first detection unit 101, the second detection unit 102, the logic unit 110, the determination unit 130 These outputs are 12 V or 0 V, and in practice they can be different values in terms of circuit design.
  • the voltage applied to the first output terminal OUT1 is 12 V
  • the voltage applied to the second output terminal OUT2 Is OV and the reference value in the first detection means 101 and the second detection means 102 is less than 12 V
  • the first detection means 101 outputs a voltage of 12 V as the first detection signal
  • the second detection means 102 The output is 0 V and does not output the second detection signal.
  • the logic means 110 outputs 0 V and the delay means 120 does not operate.
  • the determination means 130 receives the 0V input from the first detection means 101 and the 0V output from the delay means 120 and applies a 12V drive voltage to the drive coils of the first switch SW1 and the third switch SW3.
  • the first detection means 101 outputs 0 V and does not output a first detection signal
  • the second detection means 102 outputs a 12 V second detection signal.
  • the logic circuit 110 outputs 0 V and does not supply the control voltage, so the delay circuit 120 does not operate. Therefore, the determination means 130 outputs 0 V and the drive coils of the first switch SW1 and the third switch SW3 are not excited.
  • the first switch SW1 and the third switch SW3 do not operate, the first output terminal OUT1 is disconnected from the positive input terminal IN +, and the negative input terminal IN- is connected to the first output terminal OUT1.
  • the drive coil of the second switch SW2 and the fourth switch SW4 is excited by the second detection signal of 12 V from the second detection means 102, the NO contact of the second switch SW2 is closed, and the NC of the fourth switch SW4.
  • the contact opens, the positive input terminal IN + is connected to the second output terminal OUT2, and the negative input terminal IN- is disconnected from the second output terminal OUT2.
  • a DC power supply is added to the power supply system with a polarity according to the polarity of the power supply system already in operation.
  • feed conductors 1A and IB are both at 0 V, and in this state, the first output of feed unit 40
  • the first output terminal OUT1 and the second output terminal OUT2 both have a voltage of 0 V
  • the first detection means 101 and the second detection means 102 have the first detection signal. And do not output the second detection signal.
  • the logic means 110 outputs a control voltage of 12 V, and this output is sent to the judging means 130 via the delay circuit 120.
  • the delay means 120 delays the control voltage of 12 V and outputs it to the determination means 130.
  • the determination means 130 initially outputs 0 V from the delay means 120 and the first detection signal of 0 V from the first detection means 101.
  • the output of the judging means 130 is 0 V and does not output the driving voltage
  • the control voltage of 12 V is inputted from the delay means 120 to the judging means 130, and the judging means 130 outputs the driving voltage of 12 V.
  • the drive coils of the first switch SW1 and the third switch SW3 are excited, the NO contact of the first switch SW1 closes, the NC contact of the third switch SW3 opens, and the positive input terminal IN + becomes the first output terminal OUT1. Connected, the negative input terminal IN- is disconnected from the first output terminal OUT2.
  • the 0 V output from the second detection means 102 does not excite the drive coils of the second switch SW2 and the fourth switch SW4, and the NO contact of the second switch SW2 is kept open.
  • the NC contact is kept closed and the negative input terminal IN- is connected to the second output terminal OUT2. Therefore, when the feed unit is connected to the feed system for the first time, the positive input terminal IN + is connected to the first output terminal OUT1, and the negative input terminal IN- is connected to the second output terminal OUT2, and the first output
  • the positive terminal 12V of the DC power supply is preferentially applied to the terminal OUT1.

Landscapes

  • Direct Current Feeding And Distribution (AREA)
  • Electronic Switches (AREA)

Abstract

Circuit de commutation de polarité en mesure d'ajouter un bloc d'alimentation en courant continu à une ligne d'alimentation avec une polarité correcte sans nécessité de vérification de la polarité d'un système d'alimentation connecté à une charge. Le circuit de commutation de polarité est disposé entre le bloc d'alimentation en courant continu et la charge et connecte le bloc d'alimentation en courant continu à deux conducteurs d'alimentation connectés à la charge. Quatre commutateurs sont raccordés en pont entre deux bornes d'entrée connectées au bloc d'alimentation en courant continu et deux bornes de sortie connectées aux conducteurs d'alimentation. Deux commutateurs sont allumés et les deux autres commutateurs sont éteints en fonction de la polarité du conducteur d'alimentation connecté à la première borne de sortie.
PCT/JP2007/062283 2006-06-27 2007-06-19 Circuit de commutation de polarité et unité d'alimentation WO2008001644A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN2007800243001A CN101479907B (zh) 2006-06-27 2007-06-19 极性切换电路及供电单元
JP2008522467A JP4925363B2 (ja) 2006-06-27 2007-06-19 極性切換回路及び給電ユニット

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2006176654 2006-06-27
JP2006-176654 2006-06-27

Publications (1)

Publication Number Publication Date
WO2008001644A1 true WO2008001644A1 (fr) 2008-01-03

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PCT/JP2007/062283 WO2008001644A1 (fr) 2006-06-27 2007-06-19 Circuit de commutation de polarité et unité d'alimentation

Country Status (3)

Country Link
JP (1) JP4925363B2 (fr)
CN (1) CN101479907B (fr)
WO (1) WO2008001644A1 (fr)

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CN102447279A (zh) * 2010-09-29 2012-05-09 富晶电子股份有限公司 用于充电器的极性切换电路
EP2639917A3 (fr) * 2012-02-03 2017-12-06 Samsung Electronics Co., Ltd Alimentation électrique CC
JP2018153089A (ja) * 2013-03-12 2018-09-27 アセンシア・ディアベティス・ケア・ホールディングス・アーゲー バッテリーで電力供給されるデバイスのための逆バッテリー保護
CN109088391A (zh) * 2018-09-18 2018-12-25 Tcl-罗格朗国际电工（惠州）有限公司 短路保护电路及非标poe供电器

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CN106329963B (zh) * 2016-07-05 2019-05-28 濮阳市立圆汽车电器有限公司 一种电源用桥式切换装置
CN109910650B (zh) * 2019-04-03 2021-09-17 上海歌尔泰克机器人有限公司 一种接触式充电装置及无人机

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JPH07271460A (ja) * 1994-03-31 1995-10-20 Aiphone Co Ltd 直流電源給電回路
JPH09135529A (ja) * 1995-11-08 1997-05-20 Nippon Telegr & Teleph Corp <Ntt> 直流電源システム
JPH11127178A (ja) * 1997-10-24 1999-05-11 Matsushita Electric Works Ltd 信号伝送システムの給電装置
JPH11332094A (ja) * 1998-05-08 1999-11-30 Advanced Circuit Technologies:Kk 電源の接続極性に関わりなく正規の極性で負荷に電源を印加するための自動スイッチ回路
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Publication number Priority date Publication date Assignee Title
CN102447279A (zh) * 2010-09-29 2012-05-09 富晶电子股份有限公司 用于充电器的极性切换电路
EP2639917A3 (fr) * 2012-02-03 2017-12-06 Samsung Electronics Co., Ltd Alimentation électrique CC
JP2018153089A (ja) * 2013-03-12 2018-09-27 アセンシア・ディアベティス・ケア・ホールディングス・アーゲー バッテリーで電力供給されるデバイスのための逆バッテリー保護
CN109088391A (zh) * 2018-09-18 2018-12-25 Tcl-罗格朗国际电工（惠州）有限公司 短路保护电路及非标poe供电器
CN109088391B (zh) * 2018-09-18 2023-10-17 罗格朗智能电气(惠州)有限公司 短路保护电路及非标poe供电器

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CN101479907A (zh) 2009-07-08
CN101479907B (zh) 2011-07-13
JP4925363B2 (ja) 2012-04-25
JPWO2008001644A1 (ja) 2009-11-26

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