WO2007114334A1 - 回路基板、回路基板の検査方法、およびその製造方法 - Google Patents
回路基板、回路基板の検査方法、およびその製造方法 Download PDFInfo
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- WO2007114334A1 WO2007114334A1 PCT/JP2007/057094 JP2007057094W WO2007114334A1 WO 2007114334 A1 WO2007114334 A1 WO 2007114334A1 JP 2007057094 W JP2007057094 W JP 2007057094W WO 2007114334 A1 WO2007114334 A1 WO 2007114334A1
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- solder
- circuit board
- force
- mer
- melting point
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Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3442—Leadless components having edge contacts, e.g. leadless chip capacitors, chip carriers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
Definitions
- Circuit board circuit board, method of inspecting circuit board, and method of manufacturing the same
- the present invention relates to a circuit board on which an electronic component is mounted, and more particularly to a technique for inspecting the presence or absence of solder remelting.
- active components for example, semiconductor elements
- passive components for example, capacitors
- the degree of freedom in arranging electronic components is increased compared to the case of surface mounting, the improvement of high frequency characteristics can be expected by optimizing the wiring between the electronic components.
- LTCC low-temperature ceramic
- LSI semiconductor devices
- the circuit component built-in module 400 shown in FIG. 1 includes a substrate 401 on which insulating substrates 40 la, 401 b, and 401 c are stacked, and lines, line notches 402 a, 402 b, formed on the main surface and the inner surface of the substrate 401. 402 c and 402 d, and a circuit component 403 disposed inside the substrate 401 and connected to a wiring pattern.
- Wiring patterns 402a, 402b, 402c, and 402d are electrically connected by inner vias 404 and
- the insulating substrates 401a, 401b, and 401c are composed of a mixture containing an inorganic filler and a thermosetting resin.
- Patent Document 1 Japanese Patent Application Laid-Open No. 11 220262
- circuit component built-in module 400 since the circuit components 403 (403a and 403b) are embedded in the insulating substrate 401, the circuit component 403 and the line component 402 (402a and 402b) are not included. , 402c), it is very difficult to easily detect the quality of soldering electrically connected. In particular, even if the solderability of the circuit component built-in module 400 itself is confirmed by an electrical inspection or the like, the circuit component built-in module 400 is built-in at the time of secondary mounting on a wiring board such as a mass board. It is extremely difficult to confirm whether the solder has remelted and becomes defective.
- solderability When the circuit component is not embedded, a pad for evaluating solderability is prepared as proposed in, for example, JP-A-8-298360, and solder is removed by reflow or the like. After dissolution, it is possible to evaluate solderability by inspecting the size of the wetting spread by appearance or measuring the electrical resistance between pads.
- the remelting test of the solder should be carried out using the soldering inspection method proposed in JP-A-8-298360. You can't.
- the inability to inspect the solder re-melting means that even if it appears that the circuit parts are electrically connected by the solder, it actually moves physically due to the re-melting of the solder, resulting in insulation. Deterioration may occur, or remelting of the solder may cause voids in the solder, resulting in reduced reliability.
- the present invention has been made in view of the above-mentioned point of view, and a main object of the present invention is to provide a component-embedded substrate or circuit substrate having a solder mer force capable of inspecting re-melting of solder. .
- the circuit board of the present invention is a circuit board of the present invention.
- the solder mer force is composed of a first solder having a first melting point, and the electronic component is mounted on the insulating layer by a second solder having a second melting point lower than the first melting point. Be done.
- the method of inspecting the characteristics of the circuit board according to the present invention is a method of inspecting the characteristics of the circuit board when connecting another electric member to the circuit board on which the electronic component is mounted by solder.
- the circuit board is previously provided with a solder mer force having a first melting point, and the other electrical member is connected to the circuit board,
- the method for producing a circuit board of the present invention is
- a method of manufacturing a circuit board on which an electronic component is mounted comprising:
- the circuit board is provided with a solder mer force composed of a first solder having a first melting point, and the electronic component is mounted on the circuit board by a solder having a melting point equal to the first melting point.
- the remelting of the solder having the first melting point can be inspected by detecting the solder mer's force provided in the wiring substrate.
- FIG. 1 is a perspective view showing a configuration of a component built-in board including an embodiment of the present invention.
- FIG. 2A The configuration of the circuit board 100 provided with the solder mer force 10 according to the embodiment of the present invention It is a sectional view shown typically.
- FIG. 2B A sectional view schematically showing a configuration of a circuit board 100 provided with a solder mer force 10 according to an embodiment of the present invention.
- FIG. 3A It is a X-ray fluoroscopic top view of the solder mer force 10 shown to FIG. 2A.
- FIG. 3B is an X-ray transparent top view of the solder mer force 10 shown in FIG. 2B.
- FIG. 4B A sectional view schematically showing a configuration of a circuit board 100 provided with a solder mer force 10 according to an embodiment of the present invention.
- FIG. 5A A sectional view schematically showing a configuration of a circuit board 100 provided with a solder mer force 10 according to an embodiment of the present invention.
- FIG. 5B A sectional view schematically showing a configuration of a circuit board 100 provided with a solder mer force 10 according to an embodiment of the present invention.
- FIG. 6A is a cross-sectional view of a first process for illustrating a method of manufacturing a component built-in substrate according to an embodiment of the present invention.
- FIG. 7A is a cross-sectional view of a fifth step for illustrating the method of manufacturing the component built-in substrate according to the embodiment of the present invention.
- 7C is a seventh process sectional view for illustrating a method of manufacturing a component built-in board according to an embodiment of the present invention.
- FIG. 8A A first method for explaining a method of detecting a component built-in substrate according to an embodiment of the present invention It is process sectional drawing.
- FIG. 10A is a cross-sectional view of a first step of the inspection method of the mounted body according to the embodiment of the present invention.
- FIG. 10B is a cross-sectional view of a second step for illustrating the method of manufacturing a mounted body according to the embodiment of the present invention.
- FIG. Ll A phase diagram of the Sn_Sb system.
- FIG. 12A is a view showing the relationship between conductive particles and melting point (solid line).
- FIG. 13A is a top view of the solder mer's force 10 as viewed from above.
- FIG. 13B is a top view of the solder mer force 10 as viewed from above.
- FIG. 14A is a top view showing the shape of a solder-mer force 10.
- FIG. 14B A top view showing the shape of the solder-mer force 10.
- FIG. 14C is a top view showing the shape of the solder-mer force 10.
- FIG. 14D is a top view showing the shape of the solder-mer force 10.
- FIG. 15A A sectional view schematically showing a configuration of a circuit board 100 provided with a solder mer force 10 according to an embodiment of the present invention.
- circuit board 100 It is a sectional view showing typically composition of circuit board 100 provided with solder mer's power 10 in an embodiment of the present invention.
- FIG. 16A A cross-sectional view schematically showing a configuration of a circuit board 100 provided with a solder mer force 10 according to an embodiment of the present invention.
- 16B A sectional view schematically showing a configuration of a circuit board 100 provided with a solder mer force 10 according to an embodiment of the present invention.
- 7A A sectional view schematically showing a configuration of a circuit board 100 provided with a solder mer force 10 according to an embodiment of the present invention.
- FIG. 7B A sectional view schematically showing a configuration of a circuit board 100 provided with a solder mer force 10 according to an embodiment of the present invention.
- a circuit board according to an embodiment of the present invention will be described with reference to FIG.
- FIGS. 2A and 2B schematically show a cross-sectional structure of the circuit board 100 provided with the solder mer force 10 of the present embodiment.
- FIG. 2A is a state of solder force 10 showing that the solder has not remelted
- FIG. 2B is a state of solder strength 10 showing that the solder has remelted.
- FIG. 2A shows the state before reflow
- FIG. 2B shows the state after reflow.
- the circuit board 100 constitutes, for example, a primary board to be secondarily mounted on a secondary board (a mother board) 51, 200 which is an example of another electric member.
- circuit board 100 is provided with the structure shown in FIG. 1 as an entire structure, and electronic components are mounted on the inside of the substrate, the surface of the substrate, or the inside of the substrate and the surface of the substrate. Electronic parts are not shown in part of the drawings for explaining the present embodiment including 2B etc. doing.
- the circuit board 100 of the present embodiment includes an upper layer substrate 22, a lower layer substrate 21, and a connection resin layer 24 connecting the upper layer substrate 22 and the lower layer substrate 21.
- the connecting resin layer 24 is made of an insulator, and the upper substrate 22 and the lower substrate 21 constitute an insulating layer 20.
- the solder force 10 of this embodiment is composed of the first solder 12 and provided between the insulating layers 20.
- the first solder 12 is composed of a solder having a first melting point, for example, Sn_Sb as a main component.
- the solder force 10 is stored in a storage chamber 25 provided inside the circuit board 100. Specifically, the solder force 10 is disposed on the electrode pattern 23 exposed to the storage chamber 25.
- a first electronic component (not shown) is provided on upper surface 20a or lower surface 20b of circuit board 100, and the first electronic component is mounted on circuit board 100 by a second solder (not shown). Be done.
- the second solder has a second melting point lower than the first melting point.
- the second solder is made of, for example, Pb free solder.
- a second electronic component (not shown) may be provided inside the insulating layer 20 (specifically, between the upper substrate 22 and the lower substrate 21), in which case the circuit substrate 100
- the component-embedded substrate in the form in which the electronic components of
- the connecting resin layer 24 is made of a composite sheet composed of a resin and an inorganic filler.
- the hammer force 10 is disposed between the upper layer substrate 22 and the lower layer substrate 21.
- the solder mer force 10 is composed of the unmelted first solder.
- a storage chamber 25 is formed in part of the connecting resin layer (composite sheet) 24, and a solder mer's force 10 is provided in the storage chamber 25. More specifically, the solder force 10 is disposed on the electrode pattern 23 of the lower substrate 21 exposed in the storage chamber 25.
- the solder-mer force 10 of the illustrated example is composed of the first solder 12, and the first solder 12 is placed on the electrode pattern 23 through the flux 14.
- the solder mer force 10 is a marker for checking re-melting of the solder, and when the solder mer force 10 reaches a predetermined temperature (specifically, the first melting point, that is, the melting point of the first solder 12), The solder 12 of 1 is melted to be in the state shown in FIG. 2B.
- FIG. 2B shows a third solder that is a connection material for a second electronic component (not shown) mounted on circuit board 100 when circuit board 100 reaches a predetermined temperature (first melting point) or higher.
- first melting point a predetermined temperature
- the first solder 12 constituting the solder mer force 10 melts and spreads wet on the electrode pattern 23. Then, the first solder 12 in the unmelted state shown in FIG. 2A is compared with the first solder 12a in the melted, wetted and spread state shown in FIG. 2B. Specifically, the shape and characteristics of the solder mer force 10 (the first solder 12 in the unmelted state and the first solder 12a in the melted state) are confirmed. This makes it possible to detect whether remelting has occurred in the third solder which is the connection material of the second electronic component. Remelting of the third solder occurs when the circuit board 100 is exposed to a temperature above the first melting point (ie, the first melting point).
- the electrode pattern 23 that forms the general shape of the shape by receiving the first solder 12a in a molten state may be a triangle, a star, a cross, or the like, in addition to the illustrated rectangular one.
- solder mer force inspection (dissolution judgment) can be performed not only by X-ray inspection but also by electrical inspection. Specifically, for example, a configuration in which the solder force 10 consisting of the first solder 12 in an unmelted state is bridged while keeping the insulation of both patterns separated from each other and adjacent to each other. Place on Then, by detecting the insulation state of both terminals, it is possible to detect the presence or absence of melting of the solder mer force 10 S.
- solder mer force 10 be disposed close to the second electronic component to be inspected (and the third solder as the connecting material).
- the temperature to which electronic components are exposed can be inspected in the vicinity with high accuracy.
- FIG. 4A shows the solder mer force formed by placing the unmelted first solder 12 on the pair of electrode patterns 26, 26. 10 is shown.
- the electrode patterns 26, 26 and the first solder 12 are not metal-bonded, and therefore, a pair of electrode patterns Between 26 and 26 is open (insulated state). That is, as compared with the case where the first solder 12 is melted and the pair of electrode patterns 26, 26 are completely conducted, the first solder 12 is not melted and is between the pair of electrode patterns 26, 26.
- the electrical properties are different (eg high resistance).
- soldermer force 10 first solder 12
- first solder 12 melts when the temperature reaches a predetermined temperature (first melting point) or higher
- first gap between the pair of electrode patterns 26, 26 melts, as shown in FIG. 4B.
- Short with solder 1 2a Therefore, by detecting the short circuit of the solder mer force 10, it can be detected that the circuit board 100 is exposed to a predetermined temperature (first melting point) or higher, or that the first solder 12 is melted.
- a cream solder can also be used as the first solder 12 that constitutes the solder-mer force 10.
- the first solder 12 made of cream solder and the electrode patterns 26, 26 are not metal-joined, and hence the space between the pair of electrode patterns 26, 26 is open.
- the first solder 12 having cream solder strength is melted when the temperature reaches a predetermined temperature (first melting point)
- the melted first solder 12a has a pair of electrodes. Short between patterns 26 and 26.
- This state transition is detected by detecting a short circuit of solder mer's force 10 consisting of tally solder. It can be detected that the circuit board 100 is exposed to a predetermined temperature (first melting point) or that the first solder 12 is melted.
- solder mer force 10 may be embedded in connecting resin layer 24.
- the solder-mer force 10 shown in FIG. 5A is the same as the configuration shown in FIG. 4A, and is formed in a state where the solder-mer force 10 is embedded in the connecting resin layer (composite sheet) 24.
- the solder force 10 shown in FIG. 4A is stored in the storage chamber 25 provided in the connecting resin layer (composite sheet) 24.
- the third solder 32 is formed on a part (land) 31 of the electrode pattern of the lower layer substrate 21.
- the third solder 32 is a cream solder and is formed on the lands 31 by printing.
- An electrode pattern 26 for the solder mer force 10 is formed on the lower layer substrate 21.
- the electrode pattern 26 for the solder mer force 10 may also have the configuration shown in FIG. 2A.
- the second electronic component 30 is placed on the lands 31 of the lower layer substrate 21 via the third solder 32.
- the second electronic component 30 is a chip component (for example, a chip capacitor, a chip inductor, a chip resistor) or a semiconductor element (for example, a bare chip, a chip size 'package (CSP) or the like).
- a chip part is shown as the second electronic part 30.
- the first solder 12 is placed on the electrode pattern 26 to form the solder force 10.
- the first solder 12 constituting the solder mer force 10 has the same material as the third solder 32 for the second electronic component 30 or a melting point (first melting point) equivalent to the melting point of the third solder 32. It is possessed.
- solder (Sn_Sb-based solder) containing Sn_Sb as a main component is used for the first solder 12 and the third solder 32.
- a second electronic component 30 is formed by laminating the upper layer substrate 22 via the connection resin layer 24 on the lower layer substrate 21 on which the second electronic component 30 is mounted. Built in between wiring board 2 and 22. With such a laminated structure, the circuit board 200 having the second electronic component 30 incorporated therein is formed. The solder force 10 is embedded between the upper substrate 21 and the lower substrate 22 in the same manner as the second electronic component 30. As shown in FIG. 4A, the upper substrate It is also possible to store the solder force 10 in the storage chamber 25 after forming the storage chamber 25 between 21 and the lower substrate 22.
- an interlayer connection member (via) that electrically connects the lower layer substrate 21 and the upper layer substrate 22 can be formed in the connection resin layer 24.
- the connecting resin layer 24 is formed of a composite material including a resin (for example, a thermosetting resin and Z or a thermoplastic resin) and an inorganic filler.
- a thermosetting resin is used as the resin.
- the thermosetting resin is, for example, an epoxy resin etc., and when an inorganic filler is added, the inorganic filler is, for example, Al 2 O, SiO 2, Mg ,, BN,
- the connecting resin layer 24 from a composite material containing an inorganic filler.
- a wiring pattern 41 is formed in advance on the upper surface 20a of the upper layer substrate 11, and as shown in FIG. 7B, the second solder 42 is formed on the lands 41 of the wiring pattern.
- cream solder as the second solder 42 is formed on the upper layer substrate 22 by printing.
- the second solder 42 is a solder having a melting point (second melting point) lower than the melting point (melting point of the first melting third solder 32) of the first solder 12 constituting the solder mer force 10. .
- the reason why the second melting point of the second solder 42 is lower than the melting point (first melting point) of the third solder 32 incorporated in the circuit board 200 containing the electronic component is as follows: It is street. That is, if the second melting point of the second solder 42 is higher than the melting point of the third solder 32, connection is made at the first electronic component 30 mounted in the circuit board 200. As a result, the third solder 32a in the molten state remelts. When the melted third solder 32a is remelted, bubbles are generated in the third solder 32 and a defect is likely to occur.
- the third solder 32 may flow out from the initial arrangement position (on the pattern).
- a magnitude relationship is set between the melting points of the third solder 32 for primary mounting and the second solder 42 for secondary mounting so that such remelting does not occur.
- the second solder 42 may be made of conductive particles having a melting point lower than that of the third solder 32 for the primary mounting or the first solder 12 for the solder-mer force.
- Pb-free solder for example, Sn_Ag_Cu-based solder or Sn— ⁇ -based solder having a melting point (second melting point) lower than the melting point (first melting point) of the third solder 32 for primary mounting
- the second solder 42 is composed of Pb solder (Sn — 37 Pb solder).
- the first electronic component 40 is placed on the lands 41 of the upper layer substrate 22 via the second solder 42. Similar to the second electronic component 30, the first electronic component 40 is a chip component and Z or a semiconductor element.
- a second reflow process is performed to melt the second solder 42, and the first electronic component 40 is landed on the land 31 by the melted second solder 42a. Join.
- the first electronic component 40 is mounted on the top surface of the circuit board 200 in which the second electronic component 30 is built.
- the second reflow process is performed at a temperature lower than the first reflow process, and specifically, a temperature at which the third solder 32 is not remelted (less than the melting point (first melting point) of the third solder) It takes place in
- the temperature setting condition of the second reflow process is set to a temperature at which the third solder 32 does not remelt, there is actually a temperature variation in the reflow furnace.
- the temperature of the circuit board here, the component built-in board
- the reflow device measures and controls the temperature inside the furnace, it does not directly measure the temperature of the substrate (component-embedded substrate or circuit board), so the third solder 32
- the reflow setting temperature is set to a temperature that does not remelt, if the temperature inside the substrate actually causes the third solder 32 to remelt, remelting occurs as a real problem. obtain.
- the solder force 10 of the circuit board 200 is detected. That is, it is detected through the solder mer force 10 whether the third solder 32 a in the molten state, which is a connection material of the second electronic component 30 built in the circuit board 200, is not remelted.
- the state (open or short) of the solder-mer force 10 can be determined by performing an electrical inspection. Also shown in Figure 2A, Figure 2B In the case of using the solder-mer force 10, re-melting can be detected by performing X-ray measurement (50).
- solder balls 46 are formed on the lower surface 20b of the circuit board 200 to produce a component built-in module (or component built-in package) 300, as shown in FIG. 9B.
- the state of the solder force 10 can also be determined.
- a double-sided wiring board is used as the lower layer substrate 21, and solder balls (or solder bumps) 46 are formed on terminals (land) 45 of the lower layer substrate 21.
- the formation of the solder balls 46 can be performed S by using solder balls for a Bonore 'grid' array (BGA).
- the component built-in module 300 shown in FIG. 9A or 9B is mounted on a wiring board 51 such as a mass board as shown in FIG. 10A, and a mounting body (component built-in module mounting body) It is also possible to form 350. In that case, as shown in FIG. 10B, a test of remelting in the mounting body 350 can be performed using the solder mer force 10.
- the first solder 12 constituting the solder mer force 10 can use a solder material containing Sn—Sb as a main component.
- the reason for using this solder material is that the melting point can be changed by the content of Sb.
- the phase diagram of the Sn-Sb system is shown in Fig. 11 along with several melting points. For example, the melting point is 232 ° C. when Sb is 0%, and the melting point is 246 when Sb is 10%.
- the Sn--Sb-based solder has a disadvantage that it is weak to stresses such as thermal shock and easily cracked.
- the first solder 12 is embedded in the connecting resin layer 24 as in the above-mentioned configuration, the defect can be avoided, and new advantages can be obtained in that respect as well.
- the first solder 12 constituting the solder-mer force 10 can be other than Sn—Sb-based solder.
- FIG. 12 is a table showing the relationship between conductive particles used as solder and the melting point (solid phase line).
- the first solder 12 constituting the solder mer force 10 and the second and third solders for the first and second electronic components in consideration of the magnitude relationship of the melting point 32 , 42 and should be selected.
- conductive particles other than this table.
- a second solder having a second melting point lower than the first melting point is provided after providing the solder marker 10 formed of the solder 12 having the first melting point.
- the first electronic component 40 is mounted on the top surface 20 a of the circuit board 200 by the reference numeral 42.
- the remelting of the third solder 32 (the connection material of the second electronic component) having a melting point equal to the first melting point is inspected by detecting the solder mer force 10 provided in the circuit board 200. I can do it. Therefore, it becomes possible to detect the presence or absence of re-melting of the third solder 32 of the second electronic component 30 built in the circuit board 200, and the reliability of the circuit board 200 can be inspected with high accuracy. Can.
- solder mer force 10 is provided in the circuit board 200 (or the circuit board 100 not incorporating the electronic component), the variation during the reflow process (reflow) It is possible to check whether the substrate has been exposed to the specified temperature or more due to temperature deviation, etc., by means of the solder mer force 10. Therefore, it is possible to prevent the decrease in product reliability.
- the solder mer force 10 of the present embodiment can be used for other uses which are used only for the re-melting check of the circuit board 200 in which the electronic component is built. For example, in the configurations shown in FIG. 2 to FIG. 5B, an effect is obtained that it can be confirmed whether the reflow temperature is higher than the appropriate temperature. Note that this effect can be obtained similarly even in a circuit board which does not contain an electronic component. This will be further described below.
- the reflow temperature of the reflow process As a cause of degrading the quality of the substrate, there is an abnormal rise in the reflow temperature. In particular, after Pb-free is widely used, the reflow temperature of the reflow process is rising, and therefore, the mounting process of electronic parts is in a severe situation with respect to the substrate. When the reflow temperature is too high, the resin constituting the substrate is deteriorated, and the adhesion strength of the lands is reduced, and the lands and the electrodes are easily peeled off in the inner layer and the outer layer of the substrate.
- the reflow device controls the temperature inside the device due to its structure, but can not control the temperature of the product itself such as the substrate, and in fact the substrate may be exposed to high temperatures due to variations etc. Source is possible. Therefore, it is a very important technique to provide the marker 10 on the substrate and check if reflow is not higher than the appropriate temperature.
- solder mer force 10 of the present embodiment is also possible to configure the solder mer force 10 of the present embodiment as a temperature marker by making use of different types of first solders 12 (having different melting points).
- first solders 12 having different melting points
- FIG. 12B a plurality of types of soldermer forces 10 are produced by the first solder 12 group selected from the conductive particles shown in FIG. It is possible to evaluate the force (for example, the internal temperature of the substrate) of what degree C.
- the solder force 10 of the present embodiment can be modified as follows.
- 13A and 13B are views of the solder mer force 10 as viewed from above.
- the solder mer force 10 shown in FIG. 13A has a configuration in which a marker member made of the unmelted first solder 12 is bridged between electrode patterns 27 having a resist (solder resist) 29 formed on the periphery. Since the first solder 12 has surface tension when it melts, as shown in FIG. 13B, as the first solder 12 melts, the solder mer force 10 is different from the state shown in FIG. 13A before the melting. It becomes a thing. If you observe this change, you can force S to perform a test with solder-mer force 10.
- solder 12 is shaped so as to have corners at the outer peripheral edge in a plan view, the corners are deformed and rounded by surface tension during melting.
- the left side in FIGS. 14A to 14D is a solder mer force 10 composed of the unmelted first solder 12, and their corners are deformed and rounded by melting, respectively, as shown in FIG. 14A to FIG. It can be shaped like the right side in 14D. Therefore, if these changes in shape are observed, it is possible to carry out an examination by the hand hammer force 10.
- the force of forming the solder mer force 10 using the first solder 12 in the form of cream solder is not limited to this.
- FIG. It is also possible to construct 10 from solder balls consisting of the first solder 12.
- an adhesive 28 may be provided to bond the first solder 12 and the electrode 26 shown in FIG. 15A. This is because, when the first solder 12 is carried in the connecting resin layer (composite sheet) 24, the first solder 12 is fixed by the adhesive 28 so as not to move by the flow of the resin. It is. Thus, even when the first solder 12 is fixed by the adhesive 28, when the first solder 12 is melted, the melted first solder 12a and the electrode 26 are metal as shown in FIG. 16B. Since the electrodes 26 are joined together and short-circuited, it is possible to perform a nodmer force detection.
- solder mer force 10 by combining the first solder 12 and a conductive member (typically, a metal member or 0 ⁇ chip resistance) 13. is there .
- a conductive member typically, a metal member or 0 ⁇ chip resistance
- the metal member 13 is mounted on the unmelted first solder 12 (for example, cream solder)
- the first solder 12 is not melted, so the electrodes 26 are electrically open. It becomes.
- the first solder 12 is melted, as shown in FIG.
- the melted first solder 12a and the electrode 26 are metal-bonded, and the melted first solder 12a and the metal member 13 are also Shows the characteristic of the part in a state where the electrodes 26 are shorted since the metal bonding is performed. Due to the difference between the two, it is possible to carry out a solder-mer test.
- the force at which the solder mer force 10 is mounted in the substrate may or may not be necessary.
- the electronic component is embedded using a sheet (for example, a composite sheet for multi-cavity) 110 for taking a large number of modules (circuit board 200 having an electronic component etc.).
- the solder marker 10 can be provided at a location (outer frame 150) other than the area where the circuit board 200 incorporating the electronic component is located. If solder force 10 is provided at such a place, solder force detection can be performed without wasting the substrate and the area is very efficient.
- Circuit board 200 (the component built-in module 300, mounting which incorporates the electronic components as described above
- the body 350 is preferably mounted on an electronic device.
- portable electronic devices for example, mobile phones, PDAs, etc.
- electronic devices such as so-called digital home appliances (digital television etc.).
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Abstract
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Priority Applications (2)
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JP2008508652A JPWO2007114334A1 (ja) | 2006-03-31 | 2007-03-30 | 回路基板、回路基板の検査方法、およびその製造方法 |
US12/295,478 US20090202142A1 (en) | 2006-03-31 | 2007-03-30 | Circuit board, method for testing circuit board, and method for manufacturing circuit board |
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JP2006-098810 | 2006-03-31 | ||
JP2006098810 | 2006-03-31 |
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WO2007114334A1 true WO2007114334A1 (ja) | 2007-10-11 |
Family
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Family Applications (1)
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PCT/JP2007/057094 WO2007114334A1 (ja) | 2006-03-31 | 2007-03-30 | 回路基板、回路基板の検査方法、およびその製造方法 |
Country Status (4)
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US (1) | US20090202142A1 (ja) |
JP (1) | JPWO2007114334A1 (ja) |
CN (1) | CN101411252A (ja) |
WO (1) | WO2007114334A1 (ja) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011249457A (ja) * | 2010-05-25 | 2011-12-08 | Dainippon Printing Co Ltd | 部品内蔵配線板、部品内蔵配線板の製造方法 |
KR20130046378A (ko) * | 2011-10-27 | 2013-05-07 | 노드슨 코포레이션 | 촬영 시스템을 사용하여 관심 영역의 3차원 모델을 생성하기 위한 방법 및 장치 |
JP2014146842A (ja) * | 2014-05-02 | 2014-08-14 | Dainippon Printing Co Ltd | 部品内蔵配線板の製造方法 |
WO2019194071A1 (ja) * | 2018-04-02 | 2019-10-10 | 三菱電機株式会社 | はんだ噴流検査装置、実装基板及びはんだ噴流検査方法 |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
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JP5223876B2 (ja) * | 2010-03-12 | 2013-06-26 | オムロン株式会社 | X線検査装置、x線検査方法、x線検査プログラムおよびx線検査システム |
CN101799428B (zh) * | 2010-04-09 | 2012-06-06 | 深圳信息职业技术学院 | 球栅阵列焊点重熔测试方法 |
KR101675138B1 (ko) * | 2015-02-04 | 2016-11-10 | 현대모비스 주식회사 | 전력반도체 모듈 및 이의 제조방법 |
CN105425094B (zh) * | 2015-11-24 | 2018-04-27 | 深圳怡化电脑股份有限公司 | 一种pcba短路点检测方法及装置 |
CN111230350A (zh) * | 2018-11-28 | 2020-06-05 | 长鑫存储技术有限公司 | 芯片可焊性的测试方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10326959A (ja) * | 1997-05-26 | 1998-12-08 | Sony Corp | プリント配線板及び該プリント配線板によるはんだの濡れ性評価方法 |
JPH11220262A (ja) * | 1997-11-25 | 1999-08-10 | Matsushita Electric Ind Co Ltd | 回路部品内蔵モジュールおよびその製造方法 |
JP2004172464A (ja) * | 2002-11-21 | 2004-06-17 | Fujitsu Ltd | 半田付け検査の特徴量算出装置 |
JP2004245751A (ja) * | 2003-02-14 | 2004-09-02 | Canon Electronics Inc | 回路基板 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6038133A (en) * | 1997-11-25 | 2000-03-14 | Matsushita Electric Industrial Co., Ltd. | Circuit component built-in module and method for producing the same |
JP4731021B2 (ja) * | 2001-01-25 | 2011-07-20 | ローム株式会社 | 半導体装置の製造方法および半導体装置 |
US20030116860A1 (en) * | 2001-12-21 | 2003-06-26 | Biju Chandran | Semiconductor package with low resistance package-to-die interconnect scheme for reduced die stresses |
CN100446205C (zh) * | 2004-03-29 | 2008-12-24 | 日本电气株式会社 | 半导体装置和其制造方法 |
US20060186172A1 (en) * | 2005-02-18 | 2006-08-24 | Illinois Tool Works, Inc. | Lead free desoldering braid |
-
2007
- 2007-03-30 US US12/295,478 patent/US20090202142A1/en not_active Abandoned
- 2007-03-30 WO PCT/JP2007/057094 patent/WO2007114334A1/ja active Application Filing
- 2007-03-30 CN CNA2007800111572A patent/CN101411252A/zh active Pending
- 2007-03-30 JP JP2008508652A patent/JPWO2007114334A1/ja active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10326959A (ja) * | 1997-05-26 | 1998-12-08 | Sony Corp | プリント配線板及び該プリント配線板によるはんだの濡れ性評価方法 |
JPH11220262A (ja) * | 1997-11-25 | 1999-08-10 | Matsushita Electric Ind Co Ltd | 回路部品内蔵モジュールおよびその製造方法 |
JP2004172464A (ja) * | 2002-11-21 | 2004-06-17 | Fujitsu Ltd | 半田付け検査の特徴量算出装置 |
JP2004245751A (ja) * | 2003-02-14 | 2004-09-02 | Canon Electronics Inc | 回路基板 |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011249457A (ja) * | 2010-05-25 | 2011-12-08 | Dainippon Printing Co Ltd | 部品内蔵配線板、部品内蔵配線板の製造方法 |
KR20130046378A (ko) * | 2011-10-27 | 2013-05-07 | 노드슨 코포레이션 | 촬영 시스템을 사용하여 관심 영역의 3차원 모델을 생성하기 위한 방법 및 장치 |
KR102052873B1 (ko) * | 2011-10-27 | 2020-01-22 | 노드슨 코포레이션 | 촬영 시스템을 사용하여 관심 영역의 3차원 모델을 생성하기 위한 방법 및 장치 |
JP2014146842A (ja) * | 2014-05-02 | 2014-08-14 | Dainippon Printing Co Ltd | 部品内蔵配線板の製造方法 |
WO2019194071A1 (ja) * | 2018-04-02 | 2019-10-10 | 三菱電機株式会社 | はんだ噴流検査装置、実装基板及びはんだ噴流検査方法 |
Also Published As
Publication number | Publication date |
---|---|
JPWO2007114334A1 (ja) | 2009-08-20 |
CN101411252A (zh) | 2009-04-15 |
US20090202142A1 (en) | 2009-08-13 |
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