WO2007110940A1 - Dispositif a semiconducteurs et processus de fabrication de celui-ci - Google Patents

Dispositif a semiconducteurs et processus de fabrication de celui-ci Download PDF

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Publication number
WO2007110940A1
WO2007110940A1 PCT/JP2006/306424 JP2006306424W WO2007110940A1 WO 2007110940 A1 WO2007110940 A1 WO 2007110940A1 JP 2006306424 W JP2006306424 W JP 2006306424W WO 2007110940 A1 WO2007110940 A1 WO 2007110940A1
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Prior art keywords
metal
layer
gate electrode
metal gate
insulating layer
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PCT/JP2006/306424
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English (en)
Japanese (ja)
Inventor
Akito Hara
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Fujitsu Limited
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Priority to JP2008507325A priority Critical patent/JP4755245B2/ja
Priority to PCT/JP2006/306424 priority patent/WO2007110940A1/fr
Publication of WO2007110940A1 publication Critical patent/WO2007110940A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes

Definitions

  • the present invention relates to a semiconductor device having a MISFET (Metal Insulator Semiconductor Field Effect Transistor) and a manufacturing method thereof, and more particularly to a semiconductor device having a MISFET having a multi-gate structure and a manufacturing method thereof.
  • MISFET Metal Insulator Semiconductor Field Effect Transistor
  • MISFETs having a gate electrode and source / drain regions are expected to improve the performance of MISFETs as the distance between the source and the drain decreases as the width of the gate electrode is reduced.
  • MISFET performance for example, on-current, does not improve by reducing the width of the gate electrode.
  • the MISFET on-resistance is composed of the source and drain resistance and the resistance between the source and drain when the channel region directly under the gate electrode is turned on. This is because the on-resistance of the entire MISFET does not decrease.
  • the other reason why the on-current is not improved is that polycrystalline silicon is also a semiconductor, and therefore a depletion layer is generated on the polycrystalline silicon side at the interface between the polycrystalline silicon constituting the electrode and the gate insulating film.
  • Patent Document 1 discloses a MISFET having a so-called multi-gate electrode structure in which a gate electrode is disposed so as to sandwich a channel region having a rectangular cross section from two opposing directions.
  • a MISFET having a structure in which source and drain electrodes are arranged in two opposite directions is disclosed. Therefore, a two-direction force electric field is generated in the channel region by the gate electrode made of polycrystalline silicon arranged in two directions. Then, the leakage current between the source and drain is prevented by the electric field from two directions.
  • the source and drain electrode forces are placed in direct contact with the channel region from the other two opposing directions, with no distance. Then, the structure has almost no source / drain resistance.
  • Patent Document 1 Japanese Patent Laid-Open No. 2001-284598
  • the gate electrode is made of polycrystalline silicon. If the electric field generated in the channel region is reduced by the depletion layer generated on the polycrystalline silicon side, the phenomenon cannot be suppressed. .
  • the heat treatment is as low as about 500 ° C.
  • the crystallinity is very poor, and a leakage current is generated between the source and drain due to the current transmitted through the silicon grain boundary. It is an object of the present invention to provide a MISFET having a metal gate electrode and a multi-gate electrode structure in which a leakage current between a source and a drain is reduced, and a method for manufacturing the MISF ET.
  • the MISFET according to the present invention includes a first metal gate electrode, a second metal gate electrode disposed in parallel with the extending direction of the first metal gate electrode and in parallel with the first metal gate electrode, A first semiconductor layer sandwiched between a first metal gate electrode and the second metal gate electrode via a gate insulating film; adjacent to both sides of the first semiconductor layer; and A second semiconductor layer adjacent to both sides of the first metal gate electrode and the second metal gate electrode, wherein a source is formed on one side and a drain is formed on the other side.
  • One semiconductor layer has needle-like crystal grains perpendicular to the extending direction of the first metal gate electrode and the second metal gate electrode.
  • the present invention provides a method for manufacturing the following MISFET.
  • Method of manufacturing MISFET A second metal in the same direction and parallel to the extending direction of the first metal gate electrode so that a cavity is formed between the first metal gate electrode and the first metal gate.
  • the present invention can provide a MISFET having a metal gate electrode, a multi-gate electrode structure, and a structure in which a leakage current between a source and a drain is reduced, and a method for manufacturing the MISFET.
  • FIG. 1 is a plan view of a MISFET of Example 1.
  • FIG. 2A and FIG. 2B are cross-sectional views showing a cross section taken along the line AB of FIG. 1 and a cross section taken along the line CD.
  • FIG. 3A to FIG. 3F are cross-sectional views showing a part of the process for manufacturing the MISFET 1 of the first embodiment.
  • FIG. 4A to 4F are cross-sectional views showing a part of the process for manufacturing the MISFET 1 of Example 1.
  • FIG. 4A to 4F are cross-sectional views showing a part of the process for manufacturing the MISFET 1 of Example 1.
  • FIG. 5A to FIG. 5F are cross-sectional views showing a part of the process for manufacturing the MISFET 1 of the first embodiment.
  • FIG. 6A to 6F are cross-sectional views showing a part of a process for manufacturing the MISFET 1 of Example 1.
  • FIG. 6A to 6F are cross-sectional views showing a part of a process for manufacturing the MISFET 1 of Example 1.
  • FIG. 7A to FIG. 7F are cross-sectional views showing a part of the process for manufacturing the MISFET 1 of the first embodiment.
  • FIG. 8A to FIG. 8F are cross-sectional views showing a part of the steps constituting the manufacturing method of the MISFET 1 of Example 3.
  • FIG. 9A to FIG. 9F are cross-sectional views showing a part of the steps constituting the manufacturing method of the MISFET 1 of Example 3.
  • FIG. 10A and FIG. 10B are cross-sectional views showing a part of the steps constituting the manufacturing method of the MISFET 1 of Example 3.
  • Example 1 Example 1, Example 2, and Example 3 of the present invention will be described. [0012] (Example 1)
  • Example 1 relates to a MIS FET which is a metal gate electrode and has a multi-gate electrode structure. Example 1 will be described with reference to FIGS. 1, 2A, and 2B.
  • FIG. 1 is a plan view of the MISFET according to the first embodiment. 1 shows a field region 2 that defines MISFET 1, an upper metal gate electrode 3, a lower metal gate electrode 4, needle-like crystal grains 5, a channel region 6 of MISFET 1, a region 7 into which metal impurities are introduced, An insulating layer 8 for element isolation, a source / drain region 12 of the MISFET, and a contact window 15 connected to the source / drain region 12 are shown.
  • the field region 2 that defines the MISFET 1 is surrounded by an insulating layer 8 for element isolation.
  • the field region 2 is, for example, a rectangle having a horizontal width of 3 to 10 ⁇ m and a vertical width of 4 to 5 ⁇ m.
  • the vertical direction is the direction connecting the source and drain of the MISFET
  • the horizontal direction is the direction perpendicular to the direction connecting the source and drain of the MISFET.
  • the channel region 6 of the MISFET 1 is located at the center of the field region 2 that defines the MISFET 1.
  • the channel region 2 is, for example, a rectangle having a channel width of 2 to 3 ⁇ m and a channel length of 5 Onm.
  • the channel length is the length of the channel region 2 in the direction connecting the source and drain of the MISFET
  • the channel width is the channel region 2 in the direction perpendicular to the direction connecting the source and drain of the MISFET. Length!
  • the lower metal gate electrode 4 is a metal gate electrode disposed under the channel region 6.
  • the lower metal gate electrode 4 extends in the field region 2 in a direction perpendicular to the direction connecting the source and drain of the MISFET. Therefore, the lower metal gate electrode 4 has a rectangular shape.
  • the width is 50 nm as in the channel length, and the length is 4 to 5 ⁇ m as in the vertical width of the field region 2.
  • the upper metal gate electrode 3 is a metal gate electrode disposed above the channel region 6.
  • the upper metal gate electrode 3 extends in a direction perpendicular to the direction connecting the source and drain of the MISFET. That is, the upper metal gate electrode 3 is arranged in parallel with the lower metal gate electrode 4 in the same direction as the direction in which the lower metal gate electrode 4 extends.
  • the upper metal gate electrode 3 and the lower metal gate electrode 4 Are placed across the channel region 6. Therefore, the width of the upper metal gate electrode is, for example, 50 nm, similar to the channel length.
  • the source / drain region 12 is disposed adjacent to both sides of the upper metal gate electrode 3 and the lower metal gate electrode 4. Therefore, the source / drain region 12 is also adjacent to both sides of the channel region 6.
  • the region 7 into which the metal impurity has been introduced is disposed in the source / drain region 12 and is a rectangular region.
  • the upper metal gate electrode is arranged on both sides of the channel region 6.
  • the needle-like crystal grains 5 exist in the source / drain region 12 and the channel region 6 and between the regions 7 into which metal impurities are introduced. And the longitudinal direction of the acicular crystal grains 5 is
  • the contact window 15 is an opening for connecting a wiring to the source / drain region 12.
  • 2A and 2B are cross-sectional views showing a cross section taken along the line AB of FIG. 1 and a cross section taken along the line CD.
  • 2A and 2B show a field region 2 that defines the MISFET 1, an upper metal gate electrode 3, a lower metal gate electrode 4, and needle-like crystal grains 5.
  • FIG. 2A is a cross-sectional view taken along a dotted line AB in FIG.
  • the MISFET 1 is formed on the substrate 13.
  • the field region 2 of the MISFET 1 is surrounded by an insulating layer 8 for element isolation.
  • the channel region 6 is arranged in the center of the field region 2.
  • the channel region 6 includes a gate insulating film 10 between the upper metal gate electrode 3 and the channel region 6 and a lower metal gate electrode 4 by an upper metal gate electrode 3 and a lower metal gate electrode 4. It is sandwiched between the channel region 6 via the gate insulating film 11.
  • the channel region 6 is perpendicular to the direction connecting the source and drain of the MISFET.
  • the upper metal electrode 3 or the lower metal electrode 4 is sandwiched between the left and right sides.
  • the channel region 6 is surrounded by the upper metal gate electrode 3 and the lower metal gate electrode 4 in the cross section along the dotted line AB in FIG.
  • the structure surrounded by the upper metal gate electrode 3 and the lower metal gate electrode 4 in the channel region 6 force is called a gate all around structure.
  • the channel region 6 is filled with a bundle of needle-like crystal grains 5 extending in the direction connecting the source and drain of the MISFET.
  • the lower metal gate electrode 4 is deposited on the substrate 13.
  • An interlayer insulating layer 9 is deposited on the upper metal gate electrode 3.
  • FIG. 2B is a cross-sectional view taken along the line CD in FIG.
  • the field region 2 of the MISFET 1 is surrounded by an insulating layer 8 for element isolation.
  • the channel region 6, the lower metal gate electrode 4, and the upper metal gate electrode 3 are arranged in the center of the field region 2.
  • a polycrystalline silicon region 18 and a lower metal gate electrode 4 are formed on the substrate 13.
  • the polycrystalline silicon region 18 is a region constituted by polycrystalline silicon in the field region 2. That is, the polycrystalline silicon region 18 is a region up to the bottom force substrate of the channel region 6, the source 'drain region 12, and the source' drain region 12, and the lower metal gate electrode 4 and the upper metal region. A region force is arranged on both sides of the gate electrode 3.
  • the source / drain region 12 is a semiconductor region adjacent to both sides of the channel region 6, and is a region composed of polycrystalline silicon into which impurities are introduced. Accordingly, the source / drain region 12 is adjacent to both sides of the upper metal gate electrode 3 and the lower metal gate electrode 4.
  • the above-mentioned impurities are N-type impurities when MISFET 1 is N-type, and P-type impurities when MISFET 1 is P-type.
  • the region 7 into which the metal impurity has been introduced is a region formed on the surface of the source / drain region 12, and is a region arranged so as to extend in parallel to both sides of the channel region 6. . That is, the upper metal gate electrode 3 extends in the region 7 into which the metal impurity is introduced. And extending in parallel to both sides of the upper metal gate electrode. In the region 7 into which the metal impurity is introduced, a metal that causes a metal-induced solid phase growth phenomenon is introduced.
  • the metal-induced solid phase growth phenomenon is formed by doping a metal impurity into an amorphous semiconductor (amorphous semiconductor) when heat treatment is applied to the amorphous semiconductor (amorphous semiconductor).
  • a metal impurity is a phenomenon in which a semiconductor crystal grows with a compound of a metal and a semiconductor as a nucleus.
  • a poly semiconductor layer with good crystallinity can be formed in a short time at a low temperature of less than 600 ° C.
  • the semiconductor is silicon (Si), nickel (Ni), copper (Cu), gold (Au), platinum (Pt), etc. are known as metal impurities that cause the above-described induced solid phase growth phenomenon. ing.
  • the semiconductor is germanium (Ge), gold (Au) or the like is known as a metal impurity that causes an induced solid phase growth phenomenon.
  • gold (Au) or the like is known as a metal impurity that causes an induced solid phase growth phenomenon.
  • silicon germanium (SiGe) gold (Au) or the like is known as a metal impurity that causes an induced solid phase growth phenomenon.
  • silicon germanium (SiGe) or the like is known as a metal impurity that causes an induced solid phase growth phenomenon.
  • the metal introduced into the region 7 into which the metal impurity has been introduced diffuses into the amorphous silicon and grows a silicon crystal.
  • a polycrystalline silicon region 18 made of polycrystalline silicon is formed.
  • the heat treatment for growing polycrystalline silicon is less than 600 ° C. Therefore, the lower metal gate electrode 4 is not affected by the heat treatment and is maintained.
  • the region 7 into which the metal impurities are introduced extends in parallel to both sides of the channel region 6! /, And connects the source and drain of the MISFET. Metal impurities diffuse in the direction. Therefore, acicular crystal grains 5 grow in the channel region 6, and the channel region 6 is constituted by the acicular crystal grains 5.
  • the contact window 15 is a window for connecting a metal wiring to the source / drain region 12. Therefore, a resist pattern having an opening corresponding to the contact window 15 is formed on the interlayer insulating layer 9 by a photolithography method, and the interlayer insulating layer 9 is etched using the resist pattern as a mask.
  • the gate insulating film 10 and the gate insulating film 11 are formed on the upper metal gate electrode 3 and the lower gate metal electrode 4. Since the channel region 6 sandwiched between them is composed of the needle-like crystal grains 5, the leakage current between the source and the drain is reduced. This is because the carrier carrying the current flowing between the source and the drain flows through the needle-like crystal grains 5 having good crystallinity. The depletion layer generated by the electric field from the upper metal gate electrode 3 and the lower gate metal electrode 4 dominates the current path in the needle-like crystal grains 5. As a result, the carrier responsible for the current flowing between the source and drain is the force that is completely cut off when the MISFET is off. When a plurality of crystal grains exist between the source and the drain, the carrier carrying the current flowing between the source and the drain is transmitted through the grain boundary of the crystal grains and leaks. As a result, a leak current is generated between the source and the drain.
  • a MISFET having a metal gate electrode, a multi-gate electrode structure, and a structure in which a leakage current between a source and a drain is reduced.
  • Example 2 relates to a method of manufacturing a MIS FET that is a metal gate electrode and has a multi-gate electrode structure.
  • Example 2 will be described with reference to FIGS. 3A to 3F, FIGS. 4A to 4F, FIGS. 5A to 5B, FIGS. 6A to 6F, and FIGS. 7A to 7D.
  • 3A to 3F are cross-sectional views showing a part of the process for manufacturing the MISFET 1 of the first embodiment.
  • 3A, 3B, and 3C are cross-sectional views taken along the line C-D in FIG. 3D
  • FIG. 3E, and FIG. 3F show cross-sectional views along the dotted line AB in FIG. 3A to 3F show the substrate 13, the insulating layer 8 for element isolation, the metal layer for the lower metal gate electrode 4, the channel region 6, the amorphous silicon layer (amorphous silicon layer) 19, and the protective film.
  • 20 shows a protective film 21 and a sidewall film 23.
  • FIGS. 3A and 3D are diagrams showing the following steps.
  • an insulating layer 8 for element isolation is deposited on the substrate 13 by the CVD method, and a resist pattern having an opening corresponding to the field region 2 is formed on the insulating layer 8 for element isolation by the photolithography method.
  • the insulating layer 8 for element isolation is etched until the surface of the substrate 13 appears, and the resist pattern is removed.
  • a metal layer for forming the lower metal gate electrode 4 is deposited on the substrate 13 by a notching method or a CVD method.
  • the metal constituting the metal layer is preferably a refractory metal such as tantasten (W) or molybdenum (Mo).
  • the protective film 20 is deposited by PECVD (plasma enhanced chemical vapor deposition), LPCVD (low pressure chemical vapor deposition), ALD (atomic layer deposition), or sputtering.
  • the protective film 20 may be made of an oxide silicon (SiO 2) film, an oxide silicon nitride (SiO 2)
  • N nitride film (SiN) film, high dielectric film (high-k material) may be used.
  • FIG. 3B and FIG. 3E are diagrams showing the following steps. First, after the steps shown in FIGS. 3A and 3D are completed, an amorphous silicon layer (amorphous silicon layer) 19 is deposited by a plasma CVD method. Thereafter, the protective film 21 is deposited by the CVD method. Then, a resist is applied on the protective film 21, and a resist pattern is formed so that the resist remains in a region corresponding to the channel region 6 by a photolithography method.
  • the protective film 21 By performing anisotropic etching on the protective film 21, the amorphous silicon layer (amorphous silicon layer) 19, and the protective film 20 on the resist pattern mask, the protective film 21, amorphous silicon The layer (amorphous silicon layer) 19 and the protective film 20 are patterned. As a result, the cross-sectional shape shown in the cross-sectional views of FIGS. 3B and 3E is obtained.
  • the method of depositing the protective film 21 it is also possible to use the PECVD method or the like as with the protective film 20. Needless to say, the material of the protective film 21 may be a nitride film (SiN) or the like, similar to the protective film 20.
  • FIG. 3C and FIG. 3F are views showing the following steps. After completing the steps shown in FIGS. 3B and 3E, a protective film is deposited by CVD. Thereafter, the sidewall film 23 is formed on the side surface of the patterned amorphous silicon layer (amorphous silicon layer) 19 by performing anisotropic etching on the protective film. As a result, the cross-sectional shape shown in the cross-sectional views of FIGS. 3C and 3F is obtained.
  • the protective film includes an oxide silicon (SiO 2) film, an oxide silicon nitride (SiON) film, and a nitride film (S
  • FIGS. 4A to 4F are diagrams showing a process for manufacturing the MISFET 1 of the first embodiment, following FIG. It is sectional drawing which shows a part.
  • 4A, 4B, and 4C are cross-sectional views taken along the line C-D in FIG. 4D, 4E, and 4F show cross-sectional views along the dotted line AB in FIG. 4A to 4F show the substrate 13, the isolation layer 8 for element isolation, the metal layer for the lower metal gate electrode 4, the metal layer for the upper metal gate electrode 3, the channel region 6, the amorphous region.
  • a silicon layer (amorphous silicon layer) 19, a protective film 20, a protective film 21, and a side wall film 23 are shown.
  • FIG. 4A and FIG. 4D are diagrams showing the following steps. After completing the steps of FIG. 3C and FIG. 3F, a metal layer for the upper metal gate electrode 3 is deposited by sputtering or CVD. As a result, a cross-sectional shape as shown in FIGS. 4A and 4D is obtained.
  • the metal of the metal layer is preferably a refractory metal such as tandasten (W), as is the metal of the metal layer for the lower metal gate electrode 4.
  • FIG. 4B and FIG. 4E are diagrams showing the following steps. 4A and 4D is completed, a resist is applied on the metal layer of the upper metal gate electrode 3, and a resist pattern corresponding to the gate electrode is formed by a photolithography method. Then, using the above resist pattern as a mask, the upper metal layer for metal gate electrode 3, gate insulating film 10, amorphous silicon layer (amorphous silicon layer) 19, gate insulating film by anisotropic etching 11. Etch the metal layer for the lower metal gate electrode 4. Then, as a result of removing the resist pattern, the cross-sectional shapes of FIGS. 4B and 4E are obtained.
  • FIG. 4C and FIG. 4F are views showing the following steps. After the process of FIGS. 4B and 4E is completed, the amorphous silicon layer (amorphous silicon layer) 19 existing in the channel region 6 is etched and removed by an isotropic etching method. As a result, the portion corresponding to the channel region 6 becomes a cavity, and the cross-sectional shapes as shown in FIGS. 4C and 4F are obtained.
  • the amorphous silicon layer (amorphous silicon layer) 19 existing in the channel region 6 is etched and removed by an isotropic etching method. As a result, the portion corresponding to the channel region 6 becomes a cavity, and the cross-sectional shapes as shown in FIGS. 4C and 4F are obtained.
  • FIGS. 5A to 5F are cross-sectional views illustrating a part of the process for manufacturing the MISFET 1 of Example 1 following FIG. 5A, FIG. 5B, and FIG. 5C show cross-sectional views along the line CD in FIG. 5D, 5E, and 5F are cross-sectional views taken along the dotted line AB in FIG. 5A to 5F show a substrate 13, a field region 2, a region 7 into which a metal impurity is introduced, an insulating layer 8 for element isolation, a metal layer for a lower metal gate electrode 4, and an upper metal gate electrode.
  • Metal layer for 3, channel region 6, gate insulating film 10, gate An insulating film 11, an amorphous silicon layer (amorphous silicon layer) 19, an amorphous silicon layer (amorphous silicon layer) 22, and a sidewall film 23 are shown.
  • FIG. 5A and FIG. 5D are diagrams showing the following steps. After the process of FIGS. 4C and 4F is completed, the protective film 20 and the protective film 21 are removed by an isotropic dry etching method. After that, an oxide silicon (SiO 2) film is formed on the upper metal gate electrode by PECVD.
  • SiO 2 oxide silicon
  • FIG. 5B and FIG. 5E are diagrams showing the following steps.
  • the amorphous silicon (amorphous silicon) 22 is applied to the channel region 6 in the field region 2 by using a PECVD method in which a directionality is applied by applying a bias. A film is formed so as to fill the cavity.
  • the amorphous silicon layer (amorphous silicon layer) 22 is placed in the field region 2 surrounded by the insulating layer 8 for element isolation, on the insulating layer 8 for element isolation, and on the upper side.
  • the metal gate electrode 3 is deposited so as to have the same height.
  • the amorphous silicon layer (amorphous silicon layer) 22 does not adhere to the vertical wall surface in the stepped portion. Accordingly, the amorphous silicon layer (amorphous silicon layer) 22 in the field region 2 is formed on the amorphous silicon layer (amorphous silicon layer) 22 on the insulating layer 8 for element isolation and the upper metal gate electrode 3.
  • the amorphous silicon layer (amorphous silicon layer) 22 can be in an isolated state. Thereafter, as a result of introducing impurities to be introduced into the source / drain regions 12 by ion implantation or solid phase diffusion, the cross-sectional shapes shown in FIGS. 5B and 5E are obtained.
  • the channel region 6 and the source / drain region 12 are formed in a self-aligned manner.
  • the timing of ion implantation of the impurity introduced into the source / drain region 12 is not limited to the timing of FIGS. 5B and 5E.
  • the stage shown in FIG. That is, it may be after the polycrystalline silicon 18 is formed from the amorphous silicon layer (amorphous silicon layer) 22 in the field region 2.
  • the temperature at which the above impurities are activated is preferably less than 600 ° C.
  • FIG. 5C and FIG. 5F are diagrams showing the following steps. After the steps of FIG. 5B and FIG. 5E are completed, a resist is applied, and a resist pattern in which a portion corresponding to the region 7 into which the metal impurity has been introduced is opened is formed by a photolithography method. As a result, the cross-sectional shape shown in FIGS. 5C and 5F is obtained.
  • FIG. 6A to 6F are cross-sectional views illustrating a part of the process for manufacturing the MISFET 1 of the first embodiment, following FIG. 6A, 6B, and 6C are cross-sectional views taken along the line CD in FIG. 6D, 6E, and 6F show cross-sectional views along the dotted line AB in FIG. 6A to 6F show a field region 2, an upper metal gate electrode 3, a lower metal gate electrode 4, needle-like crystal grains 5, a channel region 6, a region 7 into which metal impurities are introduced, and an element isolation Insulating layer 8, gate insulating film 10, gate insulating film 11, substrate 13, nickel (Ni) ion implantation 17, polycrystalline silicon region 18, amorphous silicon layer (amorphous silicon layer) 22, and sidewall film 23 Indicates.
  • FIG. 6A, 6B, and 6C are cross-sectional views taken along the line CD in FIG. 6D, 6E, and 6F show cross-sectional views along the dotted line AB in FIG. 6A to 6F show a field
  • FIGS. 6A and 6D show nickel (Ni) ion implantation after the steps of FIGS. 5C and 5F are completed.
  • FIG. 17 is a view showing a state where nickel (Ni) is introduced as a metal impurity into the region 7 into which the metal impurity has been introduced by performing 17.
  • Layer) 22 is not introduced with nickel (Ni).
  • FIG. 6B and FIG. 6E are diagrams showing the following steps. After completing the steps of FIG. 6A and FIG. 6D, the resist pattern is removed and heat treatment is performed at a temperature of about 450 ° C. to about 600 ° C. As a result, needle-like crystal grains 5 grow in the channel region 6. Thus, the cross-sectional shape shown in FIGS. 6B and 6E can be obtained.
  • the upper limit of the heat treatment temperature is about 600 ° C. because the lower metal gate electrode 4 and the upper metal gate electrode 3 do not melt and the temperature is desired U. Therefore, it goes without saying that the upper limit of the heat treatment temperature can be raised depending on the metal constituting the metal gate electrode.
  • the lower limit of the heat treatment temperature is set to about 450 ° C because the temperature at which the metal-induced solid phase growth phenomenon starts. Therefore, the temperature of the above heat treatment should be between 500 ° C and 550 ° C! /.
  • FIGS. 6C and 6F show a case where the heat treatment of FIGS.
  • amorphous silicon layer (amorphous silicon layer) 22 in the field region 2 is converted into a polycrystalline silicon region by a metal-induced solid phase growth phenomenon. It is a figure which shows the place which became 18.
  • FIG. The impurities introduced into the source / drain regions 12 are taken into the silicon crystal lattice and activated by the metal-induced solid phase growth phenomenon.
  • amorphous silicon layer (amorphous silicon layer) 22 on the upper metal gate electrode 3 does not contain nickel (Ni), metal-induced solid-phase growth does not occur, and the polycrystalline silicon region 18 It remains.
  • FIG. 7A to 7F are cross-sectional views illustrating a part of the process for manufacturing the MISFET 1 of Example 1 following FIG. 7A and 7B are cross-sectional views taken along the line CD in FIG. 7C and 7D show cross-sectional views along the dotted line AB in FIG.
  • FIG. 7A to 7D show a field region 2, an upper metal gate electrode 3, a lower metal gate electrode 4, needle-like crystal grains 5, a channel region 6, a region 7 into which metal impurities are introduced, and an element isolation Insulating layer 8, interlayer insulating layer 9, gate insulating film 10, gate insulating film 11, source 'drain region 12, substrate 13, contact window 15, nickel (Ni) ion implantation 17, polycrystalline silicon region 18, An amorphous silicon layer (amorphous silicon layer) 22 and a sidewall film 23 are shown.
  • FIGS. 6C and 6F are diagrams showing a state where the amorphous silicon layer (amorphous silicon layer) 22 is removed by isotropic etching after the steps of FIGS. 6C and 6F are completed. . That is, since there is a difference in etching rate between polycrystalline silicon and amorphous silicon, only the amorphous silicon layer (amorphous silicon layer) 22 can be removed.
  • FIG. 7B and FIG. 7D are diagrams showing the following steps. After the process of FIGS. 7A and 7D is completed, an interlayer insulating layer 9 is deposited by the CVD method. Thereafter, a resist is applied on the interlayer insulating layer 9, and a resist pattern having an opening corresponding to the contact window 15 is formed by a photolithography method. Then, anisotropic etching is performed using the resist pattern as a mask to form a contact window 15 penetrating the interlayer insulating layer 9. As a result, a cross-sectional shape as shown in FIGS. 7B and 7E is shown.
  • the heat treatment temperature is suppressed to a low temperature of less than 600 ° C. in the process performed after the formation of the lower metal gate electrode 4 related to the MISFET manufacturing method of Example 2. Therefore, the metal constituting the lower metal gate electrode 4 and the upper metal gate electrode 3 does not melt.
  • the lower metal gate electrode 4 and the channel region 6 and the source / drain region 12 are arranged in a self-aligned manner, the MISFET of the second embodiment that does not require an alignment margin can be reduced in size.
  • the channel region 6 is composed of a bundle of acicular crystal grains 5, the crystallinity of the channel region 6 is improved, so that the leakage current between the source and the drain can be suppressed.
  • Example 3 is a modification of the manufacturing method of the MISFET of Example 2.
  • the present invention relates to a manufacturing method capable of forming the upper gate electrode in a self-aligned manner with respect to the lower gate electrode and the channel region.
  • Example 2 will be described with reference to FIGS. 8A to 8F, FIGS. 9A to 9F, and FIGS. 10A to 1OD.
  • FIG. 8A to FIG. 8F are cross-sectional views showing a part of the steps constituting the manufacturing method of the MISFET 1 of the third embodiment.
  • 8A, 8B, and 8C are cross-sectional views taken along the line CD in FIG. 8D, FIG. 8E, and FIG. 8F show cross-sectional views along the dotted line AB in FIG. 8A to 8F show the substrate 13, the insulating layer 8 for element isolation, the metal layer for the lower metal gate electrode 4, the channel region 6, the resist pattern 17, and the amorphous silicon layer (amorphous silicon layer).
  • 19 shows a protective film 20, a protective film 21, and illumination light 26.
  • FIG. 8A and FIG. 8D are diagrams showing the following steps. First, an insulating layer 8 for element isolation is deposited on a transparent substrate 13 by a CVD method, and a resist pattern having an opening corresponding to the field region 2 is formed on the insulating layer 8 for element isolation by a photolithography method. Form. The insulating layer 8 for element isolation is etched until the surface of the substrate 13 appears, and the resist pattern is removed.
  • a metal layer for forming the lower metal gate electrode 4 is deposited on the substrate 13 by a notching method or a CVD method.
  • the metal constituting the metal layer is preferably a refractory metal such as tantasten (W) or molybdenum (Mo).
  • a refractory metal such as tantasten (W) or molybdenum (Mo).
  • W tantasten
  • Mo molybdenum
  • the protective film 20 By depositing an insulating layer, which will be the protective film 20, on the metal layer by CVD, it is shown in the cross-sectional views of Figs. 8A and 8D. Get the cross-sectional shape.
  • a PECVD method, an LPCVD method, an ALD method, or a sputtering method may be used.
  • the protective film 20 is made of an oxide silicon (SiO 2) film, an silicon oxide silicon nitride (SiON) film, a nitride film (SiN) film,
  • It may be a dielectric film (high-k material).
  • FIG. 8B and FIG. 8E are diagrams showing the following steps.
  • an amorphous silicon layer (amorphous silicon layer) 19 and a protective film 21 are sequentially deposited by a plasma CVD method.
  • a resist is applied on the protective film 21, and a resist pattern is formed so that the resist remains in a region corresponding to the channel region 6 by a photolithography method.
  • anisotropic etching on the protective film 21 and the amorphous silicon layer (amorphous silicon layer) 19 on the resist pattern mask, the amorphous silicon layer (amorphous silicon layer) 19 and the protective film 21 Putting on.
  • the insulating layer is volumed and anisotropic etching is performed to form sidewalls on the side walls of the patterned amorphous silicon layer (amorphous silicon layer) 19 and the protective film 21.
  • the cross-sectional shapes shown in the cross-sectional views of FIGS. 8B and 8E are obtained.
  • the method for depositing the protective film 21 it is also possible to use a PECVD method or the like as with the protective film 20.
  • the material of the protective film 21 may be a nitride film (SiN) or the like, similar to the protective film 20.
  • FIG. 8C and FIG. 8F are diagrams showing the following steps. After completing the steps shown in FIGS. 8B and 8E, a resist is applied, and a resist pattern 17 is formed so that the resist remains in a region corresponding to the channel region 6 by a photolithography method. Then, using the resist pattern 17 as a mask, anisotropic etching is performed on the metal layer for the lower metal gate electrode 4 to form the lower metal gate electrode 4. As a result, the cross-sectional shapes shown in the cross-sectional views of FIGS. 8C and 8F are obtained.
  • FIGS. 9A to 9F are cross-sectional views showing a part of the steps constituting the manufacturing method of the MISFET 1 of the third embodiment.
  • 9A, FIG. 9B, and FIG. 9C show cross-sectional views along the line CD in FIG. 9D, 9E, and 9F show cross-sectional views along the dotted line AB in FIG. 9A to 9F show a substrate 13, an insulating layer 8 for element isolation, a metal layer for the upper metal gate electrode 3, a metal layer for the lower metal gate electrode 4, and amorphous silicon.
  • a layer (amorphous silicon layer) 19 a protective film 20, a protective film 21, a resist layer 24, and illumination light 26 are shown.
  • FIGS. 9A and 9D show a state where a metal layer for the upper metal gate electrode 3 is deposited by sputtering or CVD after the steps of FIGS. 8C and 8F are completed.
  • FIG. 9B and FIG. 9E are diagrams showing the following steps. 9A and 9D, a positive resist layer 24 is applied, transparent substrate power illumination is performed, and the resist layer 24 is exposed by light transmitted through the metal layer for the upper metal gate electrode 3. . As a result, the cross-sectional shapes shown in FIGS. 9B to 9E are obtained.
  • FIG. 9C and FIG. 9F show the resist pattern formed by removing the exposed portion of the resist layer 24 after the steps of FIG. 9B and FIG. 9E are completed.
  • the positive type resist is a resist in which the exposed portion is soluble.
  • FIG. 10A and FIG. 10B are cross-sectional views showing a part of the steps constituting the manufacturing method of the MISFET 1 of the third embodiment.
  • FIG. 10A shows a cross-sectional view along the line C-D in FIG. Fig. 10B shows a cross-sectional view along the dotted line AB in Fig. 1.
  • 10A and 10B show a substrate 13, an insulating layer 8 for element isolation, a metal layer for the upper metal gate electrode 3, a metal layer for the lower metal gate electrode 4, and an amorphous silicon layer (amorphous silicon layer). Layer) 19, protective film 20, protective film 21, and resist layer 24 are shown.
  • FIGS. 10A and 10B after the steps of FIGS. 9C and 9F are completed, the upper metal gate electrode 3 is formed by etching the metal layer for the upper metal gate electrode 3 using the resist pattern as a mask. It shows where. As a result, the cross-sectional shape shown in FIGS. 10A and 10B is obtained. Note that the cross-sectional shapes shown in FIGS. 10A and 10B are similar to the cross-sectional shapes shown in FIGS. 4B and 4E.
  • FIGS. 8A to 8F, FIGS. 9A to 9F, 10A, and 10B when a modification of the method for manufacturing the MISFET of Example 2 according to Example 3 is used, the lower metal gate is used.
  • the upper metal gate electrode 3 can be formed in a self-aligned manner with respect to the electrode 4 and the channel region 6. Therefore, after the modification of the manufacturing method of the MISFET of Example 2,
  • the source drain region that can form the upper metal gate electrode 3 in a self-aligned manner is formed in a self-aligned manner with respect to the lower metal gate electrode 4 and the channel region 6. can do.
  • the present invention provides a MISFET having a metal gate electrode, a multi-gate electrode structure, and a structure in which a leakage current between the source and drain is reduced, and a method of manufacturing the MISFET. it can.
  • Amorphous silicon layer (amorphous silicon layer)
  • Amorphous silicon layer (amorphous silicon layer)

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  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Recrystallisation Techniques (AREA)
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Abstract

L'invention concerne un MISFET présentant une électrode métallique de grille comportant une structure d'électrode multigrille, caractérisé en ce que le courant de fuite entre la source et le drain est réduit. L'invention concerne également une méthode de fabrication d'un tel MISFET. Le MISFET comprend une première électrode métallique de grille, une seconde électrode métallique de grille disposée parallèlement à la première électrode métallique de grille et s'étendant dans la même direction que la première électrode métallique de grille, une première couche de semiconducteur intercalée entre les première et seconde électrodes métalliques de grille à travers un film d'isolation de grille, et une seconde couche de semiconducteur adjacente aux faces opposées de la première couche de semiconducteur et aux faces opposées des première et seconde électrodes métalliques de grille. Ce MISFET est caractérisé en ce que des grains de cristaux aciculaires existent dans la première couche de semiconducteur dans un sens perpendiculaire à la direction selon laquelle s'étendent les première et seconde électrodes métalliques de grille.
PCT/JP2006/306424 2006-03-29 2006-03-29 Dispositif a semiconducteurs et processus de fabrication de celui-ci WO2007110940A1 (fr)

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US10615179B2 (en) 2010-02-05 2020-04-07 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
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US9685562B2 (en) 2010-09-13 2017-06-20 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, power diode, and rectifier
US9324877B2 (en) 2010-09-13 2016-04-26 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, power diode, and rectifier
US11715800B2 (en) 2010-09-13 2023-08-01 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, power diode, and rectifier
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JP2018006412A (ja) * 2016-06-28 2018-01-11 学校法人東北学院 半導体装置

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