Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
  • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B82—NANOTECHNOLOGY
  • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
  • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/0411—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having floating gates
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/0413—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having charge-trapping gate insulators, e.g. MNOS transistors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/68—Floating-gate IGFETs
  • H10D30/687—Floating-gate IGFETs having more than two programming levels
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
  • H10D30/691—IGFETs having charge trapping gate insulators, e.g. MNOS transistors having more than two programming levels
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/01—Manufacture or treatment
  • H10D64/031—Manufacture or treatment of data-storage electrodes
  • H10D64/035—Manufacture or treatment of data-storage electrodes comprising conductor-insulator-conductor-insulator-semiconductor structures
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/01—Manufacture or treatment
  • H10D64/031—Manufacture or treatment of data-storage electrodes
  • H10D64/037—Manufacture or treatment of data-storage electrodes comprising charge-trapping insulators
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
  • H10D86/01—Manufacture or treatment

Definitions

• This invention relates in general to semiconductor devices and more specifically to a back-gated semiconductor device with a storage layer and methods for forming thereof.
• FDSOI Fully Depleted Semiconductor-on- Insulator
• HCI hot carrier injection
• Figure 1 is a side view of one embodiment of two wafers being bonded together to form a resultant wafer, consistent with one embodiment of the invention
• Figure 2 shows a side view of one embodiment of a bonded wafer, consistent with one embodiment of the invention
• Figure 3 shows a partial cross-sectional side view of one embodiment of a wafer during a stage in its manufacture, consistent with one embodiment of the invention
• Figure 4 shows a partial cross-sectional side view of one embodiment of a wafer during another stage in its manufacture, consistent with one embodiment of the invention
• Figure 5 shows a partial cross-sectional side view of one embodiment of a wafer during another stage in its manufacture, consistent with one embodiment of the invention
• Figure 6 shows a partial cross-sectional side view of one embodiment of a wafer during another stage in its manufacture, consistent with one embodiment of the invention
• Figure 7 shows a partial cross-sectional side view of one embodiment of a wafer during another stage in its manufacture, consistent with one embodiment of the invention
• Figure 8 shows a partial cross-sectional side view of one embodiment of a wafer during another stage in its manufacture, consistent with one embodiment of the invention
• Figure 9 shows a partial cross-sectional side view of one embodiment of a wafer during another stage in its manufacture, consistent with one embodiment of the invention
• Figure 10 shows a partial cross-sectional side view of one embodiment of a wafer during another stage in its manufacture, consistent with one embodiment of the invention
• Figure 11 shows a partial cross-sectional side view of one embodiment of a wafer during another stage in its manufacture, consistent with one embodiment of the invention
• Figure 12 shows a partial cross-sectional side view of one embodiment of a wafer during another stage in its manufacture, consistent with one embodiment of the invention
• Figure 13 shows a partial cross-sectional side view of one embodiment of a wafer during another stage in its manufacture, consistent with one embodiment of the invention
• Figure 14 shows a partial cross-sectional side view of one embodiment of a wafer during another stage in its manufacture, consistent with one embodiment of the invention
• Figure 15 shows a partial cross-sectional side view of one embodiment of a wafer during another stage in its manufacture, consistent with one embodiment of the invention.
• a back-gated non-volatile memory (NVM) device with its channel available for contacting to overcome the typical problem of charge accumulation associated with NVMs in semiconductor on insulator (SOI) substrates is provided.
• a substrate supports the gate.
• a storage layer is formed on the gate, which may be nanocrystals encapsulated in an insulating layer, but could be of another type such as nitride.
• a channel is formed on the storage layer.
• a conductive region which can be conveniently contacted, is formed on the channel. This results in an escape path for minority carriers that are generated during programming, thereby avoiding charge accumulation in or near the channel.
• Figure 1 shows a side view of two wafers 101 and 103 that are to be bonded together to form a resultant wafer (201 of Figure 2), from which non- volatile memory cells may be formed, for example.
• Wafer 101 includes a layer 109 of gate material, a storage layer 107, and semiconductor substrate 105.
• substrate 105 is made of monocrystaline silicon, but in other embodiments, may be made of other types of semiconductor materials such as silicon carbon, silicon germanium, germanium, type III-V semiconductor materials, type II-VI semiconductor materials, and combinations thereof including multiple layers of different semiconductor materials.
• semiconductor material of substrate 105 may be strained.
• Storage layer 107 may be a thin film storage layer or stack and may be made of any suitable material, such as nitrides or nanocrystals. Nanocrystals, such as metal nanocrystals, semiconductor (e.g., silicon, germanium, gallium arsenide) nanocrystals, or a combination thereof may be used. Storage layer 107 may be formed by a chemical vapor deposition process, a sputtering process, or another suitable deposition process.
• layer 109 includes doped polysilicon, but may be made of other materials such as, amorphous silicon, tungsten, tungsten silicon, germanium, amorphous germanium, titanium, titanium nitride, titanium silicon, titanium silicon nitride, tantalum, tantalum silicon, tantalum silicon nitride, other suicide materials, other metals, or combinations thereof including multiple layers of different conductive materials.
• An insulator 111 may be formed (e.g., grown or deposited) on layer 109.
• insulator 111 includes silicon oxide, but may include other materials such as e.g. PSG, FSG, silicon nitride, and/or other types of dielectric including high thermal, conductive dielectric materials.
• Wafer 103 may include a substrate 115 (e.g., silicon) with an insulator 113 formed on it.
• the material of insulator 113 is the same as the material of insulator 111.
• wafer 103 includes a metal layer (not shown) at a location in the middle of insulator 113. This metal layer may be utilized for noise reduction in analog devices built from resultant wafer 201.
• Wafer 101 is shown inverted so as to be bonded to wafer 103 in the orientation shown in Figure 1.
• insulator 111 is bonded to insulator 113 with a bonding material.
• wafer 101 may be bonded to wafer 103 using other bonding techniques.
• wafer 101 may be bonded to wafer 103 by electrostatic bonding followed by thermal bonding or pressure bonding.
• wafer 101 does not include insulator 111 where layer 109 is bonded to insulator 113.
• wafer 103 does not include insulator 113 where insulator 111 is bonded to substrate 115.
• Wafer 101 may include a stress layer 106 formed by implanting a dopant (e.g. H+) into substrate 105.
• a dopant e.g. H+
• the dopant is implanted prior to the formation of storage layer 107, but in other embodiments, may be implanted at other times including after the formation of storage layer 107 and prior to the formation of layer 109, after the formation of layer 109 and prior to the formation of insulator 111, or after the formation of insulator 111.
• the dopant for forming stress layer 106 may be implanted after wafer 103 has been bonded to wafer 101.
• Figure 2 shows a side view of resultant wafer 201 after wafer 103 and 101 have been bonded together.
• the view in Figure 2 also shows wafer 201 after a top portion of substrate 105 has been removed, e.g., by cleaving.
• cleaving is performed by dividing substrate 105 at stress layer 106.
• Layer 203 is the remaining portion of substrate 105 after the cleaving.
• One advantage of forming the layer by cleaving is that it may allow for a channel region to be formed from a relatively pure and crystalline structure as opposed to a semiconductor layer that is grown or deposited on a dielectric.
• Figure 3 shows a partial side cross-sectional view of wafer 201. Not shown in the view of Figure 3 (or in subsequent Figures) are insulator 113 and substrate 115. After substrate 105 is cleaved to form layer 203, an oxide layer 303 is formed over layer 203. Layer 303 may be thicker than layer 203. Next, as shown in Figure 4, a layer of polysilicon, to form conductive region 401, may be deposited over oxide layer 303 after a middle portion of oxide layer 303 is patterned and then etched away. Thus, polysilicon layer is deposited directly on the transistor channel. The polysilicon layer may be doped in-situ or doped by implantation.
• Conductive region 401 may be used as a well contact. If necessary, an appropriate pre-clean may be performed to remove any interfacial oxide layer. Conductive region 401 may remove minority carriers, such as holes from the channel region 203 of a transistor formed from wafer 201.
• polysilicon layer forming conductive region 401 may be planarized by chemical-mechanical polishing, for example. Furthermore, a portion from top part of polysilicon layer forming conductive region 401 may be etched and a nitride cap 501 may be formed on top of conductive region 401. In one embodiment, nitride cap 501 should be at least as thick as layer 203 so that nitride cap 501 may serve as an implant mask during implantation described with respect to Figure 7. This would ensure the doping of layer 401 is unaltered during implantation. Referring now to Figure 6, a liner 601, such as an oxide liner may be formed after oxide layer 303 is removed.
• two implants 701 may be performed.
• amorphization implants may be performed in portions 707/709.
• germanium may be used to perform amorphization implants.
• source/drain implants may be performed in portions 703/705 to form source/drain extensions. Appropriate n-type or p-type dopants may be used as part of this step.
• the region (203) under conductive region 401 may serve as a channel region.
• a spacer 801 may be formed on the sidewalls of conductive region 401 (lined by liner 601). Spacer 801 may be made of multiple layers of dielectric materials. Spacer 801 may protect certain portions of portions 703/705 during subsequent processing. Next, exposed portions of portions 703/705 may be etched away.
• a second spacer 901 may be formed to protect sidewalls of portions 703/705. Furthermore, portions 707/709 implanted with amorphization implants may be etched away.
• an oxide layer 1001 may be deposited on wafer 201.
• selected portions of oxide layer 1001 may be etched away. Etching of selected portions of oxide layer 1001 may result in partial etching of liner 601, as well.
• Figure 12 shows a partial cross-sectional side view of wafer 201 after structures 1201 and 1203 are epitaxially grown on the exposed sidewalls of channel region (including portion 203).
• an amorphous silicon layer 1301/1303 may be deposited.
• Amorphous silicon layer 1301/1303 may be subjected to chemical mechanical polishing and etched back.
• a photoresist layer 1401 may be formed on top of a selected portion of wafer 201 and source/drain implants 1403 may be made forming doped source/drain regions 1405 and 1411.
• suicides 1501, 1503, and 1505 may be formed after nitride cap 501 is stripped.
• Gate suicide 1503 may be formed on top of conductive region 401.
• suicides may be formed using a suicide implantation (e.g., cobalt or nickel) followed by a heat treatment.
• suicides may be formed by depositing a layer of metal over the wafer and reacting the metal with the underlying material.
• the semiconductor device formed on wafer 201 may be used as a non- volatile memory.
• the non- volatile memory may include cells formed of the semiconductor device, which may be programmed using techniques such as, hot carrier injection.
• hot carrier injection For example, using HCI, one bit per cell may be stored in storage layer 107 by applying a positive bias voltage to gate 109, applying a positive voltage to drain region 1411, grounding source region 1405, and applying a negative voltage to conductive region 401 or grounding conductive region 401.
• HCI programming may result in generation of minority carriers, such as holes because of impact ionization.
• Conductive region 401 may provide an escape path for holes thereby preventing accumulation of holes in channel region 203.

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• Engineering & Computer Science (AREA)
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• Theoretical Computer Science (AREA)
• Crystallography & Structural Chemistry (AREA)
• Semiconductor Memories (AREA)
• Non-Volatile Memory (AREA)
• Thin Film Transistor (AREA)

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• 2005
  • 2005-12-14 US US11/300,077 patent/US7679125B2/en active Active
• 2006
  • 2006-11-08 WO PCT/US2006/060639 patent/WO2007094873A2/en not_active Ceased
  • 2006-11-08 JP JP2008545894A patent/JP5230870B2/ja active Active
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