Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N9/00—Details of colour television systems
  • H04N9/12—Picture reproducers
  • H04N9/31—Projection devices for colour picture display, e.g. using electronic spatial light modulators [ESLM]
  • H04N9/3179—Video signal processing therefor
• • G—PHYSICS
  • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
  • G03B—APPARATUS OR ARRANGEMENTS FOR TAKING PHOTOGRAPHS OR FOR PROJECTING OR VIEWING THEM; APPARATUS OR ARRANGEMENTS EMPLOYING ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ACCESSORIES THEREFOR
  • G03B21/00—Projectors or projection-type viewers; Accessories therefor
  • G03B21/005—Projectors using an electronic spatial light modulator but not peculiar thereto
• • G—PHYSICS
  • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
  • G03B—APPARATUS OR ARRANGEMENTS FOR TAKING PHOTOGRAPHS OR FOR PROJECTING OR VIEWING THEM; APPARATUS OR ARRANGEMENTS EMPLOYING ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ACCESSORIES THEREFOR
  • G03B21/00—Projectors or projection-type viewers; Accessories therefor
  • G03B21/14—Details
• • G—PHYSICS
  • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
  • G03B—APPARATUS OR ARRANGEMENTS FOR TAKING PHOTOGRAPHS OR FOR PROJECTING OR VIEWING THEM; APPARATUS OR ARRANGEMENTS EMPLOYING ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ACCESSORIES THEREFOR
  • G03B21/00—Projectors or projection-type viewers; Accessories therefor
  • G03B21/14—Details
  • G03B21/20—Lamp housings
  • G03B21/208—Homogenising, shaping of the illumination light
• • G—PHYSICS
  • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
  • G03B—APPARATUS OR ARRANGEMENTS FOR TAKING PHOTOGRAPHS OR FOR PROJECTING OR VIEWING THEM; APPARATUS OR ARRANGEMENTS EMPLOYING ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ACCESSORIES THEREFOR
  • G03B33/00—Colour photography, other than mere exposure or projection of a colour film
  • G03B33/08—Sequential recording or projection
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/007—Use of pixel shift techniques, e.g. by mechanical shift of the physical pixels or by optical shift of the perceived pixels
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
  • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
  • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
  • G09G5/005—Adapting incoming signals to the display format of the display terminal
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
  • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
  • G09G5/39—Control of the bit-mapped memory
  • G09G5/395—Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N9/00—Details of colour television systems
  • H04N9/12—Picture reproducers
  • H04N9/31—Projection devices for colour picture display, e.g. using electronic spatial light modulators [ESLM]
  • H04N9/3102—Projection devices for colour picture display, e.g. using electronic spatial light modulators [ESLM] using two-dimensional electronic spatial light modulators
  • H04N9/3111—Projection devices for colour picture display, e.g. using electronic spatial light modulators [ESLM] using two-dimensional electronic spatial light modulators for displaying the colours sequentially, e.g. by using sequentially activated light sources
  • H04N9/3114—Projection devices for colour picture display, e.g. using electronic spatial light modulators [ESLM] using two-dimensional electronic spatial light modulators for displaying the colours sequentially, e.g. by using sequentially activated light sources by using a sequential colour filter producing one colour at a time
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2310/00—Command of the display device
  • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
  • G09G2310/0235—Field-sequential colour display
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2320/00—Control of display operating conditions
  • G09G2320/02—Improving the quality of display appearance
  • G09G2320/0242—Compensation of deficiencies in the appearance of colours
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
  • G09G3/2007—Display of intermediate tones
  • G09G3/2018—Display of intermediate tones by time modulation using two or more time intervals
  • G09G3/2022—Display of intermediate tones by time modulation using two or more time intervals using sub-frames
  • G09G3/2025—Display of intermediate tones by time modulation using two or more time intervals using sub-frames the sub-frames having all the same time duration

Definitions

• the present invention relates to an image display device such as a projector, an FMD (face mount display), an HMD (head mount display), and an electronic viewer.
• an image display device such as a projector, an FMD (face mount display), an HMD (head mount display), and an electronic viewer.
• a spatial light modulation device such as a transmissive or reflective liquid crystal panel or a DMD (digital 'micromirror' device)
• a spatial light modulation device such as a transmissive or reflective liquid crystal panel or a DMD (digital 'micromirror' device)
• the modulated light As an image display device that magnifies and projects images onto the screen using a projection optical system, a single-plate surface-sequential method that uses a single spatial light modulation device to display RGB color images in a surface-sequential manner, and each RGB color A multi-panel type that displays RGB color images simultaneously using a special spatial light modulation device is known.
• the display pixel position of the spatial light modulation device is selectively pixel-shifted by, for example, a pixel shift means having a liquid crystal cell and a birefringent plate, and an apparent pixel is obtained.
• a pixel shift means having a liquid crystal cell and a birefringent plate
• Patent Document 1 Japanese Patent Laid-Open No. 2005-57457
• one frame of the input video signal is divided into a plurality of subfields according to the number of pixel shifts and displayed. For this reason, if the division rate of the subfield is low, the flickering force due to pixel shift is conspicuous and the image quality is degraded.
• the display frame rate must be at least 40 Hz or less in order to make the flicker force due to pixel shift inconspicuous.
• the rewrite rate of the surface sequential image that is, the field sequential rate is set. If it is low, a color break occurs and the image quality is degraded.
• an object of the present invention which has been made in view of intensive situations, is to provide an image display device that can always display an image with good image quality so that flickering force due to pixel shift is not particularly noticeable.
• an image display apparatus that spatially modulates the light of the light source unit power and displays the image by shifting the pixels of the spatial light modulation unit by the pixel shift unit in synchronization with the video signal of the subfield.
• the frame rate of the input video signal is FD
• the optical modulation device rate of the spatial light modulator is M
• the number of subfield divisions is S
• the field sequence in the spatial light modulator is When the color rate is FS and the color separation number is C,
• an image processing unit for adjusting an input video signal and a video signal supplied to the spatial light modulation unit.
• the invention according to claim 2 is the image display device according to claim 1, wherein the image processing unit adds a video signal when a display frame rate in the spatial light modulation unit is higher than the FD. When the display frame rate is lower than the FD, the video signal is thinned out.
• the invention according to claim 3 is the image display device according to claim 2 or 3, wherein the image processing unit includes a memory that stores an input video signal in units of frames, and a memory that controls access to the memory.
• a controller a subfield dividing unit that divides the frame stored in the memory, a frame rate measuring unit that measures the frame rate of the input video signal, and a pixel shift based on the frame rate measured by the frame rate measuring unit.
• a pixel shift rate determination unit for determining a transmission rate, and a memory access by the memory controller based on the pixel shift rate determined by the pixel shift rate determination unit and a subfield division rate in the subfield division unit.
• a clock generator for generating a reference clock for controlling The one in which the features.
• the invention according to claim 4 is the image display device according to any one of claims 1 to 3, wherein the light source unit is a surface-sequential emission light source for color-sequential sequence,
• the spatial light modulation unit has one spatial light modulation device, and displays a color image in a frame sequential manner.
• the invention according to claim 5 is the image display device according to any one of claims 2 to 4, wherein the image processing unit has a display frame rate in the spatial light modulation unit higher than that of the FD. Is higher, the video signal is added for each field section to adjust the input video signal and the video signal supplied to the spatial light modulator.
• the invention according to claim 6 is the image display device according to any one of claims 2 to 4, wherein the image processing unit has a display frame rate in the spatial light modulator. If it is higher than the FD, a video signal is added every fixed interval to adjust the input video signal and the video signal supplied to the spatial light modulation unit.
• the invention according to claim 7 is the image display device according to any one of claims 2 to 4, wherein the image processing unit has a display frame rate in the spatial light modulation unit higher than that of the FD. Is lower, the video signal is thinned out every predetermined interval to adjust the input video signal and the video signal supplied to the spatial light modulator.
• the invention according to claim 8 is the image display device according to any one of claims 2 to 4, wherein the image processing unit has a display frame rate in the spatial light modulation unit higher than that of the FD. In the case of low, the video signal is adjusted for each field section, and the input video signal and the video signal supplied to the spatial light modulation unit are adjusted.
• the invention according to claim 9 is the image display device according to any one of claims 3 to 8, wherein the clock generation unit uses the clock extracted from the input video signal as a source. A reference clock is generated.
• the invention according to claim 10 is the image display device according to any one of claims 3 to 8, wherein the image processing unit includes an internal oscillator, and the clock generation unit includes the internal oscillator.
• the reference clock is generated using a clock generated by the above as a source.
• the invention according to claim 11 is the image display device according to claim 4, wherein a field sequential rate of the spatial light modulation device is 480 Hz.
• the invention according to claim 12 is the image display device according to claim 4, wherein a field sequential rate of the spatial light modulation device is 540 Hz.
• FIG. 1 is a block diagram showing a basic configuration of an image display device according to the present invention.
• FIG. 2 is a schematic configuration diagram of the image display device according to the first embodiment.
• FIG. 3 is a block diagram showing a configuration of a main part of the image processing unit shown in FIG.
• FIG. 4 is a diagram showing an example of subfield division in the subfield division unit shown in FIG.
• FIG. 5 is a timing chart showing the operation of the image display device in the first embodiment.
• FIG. 6 is a diagram for explaining a four-point pixel shift according to the first embodiment.
• FIG. 7 is a block diagram showing a configuration of a main part of an image processing unit in an image display device according to a second embodiment.
• FIG. 8 is a block diagram showing a configuration of a main part of an image processing unit in an image display device according to a third embodiment.
• FIG. 9 is a timing chart showing the operation of the image display device according to the fourth embodiment.
• FIG. 10 is a timing chart showing the operation of the image display device according to the fifth embodiment.
• FIG. 11 is a timing chart showing the operation of the image display apparatus according to the sixth embodiment.
• FIG. 12 is a block diagram showing a configuration of a main part of an image processing unit in an image display device according to a seventh embodiment.
• FIG. 13 is a timing chart showing the operation of the seventh embodiment.
• FIG. 14 is a schematic configuration diagram of an image display device according to an eighth embodiment.
• FIG. 15 is a block diagram showing a configuration of an image processing unit in an eighth embodiment.
• FIG. 16 is a timing chart showing the operation of the eighth embodiment.
• FIG. 17 is a timing chart showing the operation of the image display apparatus developed together with the present invention.
• FIG. 18 is a timing chart showing the operation of the image display apparatus developed together with the present invention.
• FIG. 1 is a block diagram showing a basic configuration of an image display apparatus according to the present invention.
• the image display device shown in FIG. 1 includes a light source unit 1, a spatial light modulation unit 2, a pixel shift unit 3, and a projection optical system 4, and also performs image processing for controlling the spatial light modulation unit 2 and the pixel shift unit 3.
• the illumination light emitted from the light source unit 1 is spatially modulated based on the video signal input to the image processing unit 5 in the spatial light modulation unit 2 and then selected in the pixel shift unit 3 Therefore, the image is shifted by the projection optical system 4 and the image is projected and displayed on a screen or the like.
• the image processing unit 5 includes a memory 51, a memory controller 52, a subfield dividing unit 53, a frame rate measuring unit 54, a pixel shift rate determining unit 55, and a clock generating unit 56.
• the light source unit 1 includes, for example, a white light source such as an ultrahigh pressure mercury (UHP) lamp or a halogen lamp and a color separation element such as a dichroic mirror. Or a LED light source of three colors (R, G, B) or more, and in the case of a single plate type, a white light source and a color separation element such as a color wheel. It is configured with power or multi-color LED light sources.
• a white light source such as an ultrahigh pressure mercury (UHP) lamp or a halogen lamp
• a color separation element such as a dichroic mirror.
• a LED light source of three colors (R, G, B) or more and in the case of a single plate type, a white light source and a color separation element such as a color wheel. It is configured with power or multi-color LED light sources.
• the spatial light modulation unit 2 includes, for example, three transmissive or reflective liquid crystal (LCD) and DMD (digital micromirror 'device) spatial light modulation devices in a multi-plate type, for example, a single-plate type.
• the pixel shift unit 3 includes, for example, a liquid crystal cell such as a TN liquid crystal or a ferroelectric liquid crystal that is a polarization rotation element, and a crystal, lithium niobate, rutile, calcite, And a birefringent plate made of anisotropic crystals such as chili glass.
• FIG. 2 is a schematic configuration diagram of the image display device according to the first embodiment.
• This image display device is a single plate surface sequential system that displays the three primary colors in a surface sequential manner with a single spatial light modulation device, and the light source unit is a powerful white light source 11 such as a UHP lamp 11, a reflector 12 and a fly eye lens.
• the spatial light modulation unit is configured by using a batch write type transmissive LCD 16 as a spatial light modulation device, and writes and displays the frame sequential data output from the image processing unit 5.
• transmissive LCD 16 those with a field sequential rate of 360 Hz, 480 Hz, 540 Hz, 720 Hz, etc. are known, and a high rate is used to effectively reduce the color break.
• 720 Hz one is expensive and difficult to obtain, the one with a relatively low price and easy to obtain is used here.
• the pixel shift unit includes a horizontal pixel shift set having a liquid crystal cell 17A and a birefringent plate 18A, and a vertical pixel shift set having a liquid crystal cell 17B and a birefringent plate 18B. It is configured to shift four pixels in the horizontal and vertical directions, and the image displayed on the transmissive LCD 16 is projected and displayed on the screen 19 via this pixel shift unit and the projection optical system 4. ing.
• FIG. 3 is a block diagram showing a configuration of a main part of the image processing unit 5 shown in FIG.
• the image processing unit 5 receives an input video signal and generates a clock.
• an input interface (hereinafter also referred to as input IZF) for extracting data such as horizontal synchronization signal (hereinafter also referred to as HD), vertical synchronization signal (hereinafter also referred to as VD) 57, and subfield division unit 53.
• HD horizontal synchronization signal
• VD vertical synchronization signal
• It has a field sequential conversion unit 58 that divides subfield image data into RGB color data, a liquid crystal cell control unit 59 that controls the driving of liquid crystal cells 17A and 17B in the pixel shift unit in synchronization with the subfield, etc. ing.
• the image processing unit 5 extracts the input video signal power from the input IZF 57, such as clock, HD, VD and data, and writes it to the memory 51.
• the image data of the frame from the memory 51 is subfield dividing unit. Each frame data is divided into four subfields, and the image data of the subfield is divided into RGB color data by the frame sequential conversion unit 58 and transmitted through a transmissive LCD controller (not shown).
• Type LCD1 6 and a signal synchronized with the subfield are supplied to the liquid crystal cell control unit 59 to control the driving of the liquid crystal cells 17A and 17B of the pixel shift unit.
• the memory 51 has, for example, a buffer for three frames, and writing and reading are controlled by the memory controller 52.
• the image processing unit 5 includes a color wheel control unit that controls the rotation of the color wheel 13 in synchronization with the data division of each color in the frame sequential conversion unit 58.
• the VD extracted by the input IZF 57 is also supplied to the frame rate measuring unit 54, where the input frame rate (frame frequency, hereinafter also referred to as FD) is measured based on the sequential VD.
• the measurement result is transferred to the pixel shift rate determination unit 55.
• the pixel shift rate determination unit 55 measures, as the pixel shift rate, the field sequential rate of the transmissive LCD 16, the number of color separations by the color wheel 13, the number of subfield divisions by the subfield division unit 53, and the frame rate measurement. Based on the FD measured by the unit 54, a multiple of the reception clock of the input video signal extracted by the input IZF 57 is calculated, and the calculation result is supplied to the clock generation unit 56.
• the reception clock extracted by the input IZF 57 is multiplied by the multiple of the clock from the pixel shift rate determination unit 55, and the multiplied reception clock is synchronized with the reference clock.
• the memory 51, the memory controller 52, the subfield division unit 53, and the frame sequential conversion unit 58 are supplied to the memory 51, the memory controller 52, the subfield division unit 53, and the frame sequential conversion unit 58.
• the pixel shift rate determination unit 55 calculates the subfield frame rate based on the field sequential rate and the color separation number, and displays the display frame based on the subfield frame rate and the subfield division number. The rate is calculated, and the calculation results of the subfield frame rate and the display frame rate are supplied to the memory controller 52, the subfield division unit 53, and the frame sequential conversion unit 58.
• an interpolation processing unit for interpolating the video signal is provided between the input IZF 57 and the memory 51, and between the memory 51 and the subfield dividing unit 53, A data processing unit for processing image data such as Hans ⁇ Gamma processing is provided.
• the operation of the present embodiment will be described by taking as an example the case where the input video signal is 1080i and the effective size of the transmissive LCD 16 is XGA.
• 1080i means an interlaced video signal with an effective pixel size of S 1920 X 1080 and 60 Hz.
• the description of other than 1080i is omitted here.
• the input IZF57! / Receives 1080i odd (ODD) field and even (EVEN) field video signals alternately, and receives them as one effective pixel size of 1920 x 1080. Is written in the memory 51 as a video signal. This process may be performed by adding a memory between the input IZF 57 and the memory 51, or using an IP conversion controller.
• the 1920 x 1080 video signal written in the memory 51 is sub-divided by the sub-field dividing unit 53, as shown in Fig. 4, and one sub-field is divided into four sub-fields A of 960 x 540 size A. Divide into ⁇ D.
• the transmissive LCD 16 has an XGA (1024 X 768) size
• the transmissive LCD 16 is larger than the effective pixels of the input image. The number of effective pixels increases. Therefore, in this embodiment, as shown in FIG. 4, subfields are generated while embedding data masked in black. Thereafter, the generated subfields A to D are transmitted to the frame sequential conversion unit 58, where the subfields A to D are divided into RGB data and transmitted to the transmissive LCD 16.
• the data for filling in the missing pixels of the transmissive LCD 16 is not limited to black mask data, and can be displayed as arbitrary data by using an interpolation processing unit (not shown) arranged in front of the subfield division unit 53, for example. I'll do it for you.
• the frame rate measurement unit 54 measures and recognizes that the input video signal is interlaced at 60Hz at 1080i from the VD and field information from the input I / F 57. The information that the input frame rate (FD) power combined with 30Hz is obtained. The frame rate measurement result (30 Hz) is sent to the pixel shift rate determination unit 55.
• the pixel shift rate determination unit 55 calculates the clock multiple, the subfield frame rate, and the display frame rate of the input video signal according to the following equations (1), (2), and (3). Calculate each one.
• n 0 (4-point pixel shift), 1 (2-point pixel shift)
• the calculation result is as follows.
• the field sequential rate is an approximate value for each display color and does not match the area ratio of the color wheel 13. In other words, in some cases, R light is emitted for a long time and G light is emitted in a shorter time than R light. is there.
• the clock multiplication factor (4/3) calculated by the pixel shift rate determination unit 55 is supplied to the clock generation unit 56, and the reception clock of the input video signal extracted by the input IZF 57 is multiplied by 4Z3.
• the multiplied received clock and the synchronized clock are supplied as a reference clock to the memory 51, the memory controller 52, the subfield division unit 53, and the frame sequential conversion unit 58.
• the subfield frame rate and the display frame rate calculated by the pixel shift rate determination unit 55 are supplied to the memory controller 52, the subfield division unit 53, and the frame sequential conversion unit 58.
• the frame rate measuring unit 54 and the pixel shift rate determining unit 55 can be easily configured using a microcomputer using a CPU, and the clock generating unit 56 uses a PLL circuit. And can be configured easily.
• FIG. 5 is a timing chart showing the operation of the image display device in the present embodiment.
• FD 30 Hz
• subfield frame rate 160 Hz
• field sequential rate 480 Hz
• display frame rate 40 Hz.
• the memory 51 has a buffer for three frames.
• the memory controller 52 is a memory with a clock (4Z3 times) faster than the reception clock generated by the clock generator 56. Since 51 is read out, there are not enough images to display. Therefore, in FIG. 5, “Movie3” is read twice and adjusted with the frame rate to be displayed (hereinafter, image data to be embedded in such a manner is referred to as “PADDING DATA”).
• PADDING DATA is not limited to reading “Movie3” twice, but may read an input video (for example, Movie2) twice according to the display image.
• FIGS. 6A to 6D are diagrams for explaining the 4-point pixel shift according to the present embodiment.
• the liquid crystal cell 17A for horizontal pixel shift and the liquid crystal cell 17B for vertical pixel shift are both in the OFF state.
• the polarization plane of the light passing through the transmissive LCD 16 is in the horizontal direction, it is rotated 90 ° in the liquid crystal cell 17A to become a vertical polarization plane without being shifted in pixels by the birefringent plate 18A.
• the light is further rotated by 90 ° in the liquid crystal cell 17B to become a horizontal polarization plane, and is transmitted as it is without being shifted by the birefringent plate 18B. Therefore, the pixel after passing through the pixel shift means
• the position is the same position as the pixel position before transmission, that is, position A when one pixel is noticed.
• the light from the transmission type LCD 16 is transmitted through the liquid crystal cell 17A without being rotated on the polarization plane.
• the birefringent plate 18A is shifted by a half pixel pitch in the horizontal direction, and the liquid crystal cell 17B transmits the polarization plane in the horizontal direction without being rotated. Therefore, the birefringent plate 18B is not shifted in pixel.
• the pixel position after passing through the pixel shift unit is a position B shifted by a half pixel pitch in the horizontal direction.
• the horizontal polarization plane shifted by a half pixel pitch in the horizontal direction by the birefringent plate 18A is 90% in the liquid crystal cell 17B.
• the half-pixel pitch is shifted in the vertical direction by the birefringent plate 18B. Therefore, the pixel position after passing through the pixel shift portion is a position C that is shifted by a half pixel pitch in the horizontal and vertical directions.
• the liquid crystal cell 17A is turned OFF and the liquid crystal cell 17B is turned ON, the light from the transmissive LCD 16 is rotated by 90 ° in the liquid crystal cell 17A to become a vertical polarizing surface, and the birefringent plate 18A. Therefore, the light is transmitted as it is without being shifted by the pixel and further transmitted through the liquid crystal cell 17B with the polarization plane in the vertical direction, so that the birefringent plate 18B is shifted by a half pixel pitch in the vertical direction. Therefore, the pixel position after passing through the pixel shift portion is a position D shifted by a half pixel pitch in the vertical direction.
• the resolution can be improved by performing a four-point pixel shift in which each pixel position of the transmissive LCD 16 is shifted by a half pixel pitch in the horizontal and vertical directions.
• the spatial light modulation unit is relatively inexpensive and easily available, and is configured using the transmissive LCD 16 having a field sequential rate power of 80 ⁇ , and the pixel shift unit performs pixel shift.
• the subfield division rate due to pixel shift can be increased, and the flickering force due to wobbling (pixel shift) can be made inconspicuous.
• the color break can be reduced.
• FIG. 7 is a block diagram showing a configuration of a main part of the image processing unit in the image display device according to the second embodiment of the present invention.
• an internal oscillator 60 having a crystal oscillator is provided in the image processing unit 5, and the oscillation output of the internal oscillator 60 is divided based on the clock multiple that is calculated by the pixel shift rate determination unit 55. Then, a signal corresponding to a desired HD is generated, and the signal is supplied to the clock generation unit 56 to generate a reference clock.
• Other configurations and operations are the same as those in the first embodiment.
• the first embodiment will be described. Therefore, it is possible to generate a reference clock with less jitter compared to generating a reference clock by multiplying the clock extracted from the input video signal power, so that a clearer image can be displayed. Can do.
• FIG. 8 is a block diagram showing a configuration of a main part of the image processing unit in the image display device according to the third embodiment of the present invention.
• the image processing unit 5 includes a memory 51, a memory controller 52, a subfield division unit 53, a frame rate measurement unit 54, a pixel shift rate determination unit 55, A connection cable (not shown) is separated into a first image processing unit 5a having a clock generation unit 56 and an input IZF 57 and a second image processing unit 5b having a surface sequential conversion unit 58 and a liquid crystal cell control unit 59. It is possible to connect with.
• the second image processing unit 5b can be provided on the main body side of the image display device, and the first image processing unit 5a can be provided separately from the image display device. There is an advantage that downsizing and low cost can be achieved.
• the internal oscillator 60 may be provided in the first image processing unit 5a.
• FIG. 9 is a timing chart showing the operation of the image display apparatus according to the fourth embodiment of the present invention.
• this embodiment inserts “PADDING DATA” in units of subfields rather than in units of frames, and displays them at fixed intervals. The image is adjusted to establish the relationship with the pixel shift.
• FIG. 10 is a timing chart showing the operation of the image display apparatus according to the fifth embodiment of the present invention.
• the transmissive LCD 16 having a field sequential rate higher than 480 Hz and a relatively low price and easily available 540 Hz is used.
• the clock multiplier, subfield frame rate, and display frame rate calculated by the pixel shift rate determination unit 55 of the image processing unit 5 are as follows: Obviously, in the case of the present embodiment, the clock multiplier, subfield frame rate, and display frame rate calculated by the pixel shift rate determination unit 55 of the image processing unit 5 are as follows: Obviously, in the case of the present embodiment, the clock multiplier, subfield frame rate, and display frame rate calculated by the pixel shift rate determination unit 55 of the image processing unit 5 are as follows: Become.
• the clock power multiple is 3Z2 times. Therefore, in FIG. 10, “Movie2” is read twice and displayed to adjust the input video signal. Is going.
• the field sequential rate of the transmissive LCD 16 is 5 Since the 40 Hz one is used, the display frame signal can be 45 Hz. Therefore, the flickering force due to pixel shift can be made less noticeable and color breaks can be reduced a little.
• FIG. 11 is a timing chart showing the operation of the image display apparatus according to the sixth embodiment of the present invention.
• This embodiment is a case where the frame rate FD of the input video signal is 60 Hz as in the PC use etc. in the first embodiment.
• the clock multiplier, subfield frame rate, and display frame rate calculated by the pixel shift rate determination unit 55 of the image processing unit 5 are as follows.
• the display frame signal power ⁇ is lower than the input frame rate of 60 Hz, so that a clock is generated in a similar sequence as shown in FIG. Adjusting the input video signal and display frame by thinning out Movie3 so that it is not displayed.
• the display frame signal and the input video signal may be adjusted by performing overtaking control using a memory. More specifically, the overtaking control for setting the 75 Hz input to 60 Hz may be performed in the memory.
• FIG. 12 shows the essential parts of the image processing unit in the image display device according to the seventh embodiment of the invention. It is a block diagram which shows the structure of a part.
• the image processing unit 5 is omitted from the frame rate measurement unit 54, the pixel shift rate determination unit 55, and the clock generation unit 56, and the memory 51, the memory Consists of a controller 52, subfield division unit 53, input IZF57, frame sequential conversion unit 58, liquid crystal cell control unit 59, internal oscillator 60 and IP conversion unit 61.
• the transmissive LCD 16 has a field sequential rate of 540 Hz. .
• the 1080i input video signal is received by the input IZF57, output as it is as a 60 Hz interlaced video signal (60i), converted to a 60 Hz progressive signal (60P) by the IP converter 61, and written to the memory 51. It is.
• the internal oscillator 60 oscillates a dot clock in accordance with a field sequential rate of 540 Hz, and the memory 51 is read by this clock, and is tripled by the frame sequential conversion unit 58 to be transmitted to the transmissive LCD 16. Transferred.
• FIG. 13 is a timing chart showing the operation in this case. In each frame, one of the four subfields is thinned, and the display frame signal and the input video signal are adjusted.
• the image processing unit 5 can be configured easily and inexpensively as compared with the above embodiment.
• FIGS. 14 to 16 show an eighth embodiment of the present invention.
• FIG. 14 is a schematic configuration diagram of an image display device
• FIG. 15 is a block diagram showing a configuration of an image processing unit
• FIG. 16 is a timing diagram showing an operation. This is a chart.
• This image display device is a three-plate type using three transmissive LCDs and, as shown in FIG. 14, illuminating light from a light source unit having a white light source 11 and a reflector 12 is used as dichroic mirror.
• the light is incident on 32, where the R light is reflected and the other light is transmitted, and the separated R light is reflected by the mirror 33 and incident on the transmissive LCD 16R for R, and transmitted through the dichroic mirror 32.
• the illuminating light reflects the G light at the dichroic mirror 34, transmits the B light, and enters the G light into the transmissive LCD 16G for G.
• the B light passes through the mirrors 35 and 36, and the transmissive LCD 16B for B Enter I am shooting. Note that an illumination optical system such as a PZS converter is not shown.
• the transmissive LCD for R16R, the transmissive LCD for G16G, and the transmissive LCD for 16B and the images formed by modulation by B are combined by the combining prism and liquid crystal as in the above-described embodiment.
• the image is projected and displayed on the screen 19 through the projection optical system 4.
• the image processing unit 5 is provided with an LCD controller 62 instead of the field sequential conversion unit 58, and the LCD controller 62 transmits the transmissive LC D16R. , 16G, 16B simultaneously transfer image data.
• the operation of the present embodiment will be described taking as an example the case where the operation (light modulation device rate) of the transmissive LCDs 16R, 16G, and 16B is 160 Hz and the input video signal is 1080i.
• the 1080i odd field and even field video signals are alternately received and written in the memory 51 as one video signal.
• the input IZF 57 extracts the clock and HD VD, and the frame rate measuring unit 54 measures that the input frame rate (FD) is 30 Hz.
• the pixel shift rate judging unit 55 4), (5) and (6) are used to calculate the input video signal clock multiple, subfield frame rate and display frame rate, respectively.
• n 0 (4-point pixel shift), 1 (2-point pixel shift)
• the clock power multiple Z3 and the subfield frame rate is 1.
• 60Hz and display frame rate are 40Hz.
• the reception clock of the input video signal extracted by the input IZF57 is The multiplied clock is multiplied by the clock multiple calculated by the pixel shift rate determination unit 55, and the multiplied clock is supplied to the memory 51, the memory controller 52, the subfield dividing unit 53, and the LCD controller 62 as a reference clock.
• the subfield frame rate and display frame rate calculated by the pixel shift rate determination unit 55 are supplied to the memory controller 52, the subfield division unit 53, and the LCD controller 62.
• the video signal written in the memory 51 is read out with the reference clock from the clock generation unit 56, and is divided into four subfields A to D by the subfield division unit 53.
• the subfield video signal is transferred to the LCD controller 62 and written to the transmissive LCDs 16R, 16G, and 16B simultaneously.
• FIG. 16 is a timing chart showing the operation of the image display device in the present embodiment.
• FD 30 Hz
• subfield frame rate 160 Hz
• display frame rate 40 Hz.
• the memory 51 has a buffer for three frames.
• the memory controller 52 receives the reception clock generated by the clock generator 56. Since the memory 51 is read at a faster clock (4Z3 times), there are not enough images to be displayed. Therefore, in FIG. 16, similarly to the first embodiment, the "M. V ie3" and read twice, and subjected to adjustment of the frame rate to be displayed.
• the display frame rate is adjusted in the three-frame memory section, but the adjustment can be made with a larger frame memory.
• “PADDING DATA” is not limited to reading “Movie3” twice, but may read a certain input video (for example, Movie2) twice according to the display image.
• the subfield division rate due to pixel shift can be increased, and thus the flickering force due to wobbling (pixel shift) can be made inconspicuous.
• the present invention is not limited to the above-described embodiment, and many variations or modifications are possible.
• the frame sequential conversion unit 58 and the liquid crystal cell control unit 59 of the image processing unit 5 are separated from other constituent elements. You can also.
• the LCD controller port of the image processor 5 The controller 62 and the liquid crystal cell controller 59 can also separate other component forces.
• an internal oscillator can be provided to generate a reference clock.
• the power of the spatial light modulation device to be used is calculated by the pixel shift rate determination unit 55 of the image processing unit 5 that calculates the clock multiple, the subfield frame rate, and the display frame rate. If the field sequential rate (single-plate surface sequential method) and the light modulation device rate (multi-plate type) are known, only the clock multiple must be calculated. In this way, the circuit scale of the image processing unit 5 can be reduced and the cost can be reduced.
• the spatial light modulation device is not limited to a field sequential rate of 480 Hz or 540 Hz, and a device having a frequency of 600 Hz or 840 Hz can be used effectively.
• the four-point pixel shift is performed by the pixel shift means, but the present invention can also be effectively applied to a two-point pixel shift.
• the spatial light modulation device is not limited to a transmissive LCD, but a reflective LCD or DMD can be used, and even if a multi-plate type is used, it is effective not only for three plates but also for two or four or more plates Can be applied to.
• the pixel shift unit is not limited to the combination of the liquid crystal cell and the birefringent plate. For example, a well-known configuration disclosed in Japanese Patent Laid-Open No. 2003-279924 or a pixel shift unit based on a mechanical configuration may be used. You can also.
• the present invention can be effectively applied not only to color display but also to monochrome display.
• the color break can be reduced by adjusting the data in units of subfields.
• the display frame signal is the same as the input frame rate as shown in the timing chart of FIG. (30Hz)
• the data written to the transparent LC D16 which is generated by reading the memory 51 with the reference clock 4Z3 times faster than the reception clock, is white or black data in sub-field units as shown by diagonal lines.
• Embed "PADDING DATA" consisting of In this case, The reference clock may be generated from the received clock and may also generate an internal oscillator force
• a large frame memory is not required if white or black “PADDING DATA” is embedded in each subfield and adjusted with the input video signal.
• the color break can be reduced with an inexpensive configuration.
• the color break can be reduced by adjusting the writing of the corresponding color of the frame sequential color to "1Z2". it can.
• the data to be written at the beginning of the subfield is “R”
• write “r” data with this set to “1Z2” and then write “1 Z2” at the next “R” write timing.
• Write “r” data. “G” and “B” are similarly controlled.
• the response speed of the pixel shift unit is stored in advance in the pixel shift rate determination unit 55 of the image processing unit 5, and the above-described control is appropriately selected according to the input video image. I'll do it.

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• 2006
  • 2006-01-17 JP JP2006008959A patent/JP2007192919A/ja active Pending
  • 2006-08-04 WO PCT/JP2006/315522 patent/WO2007083409A2/ja not_active Ceased
• 2008
  • 2008-07-16 US US12/174,205 patent/US20090002297A1/en not_active Abandoned

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