Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
  • G06F17/10—Complex mathematical operations
  • G06F17/14—Fourier, Walsh or analogous domain transformations, e.g. Laplace, Hilbert, Karhunen-Loeve, transforms
  • G06F17/141—Discrete Fourier transforms
  • G06F17/142—Fast Fourier transforms, e.g. using a Cooley-Tukey type algorithm
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L27/00—Modulated-carrier systems
  • H04L27/26—Systems using multi-frequency codes
  • H04L27/2601—Multicarrier modulation systems
  • H04L27/2647—Arrangements specific to the receiver only
  • H04L27/2649—Demodulators
  • H04L27/265—Fourier transform demodulators, e.g. fast Fourier transform [FFT] or discrete Fourier transform [DFT] demodulators
  • H04L27/26522—Fourier transform demodulators, e.g. fast Fourier transform [FFT] or discrete Fourier transform [DFT] demodulators using partial FFTs

Definitions

• the present invention relates to a fast Fourier transform circuit.
• multimode fast Fourier transform circuit capable of supporting a plurality of communication methods, for example, there is one described in Patent Document 1.
• FIG. 1 is a block diagram showing a configuration of a conventional multimode fast Fourier transform circuit described in Patent Document 1.
• the multimode fast Fourier transform circuit 1 shown in FIG. 1 includes a serial / parallel transform circuit 11, a serial / parallel transform circuit 12, a switch 13, an FFT (Fast Fourier Transform) circuit 14, and a parallel / serial transform circuit 15 , A decimation circuit 16, an amplitude adjustment circuit 17, a zero signal generation circuit 18, a serial / parallel conversion circuit 19, and a combiner 20.
• a serial / parallel transform circuit 11 includes a serial / parallel transform circuit 11, a serial / parallel transform circuit 12, a switch 13, an FFT (Fast Fourier Transform) circuit 14, and a parallel / serial transform circuit 15 ,
• a decimation circuit 16 an amplitude adjustment circuit 17, a zero signal generation circuit 18, a serial / parallel conversion circuit 19, and a combiner 20.
• the synthesizer 20 when receiving an OFDM signal that requires Q-point FFT processing, the synthesizer 20 combines the received signal and the zero value data output from the zero signal generation circuit 18. , P point FFT processing is performed by converting Q parallel data to P parallel data.
• Patent Document 1 Japanese Unexamined Patent Application Publication No. 2004-186852 (Fig. 3)
• An object of the present invention is to provide a fast Fourier transform circuit capable of optimizing calculation resources while supporting a plurality of communication methods.
• the fast Fourier transform circuit of the present invention accumulates 2 N digital signals) and outputs a digital signal rearranged at a bit reversal position in which the order of each bit is reversed.
• a buffer a second buffer that accumulates 2 M (M is a natural number, where M ⁇ N) digital signals and outputs a digital signal rearranged in the bit reversal position, and the first buffer
• M is a natural number, where M ⁇ N) digital signals and outputs a digital signal rearranged in the bit reversal position
• the first fast Fourier transform processing unit that performs a first butterfly operation on the digital signal output from the second buffer and a second butterfly operation on the digital signal output from the second buffer;
• the second fast Fourier transform processing unit that performs the butterfly calculation process on the digital signal after the butterfly calculation process and the digital signal after the second butterfly calculation process are performed on the butterfly calculation process.
• the fast Fourier transform circuit of the present invention accumulates 2 N (N is a natural number) digital signals, and converts the digital signals rearranged at bit reversal positions in which the arrangement order of each bit is reversed.
• a first fast Fourier transform processing unit that performs a first butterfly operation process on the digital signal output from the first buffer and a second butterfly operation process on the digital signal output from the second buffer; , A third butterfly computation process on the digital signal after the first butterfly computation process and the second butterfly computation
• a fast Fourier transform processing unit is
• the fast Fourier transform circuit of the present invention accumulates 2 N (N is a natural number) digital signals, and converts the digital signals rearranged at bit reversal positions in which the arrangement order of each bit is reversed.
• First stage force for accumulated digital signal Nth stage butterfly computation process and first stage force (N-1) stage butterfly computation for (N-1) data storage units N butterflies for processing A calculation unit, and N switches for switching output destinations of digital signals input from the first buffer or the second buffer and the N butterfly calculation units, and the N switches are: A configuration is adopted in which the input digital signal is output to the next data storage unit or the next switch according to the setting.
• FIG. 1 is a block diagram showing an example of a conventional multimode fast Fourier transform circuit.
• FIG. 2 is a block diagram showing a configuration of a fast Fourier transform circuit according to the first embodiment of the present invention.
• FIG. 3 is a diagram showing a state of digital signal rearrangement and butterfly computation in the first embodiment.
• FIG. 4 is a block diagram showing a configuration of a butterfly computation unit in the first embodiment.
• FIG. 5 is a block diagram showing a modification of the first embodiment.
• FIG. 6 is a block diagram showing another modification of the first embodiment
• FIG. 7 is a block diagram showing still another modification of the first embodiment.
• FIG. 8 is a block diagram showing a configuration of a fast Fourier transform circuit according to the second embodiment of the present invention.
• FIG. 9 is a block diagram showing the configuration of the switch in the second embodiment.
• FIG. 10 is a block diagram showing the configuration of another switch in the second embodiment.
• FIG. 11 is a block diagram showing a configuration of a communication apparatus according to Embodiment 3 of the present invention.
• FIG. 2 is a block diagram showing a configuration of the fast Fourier transform circuit according to Embodiment 1 of the present invention.
• a fast Fourier transform circuit (hereinafter referred to as “FFT circuit”) 100 shown in FIG. 2 is a multimode fast Fourier transform circuit that can support a plurality of communication methods.
• FFT circuit a communication method that requires FFT processing of 2 N points (N is a natural number) and a communication method that requires FFT processing of 2 M points (M is a natural number, where M ⁇ N) are simultaneously performed.
• N- point FFT processing it is necessary to perform radix-2 butterfly computation processing in N stages.
• 2 M- point FFT processing it is necessary to perform radix-2 butterfly computation processing in M stages. .
• first FFT processing unit 110 includes a first FFT processing unit 110, a second FFT processing unit 120, a third FFT processing unit 130, a coefficient accumulation unit 140, and a control unit 150.
• the first FFT processing unit 110 includes the first buffer 111 and the first to first (M-1).
• the first FFT processing unit 110 applies the (M-1) stage (that is, the first stage (M-1) to the digital signal input to the first notch 111 and the second buffer 113. ) FFT processing is performed.
• the second FFT processing unit 120 includes (N—M + 1) data accumulation units 121—M to 121—N, from the first M force to the first N, and from the Mth to the Nth. (N—M + 1) butterfly operation units 122-M to 122-N. As a result, the second FFT processing unit 120 performs the first buffer processing.
• the (N ⁇ M + 1) -stage (ie, M-th to N-th) FFT processing is performed on the digital signal input to the first 111 and FFT processed by the first FFT processing unit 110.
• the third FFT processing unit 130 includes a second-M data storage unit 131 and a second-M butterfly calculation unit 132. As a result, the third FFT processing unit 130 performs a one-stage (that is, M-th) FFT on the digital signal input to the second buffer 113 and subjected to the FFT processing by the first FFT processing unit 110. Process.
• the first buffer 111 accumulates 2 N digital signals, and outputs the accumulated digital signals to the first to first data accumulation units 112-1 under the control of the control unit 150.
• the digital signal input to the first buffer 111 is rearranged to the bit reversal position obtained by reversing the order of the respective bits and output.
• the input digital signal is 0, 1, 2 ⁇ , 2 N — 2, 2 N — 1 in the order of bit reversal 0, 2 N " ⁇ ⁇ ⁇ ⁇ , 2 N_ 1 — 1, 2 N — 1 are converted and output.
• the second buffer 113 stores 2 M digital signals, and outputs the stored digital signals to the 2-1 data storage unit 114-1 under the control of the control unit 150.
• the digital signal input to the second buffer 113 is rearranged at the bit reversal position and output, as in the first buffer 111.
• the input digital signal is 0, 1, 2, ..., 2 M — 2, 2 M — 1 in the order of bit reversal 0, 2 M ⁇ ..., 2 M_1 — 1, 2 M —1 are converted and output.
• the first buffer 111 and the second buffer 113 are powers included in the first FFT processing unit 110, respectively.
• the present invention is not limited to this. Yes.
• Both the first buffer 111 and the second buffer 113 may be arranged outside the first FFT processing unit 110.
• the first FFT processing unit includes (M-1) data storage units 112-1 to 112- (M-1) and (M-1) data storage units 114 1 to 114. (M-1) and (M-1) butterfly computing units 115-1 to 115- (M-1).
• the 1-1st data storage unit 112-1 and the 2-1st data storage unit 114-1 each store 2 M_1 digital signals.
• the first In the fly computation unit 115-1 the first-stage radix-2 butterfly computation is performed on 2 M_1 accumulated digital signals.
• the result of the butterfly operation on the digital signal stored in the 1-1 data storage unit 112-1 is output to the 1-2 data storage unit 112-2.
• the result of the butterfly operation on the digital signal stored in the 2-1 data storage unit 114-1 is output to the 2-2 data storage unit 1142.
• the first butterfly calculation unit 115-1 includes a first data storage unit 112.
• the first radix-2 butterfly operation is executed using the coefficient input from the coefficient storage unit 140.
• the digital signal stored in the 2-1st data storage unit 114-1 is input as f (1, n).
• the coefficient used in the first butterfly computing unit 115-1 is the data storage of the 1-1.
• the digital signal stored in the product section 112-1 and the digital signal stored in the second data storage section 114-1 can be shared.
• FIG. 4 is a block diagram showing a configuration of the first butterfly computation unit 115-1 that executes the radix-2 butterfly computation.
• the first butterfly computing unit 115-1 includes four switches 161, 162, 163, 164, an adder 165, a subtractor 166, and a multiplier 167.
• the first butterfly computation unit 115-1 is controlled by the control unit 150 as shown in FIG.
• Each of the switches 161 to 164 is controlled to the H or L position by the control unit 150.
• the digital signal shown in (Equation 1) is output from the switch 163 as the result of the butterfly operation for the digital signal stored in the 1-1st data storage unit 112-1.
• the digital signal shown in (Equation 2) is output from switch 164.
• the digital signal shown in (Equation 3) is output from switch 163 as the result of the butterfly operation for the digital signal stored in the 2-1 data storage section 114-1.
• the digital signal shown in (Equation 4) is output from the switch 164.
• the (M-1) butterfly operation unit 115- (M-1) is connected to the first (M-1) data storage unit 112- (M-1) or the second -(M-1) data storage unit 114- (M-1) stage using the coefficients input from the coefficient storage unit 140 for 2 M_1 digital signals stored in (M-1). Perform a radix-2 butterfly operation of the eye.
• the digital signal stored in the first (M-1) data storage unit 112- (M-1) is represented by f (M)
• Equation 7 f (M— l, n) + W (M— l, n) X f (M— 1, n + 2 M_2 )... (Equation 7)
• Equation 8 f (M l, n) W (M l, n) X f (M—1, n + 2 M_2 )... (Equation 8)
• the second- (M-1) data storage unit 114-1 (M-1) stores the digital signal. f (M — l, n), where the input coefficient is W (M — l, n), the output digital signal
• k (M—1, ⁇ ) 2 ⁇ _ ( ⁇ _1 ) ⁇ (0, 1,..., 2 ⁇ _1 — 2, 2 M_1 — l), k (M— 1
• the coefficients used in the ( ⁇ -1) butterfly calculation unit 115- ( ⁇ -1) are stored in the first ( ⁇ -1) data storage unit 112- ( ⁇ -1).
• the digital signal stored in the second (M-1) data storage unit 114 (M-1) can be shared.
• the butterfly calculation result of the digital signal stored in the second (M-1) data storage unit 114-(M-1) is the second FFT data in the third FFT processing unit 130.
• the data is output to the storage unit 131.
• Data storage unit of the 1-M 121- Micromax accumulates 2 New number of digital signals.
• the N-th butterfly operation unit 122-N uses the coefficients input from the coefficient storage unit 140 for the 2 N digital signals stored in the 1-Nth data storage unit 121-N. Performs radix-2 butterfly operation in the Nth stage.
• the digital signal stored in the 1st-N data storage unit 121-N is f (N, n) and the input coefficient is W (N, n)
• the output digital signal is (Equation 13) and (Equation 14), and is output from the FFT circuit 100 as the final FFT processing result of the digital signal input to the first buffer 111.
• the second toe data storage unit 131 stores 2 ton digital signals.
• the radix-2 butterfly operation of the second stage is executed on the accumulated digital signals using the coefficient input from the coefficient accumulation unit 140.
• the output digital signal is the following (Equation 17) and (Equation 18).
• each of the shared butterfly computing units 115-1 to 115- ( ⁇ -1) can also use the coefficients used, so that the computation resources can be further optimized.
• the radix-2 butterfly operation is described as an example, but the radix of the butterfly operation is not limited to 2. It is possible to reduce the number of butterfly operations by performing butterfly operations using different radixes, such as radix 4 and radix 8, instead of radix 2.
• FIG. 5 is a block diagram showing a modification of the present embodiment.
• the FFT circuit 100a shown in FIG. 5 includes a second FFT processing unit 120a and a third FFT processing unit 130a.
• the second FFT processing unit 120a starts from the second FFT processing unit 120 in the first embodiment shown in FIG. 2 to the first-M data storage unit 121-M and the M-th butterfly computation unit 122-M. It has a configuration in which and are deleted.
• the third FFT processing unit 130a is the same as that in the first embodiment shown in FIG. In this configuration, the butterfly computation unit 132 is deleted from the third FFT processing unit 130 and a first-M data storage unit 171 and an Mth butterfly computation unit 172 are added.
• the 1st-M data storage unit 171 stores 2M digital signals, which are stored in the 1st-M data storage unit 171 and the 2nd-M data storage unit 131, respectively.
• the M-th butterfly computation unit 172 can be shared for digital signals.
• the result of the butterfly computation of the digital signal stored in the first M data storage unit 171 is output to the first— (M + 1) data storage unit 121— (M + 1) in the second FFT processing unit 120a. Is done. Also, the result of the digital signal butterfly operation stored in the second-M data storage unit 131 is output from the FFT circuit 100 as the final FFT processing result of the digital signal input to the second notch 113. .
• FIG. 6 is a block diagram showing another modification of the present embodiment.
• the second FFT processing units 120 and 120a perform pipeline-type FFT processing, whereas the memory-based FFT is used. This is when processing is performed. That is, the FFT circuit 100b shown in FIG. 6 has one data storage unit 181 and butterfly operation unit 182, respectively. As described above, the FFT circuit 100b shown in FIG. 6 differs from the FFT circuits 100 and 100a shown in FIGS. 2 and 5 in that it has only one data storage unit 181 and butterfly operation unit 182. .
• the data storage unit 181 stores 2 N digital signals.
• the butterfly calculation unit 182 uses the coefficients input from the coefficient storage unit 140 for the 2 N stored digital signals, and performs the M-th radix-2 butterfly calculation. Execute. The result of this notary operation is overwritten on the data storage unit 181 at any time. After that, the data overwriting of the data storage unit 181 and the butterfly operation for the overwritten digital signal are repeated.
• the digital signal output from the data storage unit 181 Is the FFT processing unit 100 as the FFT processing result of the digital signal input to the first buffer 111. Output from b.
• the configuration of FIG. 6 is applied to the configuration of FIG. 5, the radix-2 butterfly operation at the M + 1 first stage is executed.
• FIG. 7 is a block diagram showing still another modification example of the present embodiment.
• the first FFT processing unit has a switch. That is, in the FFT circuit 100c shown in FIG. 7, the first FFT processing unit (for example, the first FFT processing unit 110 shown in FIG. 2) further includes two switches 191 and 192. In this case, for example, when communication is not being performed using one of the two communication methods, the switch 191 is switched so that the first data storage unit 112 to the first data storage unit 112— 2 M_1 digital signals are stored in both 1 and 2-1 data storage unit 114 1, respectively, and 1st data storage unit 112-1 and 2-1 data storage unit 114 1 Can be regarded as a data accumulator that accumulates one 2M digital signal, and FFT processing can be performed at high speed.
• the switch 191 when communication is not being performed using one of the two communication methods, the switch 191 is switched so that the first data storage unit 112 to the first data storage unit 112— 2 M_1 digital signals are stored in both 1 and 2-1 data storage unit 114 1, respectively, and 1st data storage unit 112-1 and 2-1 data storage
• the first FFT processing unit when it is necessary to perform only one system of FFT processing, the first FFT processing unit performs (M ⁇ 1) stages of butterfly calculation processing. In other words, since twice the data area can be allocated to the butterfly computation in the first FFT processing section, the computation speed in the FFT circuit can be increased.
• FIG. 8 is a block diagram showing a configuration of a fast Fourier transform circuit according to Embodiment 2 of the present invention.
• the fast Fourier transform circuit (FFT circuit) 200 in FIG. 8 has the same basic configuration as the FFT circuit 100 shown in FIG. 2, and the same components are denoted by the same reference numerals and the description thereof is omitted. Is omitted.
• the feature of this embodiment is a maximum of 2 N points and 2 N_1 points, and an arbitrary number of FFs.
• It has a configuration capable of performing T processing.
• the FFT circuit 200 shown in FIG. 8 includes the first buffer 211 and the first to first N N data storage units 212-1 to 212-N, a second nother 213, and (N-1) data storage units 214 from the 2nd to the 2nd (N-1).
• the first buffer 211 stores up to 2 N digital signals, and outputs the stored digital signals to the first switch 216-1 under the control of the control unit 150a.
• the input digital signal is 0, 1,..., 2 N — 2, 2 N — 1, as shown in FIG. 3, as in the first notch 111 in the first embodiment.
• the sequence is converted into a sequence of 0, 2 N " ⁇ ⁇ , 2 N_1 — 1, 2 N — 1, which are rearranged in the bit reversal position, and output.
• the second buffer 213 stores a maximum of 2 N_1 digital signals, and outputs the stored digital signals to the first switch 216-1 under the control of the control unit 150a.
• the input digital signal is 0, 1,..., 2 N_1 — 2, 2 N_1 — 1, as shown in FIG. 3, as in the case of the second nother 113 in the first embodiment.
• the sequence is converted into a sequence of 0, 2 N_2 ,..., 2 N_2 — 1, 2 N — 1 — 1, which are rearranged in the bit reversal position, and output.
• the first switch 216-1 has two switches 221 and 222, and is controlled by the control unit 150a. That is, each of the switches 221 and 222 is controlled to the H or L position by the control unit 150a.
• the input signal from the first buffer 211 is output to the data storage unit 212-1 of the first-1 when the position force of the switch 221, and when the position of the switch 221 is H, the second switch 216 — Output to 2.
• the input signal from the second buffer 213 is output to the data storage unit 214-1 of the 2-1 when the position force of the switch 222 is present, and when the position of the switch 222 is H, the second switch 216 is input. — Output to 2.
• the 1st to 1st to 1st-N data storage units 212-1 to 212-N store 2 1 to 2N digital data.
• 1st to 1st to Nth data storage units 212-1 to 212- When 2 N digital signals are stored in N, the 1st to Nth butterfly operation units 215-1 to 21 5—N
• the radix-2 butterfly operation up to the first stage N-th stage is performed on the Si S accumulated digital signals using the coefficients input from the coefficient accumulation unit 140a.
• the data storage units 214-1 to 214-(N ⁇ 1) from the 2nd to the 1st to the 2nd (N ⁇ 1) store S sN ⁇ 1 digital data.
• each of the SS ⁇ 1 accumulated digital signals is used for one stage using the coefficients input from the coefficient storage section 140a.
• the radix-2 butterfly operation from the first to the (N-1) th stage is executed.
• the first to N-th butterfly computation units 215-1-215-N are similar to the butterfly computation unit in the first embodiment as shown in FIGS. 1—N data storage unit 212— 1 to 212—N or 2nd to 2nd (N—1) data storage units 214— 1 to 214— (N-1)
• the radix-2 butterfly operation up to the first stage force N stage is executed for each digital signal using the coefficients input from the coefficient accumulator 140a.
• the second to (N-1) th switches 216-2-216- (N-1) have four switches.
• the second switch 216-2 will be described as an example.
• the second switch 216-2 has four switches 231, 232, 233, and 234 as shown in FIG. 9 and is controlled by the ff3 ⁇ 4 control 150a. That is, the switches 231 to 234 are controlled to the H or L position by the control unit 150a.
• the first stage for the digital signal stored in the first data storage unit 212-1 in the first butterfly calculation unit 215-1 The result of the butterfly calculation is output to the first and second data storage sections 212-2 when the position force of switch 232 is applied, and is output to the third switch 216-3 when the position of switch 232 is H.
• the second butterfly computing unit 215-1 uses the second
• the result of the first butterfly operation on the digital signal stored in the data storage unit 214-1 of 1 is output to the data storage unit 214-2 of the 2nd-2 when the position force of the switch 234 is applied.
• the position of 234 is H, it is output to the third switch 216-3.
• the Nth switch 216-N has three switches 241, 242, and 243, and is controlled by the control unit 150a. That is, the switches 241 to 243 are connected to the control unit 15.
• the (N + 1) th switch 216— (N + 1) is output.
• the (N + 1) th switch 216— (N + 1) has one switch 251 and is controlled by the control unit 150a. That is, the switch 251 is controlled to the H or L position by the control unit 150a.
• the position of switch 251 is L
• the result power of the N-th butterfly operation for the digital signal stored in the 1st-N data storage unit 212-N in the N-th butterfly operation unit 215-N FFT Result of FFT processing of circuit 200 Is output.
• the position of the switch 251 is H, it is output as the FFT processing result of the input signal force FFT circuit 200 from the Nth switch 216-N.
• the first switch 216-1 sets all the two built-in switches 221 and 222 to the L position. Accordingly, the first switch 216-1 (1) outputs the input signal from the first buffer 211 to the first data storage unit 212-1, and (2) the second buffer 213. These input signals are controlled so as to be output to the 2-1st data storage unit 214-1.
• the second to (N-1) switches 216-2 to 216- (N-1) are all set to the L position of the four built-in switches 231 to 234, respectively. .
• the second to (N-1) th switches 216-2-216- (N-1) are respectively (1) first to (N-2) butterfly computing units 215-1-215.
• the first stage force for the digital signal stored in (N-2) data storage unit 212-1 to 212- (N-2) in (N-2) is also (N — 2) Output the result of the butterfly calculation in the first stage to the data storage unit 212—2 to 212_ (N_1) from the 1st-2 to the 1st (N-1), and (2) from the 1st to the 2nd ( N_ 2) butterfly calculation unit 215-1 to 215 — stored in (N-2) from 2nd to 1st to 2nd to (N 2) data storage units 214— 1 to 214- (N-2)
• the results of the first to (N ⁇ 2) th stage butterfly calculations on the digital signal are sent to the data storage units 214 ⁇ 2 to 214 ⁇ (N1) from the second to the second (N ⁇ 1). It is controlled to output.
• the Nth switch 216-N is set to the L position for all the three built-in switches 241-243.
• the Nth switch 216-N becomes (1) the first (N-1) data storage unit 212- (N— in the (N-1) butterfly operation unit 215- (N-1).
• the result of the (N—1) stage butterfly operation for the digital signal stored in 1) is output to the 1st—N data storage unit 212—N, and (2) the (N ⁇ 1) butterfly
• the result of the (N-1) stage butterfly operation for the digital signal stored in the second (N-1) data storage unit 214- (N-1) in the calculation unit 215- (N-1) It is controlled to output as the FFT processing result of the FFT circuit 200.
• the (N + 1) th switch 216— (N + 1) sets one built-in switch 251 to the L position.
• the (N + 1) -th switch 216— (N + 1) is the N-th stage for the digital signal stored in the first-N data storage unit 212-N in the N-th butterfly computation unit 215-N.
• the result of the butterfly operation is controlled so as to be output as the FFT processing result of the FFT circuit 200.
• the first switch 216-1 sets all the two built-in switches 221 and 222 to the L position. Accordingly, the first switch 216-1 (1) outputs the input signal from the first buffer 211 to the first data storage unit 212-1, and (2) the second buffer 213. These input signals are controlled so as to be output to the 2-1st data storage unit 214-1.
• the second to (N-1) switches 216-2 to 216- (N-1) are (i) switch 231 and switch 232, respectively, of the four built-in switches.
• switch 233 the 2nd to 6th switches 216-2 to 216-6 are in the L position, and the 7th to (N-1) switches 216—7 to 216— (N—1) is set to the H position.
• Switch 234 is set to 1 for the second to fifth switches 216-2 to 216-5. In the case of the 6th to (N-1) switches 216-6 to 216- (N-1), set them to the ⁇ position.
• the second to (N-1) th switches 216-2 to 216- (N-1) are respectively connected to (1) the first to (N-2) butterfly operation units 215-1 to 215—
• the first to first (N 2) data storage units 212-1 to 212- in (N-2) (N-2) from the first stage to the digital signals stored in (N-2) ) Outputs the result of the butterfly calculation in the first stage to the data storage unit 2 12-2 to 212- (N-1) from the 1st-2 to the 1st (N-1), and (2) from the 1st to the 1st 4 butterfly calculation units 215—1-2 15-15 4th to 2nd to 4th data storage units 214-1 to 214-4
• the result of the calculation is output from the second 2-2 to the second to fifth data storage units 214-2 to 214-5, and (3) the second to fifth data storage units 214 in the fifth butterfly calculation unit 215 5 — 5th stage butterfly performance for digital signal stored in 5
• switch 241 is set to the position
• switch 242 is set to the H position
• switch 243 is set to the H position.
• the N-th switch 216—N becomes (1) the first (N ⁇ 1) data storage unit 212— (N ⁇ 1) in the (N ⁇ 1) butterfly operation unit 215— (N 1).
• the (N + 1) th switch 216— (N + 1) sets one built-in switch 251 to the H position.
• the (N + 1) th switch 216— (N + 1) becomes the first (N ⁇ 1) data storage unit 212 in the (N ⁇ 1) butterfly operation unit 215— (N-1). — Control is performed so that the (N— 1) stage butterfly computation result for the digital signal stored in (N— 1) is output as the FFT processing result of the FFT circuit 200.
• the two switches 221 and 222 in the first switch 216-1 are all set to the H position, and among the four switches in the second switch 216-2, the switch 231 Set switch and switch 233 to the H position, and switch 232 and switch 234 to the L position.
• a radix-4 butterfly operation is performed on the digital signal stored in the first-second data storage unit 212-2 using the coefficient input from the coefficient storage unit 140a, and the calculation result is obtained as the first result.
• Output to -3 data storage unit 212-3 In addition, a radix-4 butterfly operation is performed on the digital signal stored in the 2-2 data storage unit 214-2 using the coefficient input from the coefficient storage unit 140a, and the result of the operation is calculated. 2 ⁇ 3 data storage unit 21 4 ⁇ Outputs to 3 ⁇ 3. In this way, by changing the number of butterfly operations used using the switch, butterfly operations can be performed with different radixes.
• the number of FFT processing points is arbitrarily switched using a switch. Can be executed simultaneously and can flexibly cope with a plurality of communication methods.
• FIG. 11 is a block diagram showing a configuration of a communication apparatus according to Embodiment 3 of the present invention.
• a case where the FFT circuit 100 of Embodiment 1 is applied to a communication device will be described.
• a communication device 300 shown in FIG. 11 includes a first antenna 310, a second antenna 312, a first receiving unit 320, a second antenna, in addition to the FFT circuit 100 of the first embodiment shown in FIG.
• a receiving unit 322, a first baseband signal processing unit 330, and a second baseband signal processing unit 332 are included.
• First receiving section 320 converts the radio frequency signal of the first radio system received by first antenna 310 into a digital signal and outputs the digital signal.
• the second receiving unit 322 converts the radio frequency signal of the second radio system received by the second antenna 312 into a digital signal and outputs it.
• the first wireless system is the DVB-H (Digital Video Broadcasting) system and the second wireless system is the IEEE 802.1 la system.
• DVB-H Digital Video Broadcasting
• the first buffer 111 stores 4096 digital signals
• the second buffer 113 stores 64 digital signals.
• the first FFT processing unit 110 includes first to first to fifth data storage units 112-1 to 112-5, second to second to fifth data storage units 11 4 1 to 114 5, and , First to fifth butterfly computing units 115-1 to 115-5.
• the second FFT processing unit 120 includes sixth to twelfth data storage units 121-6 to 121-12 and sixth to twelfth butterfly operation units 122-6 to 122-12.
• the third FFT processing unit 130 includes a 2-6th data storage unit 131 and a butterfly operation unit 132.
• FFT circuit 200 in the second embodiment can be used.
• the switch 222 in the first switch 216-1 is set to H.
• the digital signal stored in the second buffer 213 can be directly output from the FFT circuit 200 by setting the switch 243 in the switch 216-N to the H position. For this reason, it is possible to flexibly support communication methods that do not require FFT processing.
• the present invention has the effect of optimizing the computation resources while supporting a plurality of communication schemes, and is useful for a multimode communication apparatus that supports a plurality of communication schemes. Therefore, it is suitable for downsizing and power saving of the device.

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