WO2013057855A1 - 適応等化器 - Google Patents
適応等化器 Download PDFInfo
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- WO2013057855A1 WO2013057855A1 PCT/JP2012/004250 JP2012004250W WO2013057855A1 WO 2013057855 A1 WO2013057855 A1 WO 2013057855A1 JP 2012004250 W JP2012004250 W JP 2012004250W WO 2013057855 A1 WO2013057855 A1 WO 2013057855A1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L25/03159—Arrangements for removing intersymbol interference operating in the frequency domain
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
- G06F17/14—Fourier, Walsh or analogous domain transformations, e.g. Laplace, Hilbert, Karhunen-Loeve, transforms
- G06F17/141—Discrete Fourier transforms
- G06F17/142—Fast Fourier transforms, e.g. using a Cooley-Tukey type algorithm
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
- H04L25/03019—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
- H04L25/03057—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception with a recursive structure
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/01—Equalisers
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L2025/0335—Arrangements for removing intersymbol interference characterised by the type of transmission
- H04L2025/03375—Passband transmission
- H04L2025/03414—Multicarrier
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L2025/03433—Arrangements for removing intersymbol interference characterised by equaliser structure
- H04L2025/03535—Variable structures
- H04L2025/03541—Switching between domains, e.g. between time and frequency
Definitions
- the present invention relates to an adaptive equalizer that performs adaptive equalization processing on a time domain signal in the frequency domain.
- the ATSC Advanced Television Systems Committee
- OFDM Orthogonal Frequency Division Multiplexing
- Single carrier modulation generally performs adaptive equalization processing in the time domain.
- the adaptive equalization process in the time domain requires a convolution operation in the filter process and the coefficient update process, and the circuit scale increases as the number of taps increases.
- Patent Document 1, Patent Document 2, and Non-Patent Document 1 there is a technique for performing adaptive equalization processing on a time domain signal in the frequency domain instead of the time domain.
- the techniques described in Patent Document 1, Patent Document 2, and Non-Patent Document 1 (hereinafter referred to as “prior art”) perform adaptive equalization processing after converting a time domain signal into a frequency domain signal by fast Fourier transform. Do. Further, in the conventional technique, the frequency domain signal after the adaptive equalization processing is converted into a time domain signal by inverse fast Fourier transform. In such a single-carrier modulation signal receiving apparatus using the conventional technique, it is possible to improve reception performance while suppressing an increase in circuit scale.
- the conventional technique has a problem that the operation clock frequency required for the adaptive equalizer becomes high when the number of taps required is large or when it is necessary to perform reception processing at high speed.
- the operation clock frequency when the operation clock frequency is increased, the power consumption of the adaptive equalizer is increased, and there is a problem in that it becomes troublesome when mounted on an FPGA (Field-Programmable-Gate-Array). Therefore, it is desirable that an adaptive equalizer that performs adaptive equalization processing for a signal in the time domain in the frequency domain can suppress an increase in circuit scale and an increase in operating clock frequency as much as possible.
- An object of the present invention is to provide an adaptive equalizer that can suppress an increase in circuit scale and an operation clock frequency in an adaptive equalizer that performs an adaptive equalization process on a time domain signal in a frequency domain. is there.
- the adaptive equalizer of the present invention has a signal conversion unit that performs at least one of fast Fourier transform and inverse fast Fourier transform in an adaptive equalizer that performs adaptive equalization processing on a signal in the time domain in the frequency domain.
- the signal conversion unit includes a memory capable of reading and writing signals of 2M (M is a natural number) samples, 2M registers accessible to the memory, M butterfly operation units, and the 2M registers And a switching control unit that switches a connection state between the M butterfly computation units.
- an increase in circuit scale and an increase in operating clock frequency can be suppressed.
- FIG. 1 is a block diagram showing a configuration of an adaptive equalizer according to Embodiment 1 of the present invention.
- the chart figure which shows an example of the processing timing of each signal conversion part in Embodiment 1 of this invention
- the block diagram which shows the 1st example of a structure of the signal conversion part which concerns on Embodiment 1 of this invention.
- the block diagram which shows the 2nd example of a structure of the signal conversion part which concerns on Embodiment 1 of this invention.
- the block diagram which shows the 3rd example of a structure of the signal conversion part which concerns on Embodiment 1 of this invention.
- the block diagram which shows the 1st example of a structure of the adaptive equalizer which concerns on Embodiment 2 of this invention.
- FIG. 5 is a block diagram showing an example of a configuration of a time domain filter according to Embodiment 2 of the present invention.
- the block diagram which shows an example of a structure of the periphery of the butterfly calculating part in Embodiment 2 of this invention The block diagram which shows the 1st example of a structure of the register periphery in Embodiment 2 of this invention.
- FIG. 7 is a block diagram showing a second example of the configuration of the adaptive equalizer according to Embodiment 2 of the present invention.
- Block diagram showing the configuration of an adaptive equalizer according to Embodiment 4 of the present invention Block diagram showing a configuration of a time domain filter according to the fourth embodiment of the present invention.
- FIG. 1 is a block diagram showing a configuration of an adaptive equalizer according to Embodiment 1 of the present invention.
- the adaptive equalizer 100 includes an accumulation unit 101, an inter-block connection unit 102, a first fast Fourier transform unit (hereinafter referred to as “FFT unit”) 103, a complex conjugate unit 104, and a first multiplication.
- the adaptive equalizer 100 includes a first inverse fast Fourier transform unit (hereinafter referred to as “IFFT unit”) 106, a block extraction unit 107, a determination unit 108, an error extraction unit 109, and a first zero insertion unit 110. And a second FFT unit 111.
- IFFT unit first inverse fast Fourier transform unit
- the adaptive equalizer 100 includes a second multiplier 112, a second IFFT unit 113, a second zero insertion unit 114, a third FFT unit 115, a third multiplier 116, and a first adder. 117 and a first delay unit 118.
- the storage unit 101 receives time domain signals and sequentially stores a predetermined block size.
- the inter-block connection unit 102 connects the block stored in the storage unit 101 and the latest block and outputs the result.
- the first FFT unit 103 performs a fast Fourier transform on the output of the inter-block coupling unit 102 and outputs the obtained signal.
- the complex conjugate unit 104 outputs the complex conjugate of the first FFT unit 103.
- the first multiplier 105 multiplies the output of the first FFT unit 103 and the output of the first delay unit 118 described later (adaptive equalizer coefficient converted to the frequency domain), and uses the obtained signal. Output.
- the first IFFT unit 106 performs inverse fast Fourier transform on the output of the first multiplier 105, and outputs the obtained signal.
- the block extraction unit 107 extracts the latest signal sequence block from the output of the first IFFT unit 106 and outputs it.
- the determination unit 108 outputs a determination result for the output of the block extraction unit 107.
- the error extraction unit 109 Based on the output of the determination unit 108, the error extraction unit 109 extracts an error from the ideal signal point from the output of the block extraction unit 107 (that is, the output of the first IFFT 106), and outputs the extracted error.
- the first zero insertion unit 110 receives the error extracted by the error extraction unit 109, zeros a portion other than the desired tap coefficient in the error series, and outputs the obtained signal.
- the second FFT unit 111 performs a fast Fourier transform on the output of the first zero insertion unit 110 and outputs the obtained signal.
- the second multiplier 112 multiplies the output of the complex conjugate unit 104 (that is, the complex conjugate of the output of the first FFT unit 103) and the output of the second FFT unit 111, and outputs the obtained signal.
- the second IFFT unit 113 performs an inverse fast Fourier transform on the multiplication result of the second multiplier 112 and outputs the obtained signal.
- the second zero insertion unit 114 sets a portion other than the desired tap coefficient among the outputs of the second IFFT unit 113 to zero, and outputs the obtained signal.
- the third FFT unit 115 performs a fast Fourier transform on the output of the second zero insertion unit 114 and outputs the obtained signal.
- the adaptive equalizer 100 arranges the second IFFT unit 113, the second zero insertion unit 114, and the third FFT unit 115 in the subsequent stage of the second multiplier 112.
- the adaptive equalizer 100 can remove the influence caused by Fourier transform of a discontinuous signal.
- these parts have a function to return the multiplication result of the error sequence and the input signal in the frequency domain to the time domain, and to convert the invalid part as a tap coefficient to zero, and then convert it to the frequency domain again. is doing.
- the third multiplier 116 multiplies the output of the third FFT unit 115 by a predetermined coefficient ⁇ and outputs the obtained signal.
- the first adder 117 adds the output of the third multiplier 116 and the output of the first delay unit 118 in the subsequent stage, and outputs the obtained signal.
- the first delay unit 118 delays the output of the first adder 117 and outputs it to the first multiplier 105 as an adaptive equalizer coefficient converted to the frequency domain.
- the first adder 117 and the first delay unit 118 function as an accumulating unit that accumulates the output of the third multiplier 116.
- the complex conjugate unit 104 and the part from the determination unit 108 to the first delay unit 118 function as the first coefficient update unit 120 in the adaptive equalizer 100.
- the adaptive equalizer 100 can perform the adaptive equalization processing for the time domain signal in the frequency domain instead of the time domain.
- the received signal when the received signal is a television broadcast signal, the received signal must be processed within real time in order to continuously view the broadcast without interruption. That is, all the operations executed by the adaptive equalizer 100 need to be completed within the block size time.
- the fast Fourier transform / inverse fast Fourier transform is performed at five locations of the first to third FFT units 103, 111, 115 and the first and second IFFT units 106, 113.
- these fast Fourier transform / inverse fast Fourier transform a part of the computation processing is executed in parallel, thereby reducing the number of necessary computations and shortening the time required for computation processing of the adaptive equalizer 100. Is possible. Therefore, the adaptive equalizer 100 may execute the fast Fourier transform / inverse fast Fourier transform operation that can be performed in parallel, in parallel.
- a system from the inter-block connecting unit 102 to the first multiplier 105 through the complex conjugate unit 104 is referred to as an A system.
- a system from the first multiplier 105 to the second multiplier 112 of the A system through the determination unit 108 is referred to as a B system.
- the arithmetic processing of the first FFT unit 103 is processing A-1
- the arithmetic processing of the second IFFT unit 113 is processing A-2
- the arithmetic processing of the third FFT unit 115 is processing.
- A-3 the arithmetic processing of the first IFFT unit 106 is represented as processing A-4.
- the calculation process of the second FFT unit 111 is represented as process B-1.
- the first to third FFT units 103, 111, and 115, and the first and second IFFT units 106 and 113 are collectively referred to as “signal conversion units” as appropriate.
- FIG. 2 is a chart showing an example of processing timing of each signal conversion unit of the adaptive equalizer 100.
- Process A-1 and process B-1 are not dependent on each other.
- the adaptive equalizer 100 is provided with two systems for performing fast Fourier transform / inverse fast Fourier transform arithmetic processing. For example, as shown in FIG. 2, processing A-1 and processing B-1 are performed in parallel. Execute. As a result, the adaptive equalizer 100 can reduce the time required for one fast Fourier transform / inverse fast Fourier transform operation.
- the process A-2 depends on the process data of the process B-1, and the process B-1 must be completed before the start timing. Therefore, as shown in FIG. 2, the adaptive equalizer 100 needs to complete the processes A-1 to A-4 within the block size for the A system.
- the adaptive equalizer 100 reduces the calculation time of the fast Fourier transform / inverse fast Fourier transform required for each block size to four times even if the number is increased to three or more due to the dependency of the signal processing data. It cannot be reduced to less than the time.
- the calculation time of the block size is about 38.65 ⁇ sec. . Therefore, in the ATSC standard, the 1024-point fast Fourier transform / inverse fast Fourier transform must be performed a total of 5 times (4 times in the above example) in about 38.65 ⁇ sec. Even if processing time other than the fast Fourier transform / inverse fast Fourier transform is ignored, the calculation process of one fast Fourier transform / inverse fast Fourier transform is completed within 7.73 ⁇ sec (in the above example, 9.66 ⁇ sec). There must be.
- the assumed application system must support a long delay multipath of 40 ⁇ sec or more, and requires at least 500 taps or more.
- the adaptive equalizer can reduce the number of cycles by configuring a plurality of butterfly operation circuits in parallel and combining them with a multi-port memory.
- the circuit scale increases, and a memory corresponding to the number of ports exceeding 10 ports is generally not used, and there are restrictions on the use.
- the memory can be replaced with a register, but the circuit scale also increases.
- the adaptive equalizer 100 is configured such that a circuit is configured with registers that are not limited to simultaneous access, and the utilization of a single port memory is realized.
- a memory as means for holding digital data having the same capacity can be realized with an area of a fraction of that of a register.
- the adaptive equalizer 100 according to the present embodiment increases the circuit scale by using a memory capable of reading and writing a plurality of signal samples and a plurality of registers accessible to each signal conversion unit. Can be suppressed.
- FIG. 3 is a block diagram showing a first example of the configuration of the signal conversion unit according to the present embodiment.
- the signal conversion units are the first to third FFT units 103, 111, and 115 and the first and second IFFT units 106 and 113 shown in FIG.
- each operation stage performed by the fast Fourier transform / inverse fast Fourier transform is simply referred to as a “stage”.
- the signal converter 200 includes a first wide bit memory 201, a first register group 202, a first connection switching unit 203, a butterfly operation unit group 204, a second connection switching unit 205, a second register group 206, And a second wide bit memory 207.
- the first wide bit memory 201 and the second wide bit memory 207 are memories having a large word size capable of reading and writing signals (data) of M samples (2 M samples for two times).
- the order of data held in the first wide bit memory 201 and the second wide bit memory 207 is the same as the order of data read by the normal fast Fourier transform / inverse fast Fourier transform operation.
- the first wide bit memory 201 and the second wide bit memory 207 collectively store the data for M samples at one address.
- the first register group 202 is composed of 2M registers each capable of accessing the first wide bit memory 201.
- the first register group 202 accesses the first wide bit memory 201 twice, thereby performing simultaneous access in which 2M samples are substantially parallelized.
- the first connection switching unit 203 switches the connection state between the first register group 202 and the butterfly operation unit group 204 (hereinafter referred to as “connection state on the first register group 202 side”).
- the butterfly computation unit group 204 is composed of M butterfly computation units, each performing a butterfly computation.
- connection state on the second register group 206 side switches the connection state between the butterfly computation unit group 204 and the second register group 206 (hereinafter referred to as “connection state on the second register group 206 side”).
- the second register group 206 is composed of 2M registers each capable of accessing the second wide bit memory 207.
- the second register group 206 accesses the second wide bit memory 207 twice to perform simultaneous access in which 2M samples are substantially parallelized.
- the operation clock frequency required for memory access of the first register group 202 and the second register group 206 is twice the operation clock frequency of the butterfly operation unit group 204.
- the first register group 202 and the second register group 206 need to perform memory access 2 ⁇ (1024 / M) times to complete one stage.
- the first connection switching unit 203 and the second connection switching unit 205 must appropriately control switching of the connection state between each register and each butterfly calculation unit every two memory accesses. Don't be.
- the first connection switching unit 203 and the second connection switching unit 205 have an output memory, an input memory, and a role of the first wide bit memory 201 and the second wide bit memory 207, respectively.
- the first connection switching unit 203 and the second connection switching unit 205 change the connection state on the first register group 202 side and the connection state on the second register group 206 side to appropriate states.
- the appropriate state is a state in which a signal is input from each appropriate register to each butterfly operation unit and a signal is output from each appropriate register from each butterfly operation unit.
- the butterfly calculation unit group 204 sequentially performs the calculation of each stage according to the switching of the connection state.
- the traveling direction of the signal is switched to the left and right for each stage. That is, when 10 stages of computation are required, for example, the signal advances in the right direction in FIG. 3 in the first stage, and the signal advances in the left direction in FIG. 3 in the next second stage.
- the signal processing unit 200 FFT unit / IFFT unit
- the signal processing unit 200 can prevent an increase in circuit scale by switching the signal traveling direction for each stage and using the circuit repeatedly.
- the signal conversion unit (FFT unit / IFFT unit) 200 can realize reception processing in real time at a low operation clock frequency while avoiding the use of multi-ports whose circuit scale increases.
- the signal converter 200 may use a two-bank wide bit memory.
- FIG. 4 is a block diagram illustrating a second example of the configuration of the signal conversion unit 200.
- the signal conversion unit 200 includes wide bit memories 201a and 201b and register groups 202a and 202b instead of the first wide bit memory 201 and the first register group 202 of FIG. .
- the signal conversion unit 200 includes wide bit memories 207a and 207b and register groups 206a and 206b instead of the second wide bit memory 207 and the second register group 206 of FIG.
- the wide bit memories 201a, 201b, 207a, and 207b each store data for M samples in one address, and the address space is 1024 / 2M.
- the register groups 202a, 202b, 206a, and 206b sequentially access the wide bit memories 201a, 201b, 207a, and 207b, respectively.
- the signal conversion unit 200 can reduce the number of memory accesses by configuring a wide bank memory of two banks. That is, the number of memory accesses required 2 ⁇ (1024 / M) times in the case of one bank configuration (see FIG. 3) is reduced to half. Therefore, the operation clock frequency of the register group can be the same as that of the butterfly operation unit, and can be half that of the configuration shown in FIG. In other words, in the memory access operation, in the case of the one-bank configuration, twice the clock frequency of the butterfly operation unit is required, but in the case of the two-bank configuration, the clock frequency may be maintained as one time.
- the signal conversion unit 200 Even if the signal conversion unit 200 has a one-bank configuration, if a dual port that can access any two addresses at the same time is adopted, the signal conversion unit 200 should remain at a single clock frequency as in the two-bank configuration. Is possible. However, the circuit size of the dual port configuration increases as the number of ports increases. On the other hand, the two-bank configuration is a configuration that cannot access addresses across banks, and an increase in circuit scale with respect to the one-bank configuration is negligible.
- the signal conversion unit 200 has a two-bank configuration as shown in FIG. 4, thereby avoiding the use of multi-ports with an increased circuit scale and performing reception processing in real time at a lower operating clock frequency. It can be realized.
- each butterfly computation unit needs to acquire an appropriate value for each stage for the rotor necessary for the butterfly computation. 3 and 4, it is assumed that each butterfly calculation unit stores a rotor, but a rotor memory storing the rotor of each stage may be arranged outside the butterfly calculation unit. .
- FIG. 5 is a block diagram illustrating a third example of the configuration of the signal conversion unit 200.
- the signal conversion unit 200 includes a rotor wide bit memory 208 and a rotor register group 209 in addition to the configuration of FIG. 3. Note that the butterfly computation unit group 204 shown in FIG. 5 does not hold a rotor.
- the rotor wide bit memory 208 is a memory having a large word size capable of reading and writing signals (data) for M rotors.
- the rotor wide bit memory 208 has an address assigned to each stage, and stores a rotor in each stage in advance.
- the rotator register group 209 includes M registers each capable of accessing the rotator wide bit memory 208. That is, the rotator register group 209 performs simultaneous access to the rotator wide bit memory 208 by parallelizing M rotators. Then, the rotator register group 209 reads M corresponding rotators from the rotator wide bit memory 208 for each stage, and passes them to an appropriate butterfly operation unit of the butterfly operation unit group 204.
- the signal conversion unit 200 does not need to provide a memory for holding the rotor for each butterfly operation unit, and can further reduce the circuit scale.
- the adaptive equalizer 100 includes the signal conversion unit 200 using a memory having a large word size and a plurality of registers for accessing the memory. Thereby, the adaptive equalizer 100 can suppress an increase in circuit scale and an increase in operation clock frequency.
- the signal conversion unit 200 in order to perform the rearrangement in the bit reverse relationship, it does not fit in the closed process only in the sample to be read together, and the data read from other addresses Sorting is necessary. That is, in order to rearrange the bit reverse relationship, a temporary holding register only for rearrangement must be added, and the number of cycles increases because memory access increases.
- the entire adaptive equalizer 100 according to the present embodiment, the condition that an inverse fast Fourier transform is always performed on a fast Fourier transform once performed.
- each signal conversion unit 200 of the adaptive equalizer 100 according to the present embodiment is configured not to perform bit reverse.
- the adaptive equalizer 100 may have a configuration in which butterfly computing units 204 provided for each stage are connected in series.
- the first connection switching unit 203 and the second connection switching unit 205 are not necessary, but the circuit scale can be increased as compared with the configuration of FIG.
- a decision feedback type feedback filter (hereinafter referred to as “time domain filter”) by time domain processing is arranged, and the multiplier and register of the signal conversion unit are replaced with the multiplier and register of the time domain filter. This is an example of sharing.
- FIG. 6 is a block diagram showing a first example of the configuration of the adaptive equalizer according to the present embodiment, and corresponds to FIG. 1 of the first embodiment.
- the same parts as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.
- the first coefficient updating unit 120a of the adaptive equalizer 100a includes a time domain filter 131a and a second adder 132a in addition to the configuration shown in FIG.
- the time domain filter 131a is a transversal filter, which receives the output of the determination unit 108 and the output of the error extraction unit 109, and outputs a time domain feedback signal.
- the second adder 132a adds the output of the block extraction unit 107 and the feedback signal that is the output of the time domain filter 131a, and outputs the obtained signal. Note that the determination unit 108 and the error extraction unit 109 receive not the output of the block extraction unit 107 but the output of the second adder 132a.
- FIG. 7 is a block diagram showing an example of the configuration of the time domain filter 131a.
- the time domain filter 131a includes a filter calculation unit 310a and a second coefficient update unit 320a.
- the filter operation unit 310a has N tap coefficients, and includes N multipliers 311a, N registers 312a, an adder 313a, and the like.
- the tap coefficients (wb 0 , wb 1 , wb 2 , wb 3 ,..., Wb N ⁇ 1 ) in the filter calculation unit 310 a are coefficients obtained by the second coefficient update unit 320 a.
- the second coefficient updating unit 320a includes N multipliers 321a, N step size coefficient ( ⁇ ) multipliers 322a, N adders 323a, N registers 324a, and the like.
- the second coefficient updating unit 320a operates as an adaptive filter and obtains tap coefficients (wb 0 , wb 1 , wb 2 , wb 3 ,..., Wb N ⁇ 1 ) in the filter calculation unit 310a.
- the adaptive equalizer 100a having the above configuration can perform adaptive equalization processing even in the time domain, and can further improve the reception performance.
- signals are input to the time domain filter 131a in units of block sizes.
- the adaptive equalization process in the frequency domain and the adaptive equalization process in the time domain can be executed in parallel.
- adaptive equalizer 100a uses a part of a circuit used in adaptive equalization processing in the frequency domain and adaptive equalization processing in the time domain.
- a part of the circuit can be shared.
- the adaptive equalizer 100a includes a multiplier (not shown in FIG. 3) of each butterfly operation unit of the signal conversion unit 200 (see FIG. 3), a multiplier 311a and a multiplier 321a of the time domain filter 131a. Can be shared.
- the adaptive equalizer 100a can share the first and second register groups 202 and 206 of the signal conversion unit 200 (see FIG. 3) and the registers 312a and 324a of the time domain filter 131a. .
- FIG. 8 is a block diagram showing an example of the configuration around the butterfly computation unit.
- the butterfly operation unit 410a includes two adders 411a and 412a and a multiplier 413a arranged on the output side of one adder 412a for multiplying the rotor.
- the butterfly operation unit 410a further includes a first switching unit 414a between the adder 412a and the multiplier 413a.
- the signal conversion unit (not shown) has a second switching unit 430a disposed between the rotor register 420a holding the rotor and the multiplier 413a, and the third switching unit 430a is connected to the output side of the multiplier 413a.
- the switching unit 440a is arranged.
- the signal conversion unit includes a control unit 450a that controls switching of connection states of the first to third switching units 414a, 430a, and 440a.
- the first switching unit 414a switches one input of the multiplier 413a between the output of the adder 412a and the output of a calculation unit other than the signal conversion unit (hereinafter referred to as “other calculation unit”). It has become.
- the second switching unit 430a switches the other input of the multiplier 413a between the output of the rotator register 420a and the output of another arithmetic unit.
- the third switching unit 440a is configured to switch the output destination of the multiplier 413a between the connection switching unit of the signal conversion unit and another arithmetic unit.
- the control unit 450a controls the first to third switching units 414a, 430a, and 440a so that the normal connection of the butterfly computation unit 410a is established. . That is, the control unit 450a causes the multiplier 413a of the butterfly calculation unit 410a to be used for calculation processing of fast Fourier transform / inverse fast Fourier transform.
- the control unit 450a causes the first to third switching units 414a, 430a, 440a to be connected in reverse to the normal connection.
- the control unit 450a includes the first to third switching units 414a, so that the multiplier 413a of the butterfly calculation unit 410a functions as, for example, the multipliers 311a and 321a (see FIG. 7) of the time domain filter 131a. 430a and 440a are controlled.
- FIG. 9 is a block diagram showing a first example of the configuration around the register.
- the register group arrangement unit 500a includes a register input side switching unit group 510a, a register group 520a, a register output side switching unit group 530a, and a control unit 540a.
- the register group 520a corresponds to the first and second register groups 202 and 206 (see FIG. 3) of the signal conversion unit 200 described in the first embodiment.
- the register input side switching unit group 510a includes 2M register input side switching units 511a arranged one-to-one on the input side of the 2M registers 521a of the register group 520a.
- the register output side switching unit group 530a includes 2M register output side switching units 531a arranged one-to-one on the output side of each register 521a of the register group 520a.
- One of the register input side switching units 511a switches the input of the corresponding register 521a between the signal conversion unit 200 (see FIG. 3) and the determination unit 108 (see FIG. 6). Then, the other register input side switching unit 511a switches the input of the corresponding register 521a between the signal conversion unit 200 (see FIG. 3) and the output of the register 521a adjacent to the corresponding register 521a.
- the register output side switching unit 531a sets the output destination of the corresponding register 521a to the signal conversion unit 200 (see FIG. 3) and the input side of the register 521a adjacent to the corresponding register 521a (the input side of the register input side switching unit 511a). ).
- the control unit 540a controls the register input side switching unit group 510a and the register output side switching unit group 530a so that the register group 520a is normally connected. To do. That is, in the control unit 540a, the register group 520a is used for fast Fourier transform / inverse fast Fourier transform arithmetic processing.
- the control unit 540a controls the register input side switching unit group 510a and the register output side switching unit group 530a so that the connection is the reverse of the normal connection. To do. Specifically, the control unit 540a connects adjacent registers 521a so that the entire register group 520a functions as a shift register. The control unit 540a controls the register input side switching unit group 510a and the register output side switching unit group 530a so that the register group 520a functions as the register 312a (see FIG. 7) of the filter operation unit 310a of the time domain filter 131a. To do.
- FIG. 10 is a block diagram showing a second example of the configuration around the register, and corresponds to FIG.
- the same parts as those in FIG. 9 are denoted by the same reference numerals, and description thereof will be omitted.
- each register input side switching unit 511a receives the input of the corresponding register 521a from the signal conversion unit 200 (see FIG. 3) and the adder 323a of the second coefficient update unit 320a of the time domain filter 131a (see FIG. 10). 7).
- the register output side switching unit 531a determines the output destination of the corresponding register 521a as the signal conversion unit 200 (see FIG. 3), the adder 323a of the second coefficient update unit 320a, and the multiplier 311a of the filter operation unit 310a (FIG. 7).
- control unit 550a controls the register input side switching unit group 510a and the register output side switching unit group 530a so as to achieve the above-described normal connection.
- the control unit 550a controls the register input side switching unit group 510a and the register output side switching unit group 530a so that the connection is reverse to the normal connection. To do.
- the control unit 550a includes a register input side switching unit group 510a and a register output side switching unit group so that the register group 520a functions as the register 324a (see FIG. 7) of the second coefficient updating unit 320a of the time domain filter 131a. 530a is controlled.
- the register 324a of the second coefficient updating unit 320a needs to hold past coefficient values. Therefore, as in this embodiment, when the register of the signal conversion unit and the register 324a of the second coefficient update unit 320a are shared, the register data is stored in the memory before switching, and the switching is performed. It is necessary to read data from the memory again later.
- the register input side switching unit 511a further has a memory value reading unit (not shown) of a coefficient value memory for holding past coefficient values on the input side of the corresponding register 521a. Switch to the output side of and connect. Further, the register output side switching unit 531a further switches and connects the output side of the corresponding register 521a to a memory writing unit (not shown) of the coefficient value memory. Then, the control unit 560a performs the same control as the above-described control unit 550a. Further, the control unit 560a sets the register input side switching unit group 510a and the register output side switching unit group 530a so that the coefficient values are read from and written to the coefficient value memory in the calculation process of the time domain filter 131a. Control.
- the adaptive equalizer 100a can improve the reception performance while suppressing an increase in circuit scale.
- the frequency of feedback in the time domain (coefficient update frequency of the time domain filter 131a) is the same as the frequency of feedback in the frequency domain (coefficient update frequency of the first coefficient update unit 120a in FIG. 6) for each block size. It is good also as a ratio once. In this case, the second coefficient updating unit 320a of the time domain filter 131a is not necessary.
- FIG. 12 is a block diagram showing a second example of the configuration of the adaptive equalizer 100a, and corresponds to FIG.
- the same parts as those in FIG. 6 are denoted by the same reference numerals, and description thereof will be omitted.
- the adaptive equalizer 100a shown in FIG. 12 does not include the second coefficient update unit 320a described in FIG. 7 in the time domain filter 131a. Then, as shown in FIG. 12, the adaptive equalizer 100a replaces the second coefficient updating unit 320a with a fourth FFT unit 141a, a fourth multiplier 142a, a third IFFT unit 143a, and a fifth Multiplier 144a, third adder 145a, and second delay unit 146a.
- the fourth FFT unit 141a performs a fast Fourier transform (transformation to the frequency domain) on the output (feedback signal after determination) of the determination unit 108, and outputs the obtained signal.
- the fourth multiplier 142a multiplies the output of the second FFT unit 111 and the output of the fourth FFT unit 141a, and outputs the obtained signal.
- the third IFFT unit 143a performs inverse fast Fourier transform (transformation into the time domain) on the output (error component from the determination value) of the fourth multiplier 142a, and outputs the obtained signal.
- the fifth multiplier 144a multiplies the output of the third IFFT unit 143a and the coefficient update step size ( ⁇ ), and outputs the obtained signal.
- the third adder 145a adds the output of the fifth multiplier 144a and the output of the second delay unit 146a in the subsequent stage, and outputs the obtained signal.
- the second delay unit 146a delays the output of the third adder 145a and outputs it to the time domain filter 131a as an adaptive equalizer coefficient converted to the time domain.
- the third adder 145a and the second delay unit 146a function as an accumulating unit that accumulates the output of the fifth multiplier 144a.
- the adaptive equalizer 100a can reduce the number of multipliers and registers necessary for the transversal filter even when the feedback unit must have a large number of coefficients. Can be reduced.
- the third embodiment of the present invention is an example in which the wide bit memory of the signal conversion unit is shared with the memory of another device unit.
- the OFDM demodulator (multi-carrier demodulator)
- the number of fast Fourier transform operations required for basic demodulation processing is only one, and there is a feedback system that requires adaptive processing. No.
- the OFDM demodulator can perform arithmetic processing by a plurality of circuits simultaneously in a pipeline manner, and real-time processing is possible without using the configuration of the signal converter of the present invention.
- the OFDM demodulator requires relatively complicated memory access using regularly arranged scattered pilot signals for channel estimation and the like. That is, a memory having a large word size is a memory essential for the OFDM demodulator.
- reception processing of the OFDM demodulator and the reception processing of the ATSC demodulator do not necessarily have to be performed simultaneously.
- the memory essential to the OFDM demodulator is shared with the memory of the adaptive equalizer 100, so that the entire apparatus by adding the adaptive equalizer 100 can be reduced. It is conceivable to suppress an increase in circuit scale.
- the OFDM demodulator is a method of converting a time domain signal into a frequency domain signal by fast Fourier transform and equalizing based on a channel estimation value. Therefore, the configuration of the OFDM demodulator is significantly different from that of the adaptive equalizer, and there are few parts common to these. For this reason, when realizing a circuit that can handle both the ATSC system and the OFDM system, a large area is conventionally required, and an increase in cost is inevitable.
- the receiving apparatus employing the adaptive equalizer 100 according to the present embodiment can reduce the circuit scale of a circuit that can handle both the ATSC system and the OFDM system by sharing the memory. Is possible.
- FIG. 13 is a block diagram showing a first example of the configuration around the memory according to the present embodiment.
- the adaptive equalizer (not shown) according to the present embodiment includes an address conversion unit 620b, a serial / parallel conversion unit 630b, a parallel / serial conversion unit 640b, and an ATSC / OFDM switching unit 650b.
- an address conversion unit 620b a serial / parallel conversion unit 630b, a parallel / serial conversion unit 640b, and an ATSC / OFDM switching unit 650b.
- the wide bit memory 610b corresponds to the first wide bit memory 201 and the second wide bit memory 207 (see FIG. 3) described in the first embodiment.
- the wide bit memory 610b reads / writes data according to these signals.
- the address conversion unit 620b inputs the address signal as it is to the wide bit memory 610b without conversion in the ATSC mode in which the operation for ATSC is performed.
- the address conversion unit 620b shifts the address signal to the right by Log 2 (M) bits and inputs only the upper bits to the wide bit memory 610b in the OFDM mode in which the operation for OFDM is performed.
- the address conversion unit 620b inputs the bits truncated by the right shift to the serial / parallel conversion unit 630b and the parallel / serial conversion unit 640b. That is, the serial / parallel converter 630b and the parallel / serial converter 640b are designated as to which position of the data held together for M samples.
- the serial / parallel converter 630b inputs the input data as it is to the wide bit memory 610b without conversion.
- the serial / parallel converter 630b In the OFDM mode, the serial / parallel converter 630b overwrites only the data at the position specified by the address converter 620b with the input data in the wide bit memory 610b. At this time, it is necessary to rewrite the data at other positions not specified as they are. For this reason, the serial / parallel converter 630b once reads the data at the designated address, and overwrites only the data at the designated position among the read data for M samples and writes it back.
- the parallel / serial conversion unit 640b uses the data for M samples output from the wide bit memory 610b as output data without conversion.
- the parallel / serial conversion unit 640b extracts only the data at the position specified by the address conversion unit 620b from the data for M samples output from the wide bit memory 610b, and outputs the data as output data. To do.
- the ATSC / OFDM switching unit 650b switches the ATSC mode / OFDM mode to the address conversion unit 620b, the serial / parallel conversion unit 630b, and the parallel / serial conversion unit 640b.
- the adaptive equalizer can share a wide bit memory between the ATSC system and the OFDM system. That is, the adaptive equalizer according to the present embodiment realizes a small demodulator that supports multimode by using the memory of the OFDM demodulator for demodulation of a single carrier system such as ATSC. Can do.
- the adaptive equalizer (not shown) according to the present embodiment further includes an M counter 660b as a data input / output unit of the wide bit memory 610b.
- the address conversion unit 620b outputs the bits truncated by the above-described right shift to the M counter 660b.
- the M counter 660b starts counting at the timing when the input bit (the truncated bit) is zero. Then, every time the count value reaches M, the M counter 660b inputs a signal indicating the timing to the serial / parallel converter 630b and the parallel / serial converter 640b.
- the serial / parallel converter 630b parallelizes the continuous input data and writes the parallelized data to the wide bit memory 610b based on the signal input timing from the M counter 660b (that is, once every M samples).
- the parallel / serial converter 640b reads the data by accessing the wide bit memory 610b based on the signal input timing from the M counter 660b (that is, once every M samples). Then, the parallel / serial conversion unit 640b continuously outputs the read data one sample at a time as output data.
- the number of accesses to the wide bit memory 610b can be suppressed, which can contribute to a reduction in power consumption.
- the adaptive equalizer may have a configuration in which the configuration shown in FIG. 13 and the configuration shown in FIG. 14 are combined.
- the adaptive equalizer may further include a control unit that switches the configuration of the data input / output unit depending on whether the access method to the wide bit memory 610b is random or continuous.
- the common mode of the signal converter circuit is not limited to the example of each embodiment described above.
- the adaptive equalizer may be configured to share the first to third multipliers and the time domain filter multiplier.
- Embodiment 4 of the present invention is an example in which the filter coefficient update frequency is made shorter than the block size in only a part of the regions.
- Non-Patent Document 1 When used in an actual environment, the performance is degraded if all the tap coefficients are updated in units of block sizes because they are affected by factors other than equalization processing, such as a synchronization error in timing reproduction. In particular, when a proximity multipath wave having a large D / U exists, the influence becomes significant.
- a general timing recovery method corresponding to a single carrier method such as the ATSC method, there is a method of extracting a timing component through a tank limiter circuit after square detection. When a proximity multipath wave having a large D / U exists, most of the signal components in the band from which the timing component is extracted disappear according to the phase relationship between the proximity multipath wave and the desired wave, and the timing reproduction signal A relatively large error may occur.
- the filter coefficients are updated more frequently than the block size (for example, every symbol) only for the main wave and its neighboring taps (for example, 16 taps before and after).
- FIG. 15 is a block diagram showing a configuration of the adaptive equalizer 100a according to the present embodiment.
- the adaptive equalizer 100a includes a third zero insertion unit 1501, a fourth zero insertion unit 1502, and a partial tap coefficient update unit 1503, compared to the adaptive equalizer 100a of FIG. .
- the adaptive equalizer 100a is obtained by changing the time domain filter 131a that receives only the decision feedback signal to a time domain filter 1504 that also receives the received signal in addition to the decision feedback signal.
- the third zero insertion unit 1501 is a tap coefficient that increases the update frequency among the main wave tap and the tap for canceling the preceding wave ahead of the main wave tap at the output of the second zero insertion unit 114. Only the part corresponding to is always set to zero.
- the adaptive equalizer 100a assumes, for example, that the number of FFT points is 1024, the number of taps in the feedforward unit is 300 taps, and only the main tap and the preceding 9 taps immediately before this are updated faster. To do.
- the second zero insertion unit 114 sets addresses 301 to 1024 where no tap coefficient exists to zero.
- 10 taps (addresses 291 to 300) for increasing the update frequency are set to zero.
- the third zero insertion unit 1501 is configured to prevent the normal processing in units of blocks and the processing with the faster update frequency from being overlapped with respect to the tap with the faster update frequency. Insert zeros so that normal processing is disabled.
- the overlap processing is performed, a disturbance factor in the adaptive processing is generated in a cycle of the block unit, and the equalization performance is deteriorated.
- the third zero insertion unit 1501 outputs the obtained signal to the third FFT unit 115.
- the fourth zero insertion unit 1502 always sets only the tap coefficient for increasing the update frequency to zero among the taps for canceling the delayed wave behind the main wave tap in the output of the third IFFT unit 143a. .
- a partial tap coefficient update unit 1503 is provided to perform conventional time domain processing instead of frequency domain processing in units of blocks.
- the role of the fourth zero insertion unit 1502 is to prevent the overlap processing between the processing that is processed in units of blocks and the partial tap coefficient update processing that is accelerated in the update frequency in the feedback filter calculation unit. For this reason, the fourth zero insertion unit 1502 invalidates the normal processing in units of blocks. If normal processing in units of blocks and processing with faster update frequency are overlapped, disturbance factors in adaptive processing will occur at the period of blocks, and the equalization performance will deteriorate. .
- the fourth zero insertion unit 1502 outputs the obtained signal to the fifth multiplier 144a.
- the partial tap coefficient updating unit 1503 has the same configuration as the coefficient updating unit 320a in FIG. 7 and multiplies the data string after determination input from the determination unit 108 and the determination error component input from the error extraction unit 109. The result is multiplied by a time constant ⁇ . Then, the partial tap coefficient updating unit 1503 derives a new tap coefficient by adding the result to the tap coefficient before update. The partial tap coefficient updating unit 1503 updates the filter coefficient at every symbol by performing this update every time determination data is obtained. Partial tap coefficient updating section 1503 outputs the obtained filter coefficient to time domain filter 1504.
- the input signal of the time domain filter 1504 is an output from the storage unit 101, but is delayed by an amount corresponding to the tap position that increases the update frequency.
- the calculation of taps with a fast update frequency is all handled by the partial tap coefficient update unit 1503.
- the third zero insertion unit 1501 and the fourth zero insertion unit 1502 are provided so that the normal processing in units of blocks and the processing with a faster update frequency are not overlapped in the tap calculation.
- the time domain filter 1504 includes a filter calculation unit 1603 that receives a received signal in addition to the filter calculation unit 310a of FIG. 7 that receives a determination feedback signal.
- a filter calculation unit 1603 that receives a received signal in addition to the filter calculation unit 310a of FIG. 7 that receives a determination feedback signal.
- the filter calculation unit 1603 has M tap coefficients, and includes M multipliers 1602, M registers 1604, an adder 1601, and the like.
- the filter calculation unit 1603 has the same configuration as the filter calculation unit 310a, but the number of taps is limited to the total number of taps for canceling the main wave tap and the preceding wave ahead of the main wave tap. .
- the filter calculation unit 1603 sets the output of the partial tap coefficient update unit 1503 for the filter coefficient.
- the filter calculation unit 310a similarly sets the output of the partial tap coefficient update unit 1503 for the tap coefficient that increases the update frequency, and sets the output of the second delay unit 146a for the tap coefficient that is updated in units of blocks. Yes.
- An adaptive equalizer has a signal conversion unit that performs at least one of a fast Fourier transform and an inverse fast Fourier transform in an adaptive equalizer that performs adaptive equalization processing on a time domain signal in a frequency domain.
- the signal conversion unit includes a memory capable of reading and writing a signal of 2M (M is a natural number) samples, 2M registers accessible to the memory, M butterfly calculation units, and the 2M pieces A switching control unit that switches a connection state between the register and the M butterfly computation units.
- the signal conversion unit includes two sets of the memory and the 2M registers
- the switching control unit includes fast Fourier transform / inverse fast Fourier transform.
- the connection state between the 2M registers of one set and the M butterfly operation units so that the role of the memory is switched between the output memory and the input memory for each stage of conversion.
- the connection state between the 2M registers of the other set and the M butterfly operation units is switched.
- the adaptive equalizer according to the present invention in the configuration described above, includes a first signal conversion unit as the signal conversion unit that performs fast Fourier transform, and a signal that has been subjected to fast Fourier transform by the first signal conversion unit.
- a second signal conversion unit as the signal conversion unit for performing inverse fast Fourier transform on the first signal conversion unit, the first signal conversion unit does not perform bit reverse rearrangement in the fast Fourier transform, The second signal conversion unit does not perform bit reverse rearrangement in the inverse fast Fourier transform.
- the signal conversion unit is a rotation that stores a rotator in each stage of fast Fourier transform / inverse fast Fourier transform and can read and write signals of M samples.
- the adaptive equalizer inputs the time-domain signal and connects the accumulation unit that sequentially accumulates a predetermined block size, and the previously accumulated block and the latest block.
- An inter-block connecting unit, a first fast Fourier transform unit as the signal converting unit that performs fast Fourier transform on the output of the inter-block connecting unit, and an output and frequency domain of the first fast Fourier transform unit A first multiplier that multiplies the adaptive equalizer coefficient converted into the first multiplier, and a first inverse fast Fourier transform unit as the signal transforming unit that performs an inverse fast Fourier transform on the output of the first multiplier
- a block extraction unit that extracts the latest signal sequence block from the output of the first inverse fast Fourier transform unit, and an error that extracts an error from the ideal signal point from the output of the first inverse fast Fourier transform unit
- Fast Fourier transform is performed on the output of the output unit, the first zero insertion unit that zeros a portion other than the desired tap coefficient in the extracted error series, and the second
- the adaptive equalizer according to the present invention further includes a time-domain filter unit that performs a decision feedback type equalization process on the output of the first inverse fast Fourier transform unit in the configuration described above. At least one of the multipliers used in the butterfly computing unit of the third fast Fourier transform unit and the first and second inverse fast Fourier transform units is shared with the convolution computation multiplier of the time domain filter unit. It has become.
- the adaptive equalizer according to the present invention has at least one of the multipliers used in the butterfly computing unit of the first to third fast Fourier transform units and the first and second inverse fast Fourier transform units in the configuration. One is shared with at least one of the first to third multipliers.
- the adaptive equalizer according to the present invention further includes a time-domain filter unit that performs a decision feedback type equalization process on the output of the first inverse fast Fourier transform unit in the configuration described above. At least one of the registers of the third fast Fourier transform unit and the first and second inverse fast Fourier transform units is shared with the register of the time domain filter unit.
- the adaptive equalizer according to the present invention uses a filter coefficient updated at a frequency shorter than the block size, and uses at least a decision feedback for the output of the first inverse fast Fourier transform unit of the main wave. It further has a time domain filter unit for performing type equalization processing.
- the adaptive equalizer according to the present invention is provided in a receiving apparatus having a multicarrier demodulation unit in the above configuration, and the memory is shared with the memory of the multicarrier demodulation unit.
- the adaptive equalizer according to the present invention includes an address conversion unit, a serial / parallel conversion unit, and a parallel / serial conversion unit in the above configuration, and an input / output unit that controls input / output of signals of the memory, and the memory And a control unit that switches the configuration of the input / output unit according to whether the access method is random or continuous.
- the input / output unit receives data of 2M samples from the memory before writing in a write mode in a case where a method of accessing the memory is random. Reading and data overwriting are performed only on a predetermined position of the memory.
- the present invention is useful as an adaptive equalizer that can suppress an increase in circuit scale and an operation clock frequency in an adaptive equalizer that performs an adaptive equalization process on a signal in the time domain in the frequency domain.
- the present invention is suitable for an adaptive equalizer of a receiving apparatus that supports multilevel VSB (Vestigial Sideband) modulation, which is employed in ATSC and the like.
- the present invention is suitable for various digital adaptive equalizers such as a speech echo canceller and a noise canceller that require a large number of taps in addition to an adaptive equalizer for wireless transmission.
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Abstract
Description
図1は、本発明の実施の形態1に係る適応等化器の構成を示すブロック図である。
本発明の実施の形態2は、時間領域処理による判定帰還型のフィードバックフィルタ(以下「時間領域フィルタ」という)を配置し、信号変換部の乗算器およびレジスタを、時間領域フィルタの乗算器およびレジスタと共用にした例である。
本発明の実施の形態3は、信号変換部のワイドビットメモリを他の装置部のメモリと共用にした例である。
本発明の実施の形態4は、一部の領域のみフィルタ係数の更新頻度をブロックサイズよりも短くした例である。
101 蓄積部
102 ブロック間連結部
103 第1のFFT部
104 複素共役部
105 第1の乗算器
106 第1のIFFT部
107 ブロック抽出部
108 判定部
109 誤差抽出部
110 第1のゼロ挿入部
111 第2のFFT部
112 第2の乗算器
113 第2のIFFT部
114 第2のゼロ挿入部
115 第3のFFT部
116 第3の乗算器
117 第1の加算器
118 第1の遅延部
120、120a 第1の係数更新部
131a 時間領域フィルタ
132a 第2の加算器
141a 第4のFFT部
142a 第4の乗算器
143a 第3のIFFT部
144a 第5の乗算器
145a 第3の加算器
146a 第2の遅延部
200 信号変換部
201 第1のワイドビットメモリ
201a、201b、207a、207b ワイドビットメモリ
202 第1のレジスタ群
202a、202b、206a、206b レジスタ群
203 第1の接続切替部
204 バタフライ演算部群
205 第2の接続切替部
206 第2のレジスタ群
207 第2のワイドビットメモリ
208 回転子用ワイドビットメモリ
209 回転子用レジスタ群
310a フィルタ演算部
311a、321a、413a 乗算器
312a、521a レジスタ
313a、323a、411a、412a 加算器
320a 第2の係数更新部
322a ステップサイズ係数乗算器
324a レジスタ
410a バタフライ演算部
414a 第1の切替部
420a 回転子レジスタ
430a 第2の切替部
440a 第3の切替部
450a、540a、550a、560a 制御部
500a レジスタ群配置部
510a レジスタ入力側切替部群
511a レジスタ入力側切替部
520a レジスタ群
530a レジスタ出力側切替部群
531a レジスタ出力側切替部
610b ワイドビットメモリ
620b アドレス変換部
630b シリアル/パラレル変換部
640b パラレル/シリアル変換部
650b ATSC/OFDM切替部
660b Mカウンタ
1501 第3のゼロ挿入部
1502 第4のゼロ挿入部
1503 部分タップ係数更新部
1504 時間領域フィルタ
1601 加算器
1602 乗算器
1603 フィルタ演算部
1604 レジスタ
Claims (12)
- 時間領域の信号に対する適応等化処理を周波数領域で行う適応等化器において、
高速フーリエ変換および逆高速フーリエ変換の少なくとも1つを行う信号変換部を有し、
前記信号変換部は、
2M(Mは自然数)サンプル分の信号を読み書きすることができるメモリと、
前記メモリにアクセス可能な2M個のレジスタと、
M個のバタフライ演算部と、
前記2M個のレジスタと前記M個のバタフライ演算部との間の接続状態を切り替える切替制御部と、を有する、
適応等化器。 - 前記信号変換部は、
前記メモリと前記2M個のレジスタとの組を2組有し、
前記切替制御部は、
高速フーリエ変換/逆高速フーリエ変換のステージごとに、前記メモリの役割が、出力用メモリと入力用メモリとの間で切り替わるように、一方の組の前記2M個のレジスタと前記M個のバタフライ演算部との間の接続状態、および、他方の組の前記2M個のレジスタと前記M個のバタフライ演算部との間の接続状態を切り替える、
請求項1記載の適応等化器。 - 高速フーリエ変換を行う前記信号変換部としての第1の信号変換部と、前記第1の信号変換部により高速フーリエ変換が行われた信号に対して逆高速フーリエ変換を行う前記信号変換部としての第2の信号変換部と、を有し、
前記第1の信号変換部は、
高速フーリエ変換におけるビットリバースの並べ替えを実施せず、
前記第2の信号変換部は、
逆高速フーリエ変換におけるビットリバースの並べ替えを実施しない、
請求項2記載の適応等化器。 - 前記信号変換部は、
高速フーリエ変換/逆高速フーリエ変換の各ステージにおける回転子を格納した、Mサンプル分の信号を読み書きすることができる回転子用メモリと、
前記回転子用メモリにアクセス可能であって、前記回転子を取得して前記M個のバタフライ演算部へ渡すM個の回転子用レジスタと、を更に有する、
請求項1記載の適応等化器。 - 前記時間領域の信号を入力し、逐次的に所定のブロックサイズ分を蓄積する蓄積部と、
前回蓄積されたブロックと最新のブロックとを連結するブロック間連結部と、
前記ブロック間連結部の出力に対して高速フーリエ変換を行う前記信号変換部としての第1の高速フーリエ変換部と、
前記第1の高速フーリエ変換部の出力と周波数領域に変換された適応等化器係数とを乗じる第1の乗算器と、
前記第1の乗算器の出力に対して逆高速フーリエ変換を行う前記信号変換部としての第1の逆高速フーリエ変換部と、
前記第1の逆高速フーリエ変換部の出力から最新の信号系列ブロックを抽出するブロック抽出部と、
前記第1の逆高速フーリエ変換部の出力から理想信号点との誤差を抽出する誤差抽出部と、
抽出された前記誤差の系列のうち、所望のタップ係数以外の箇所をゼロにする第1のゼロ挿入部と、
前記第2のゼロ挿入部の出力に対して高速フーリエ変換を行う前記信号変換部としての第2の高速フーリエ変換部と、
前記第1の高速フーリエ変換部の出力の複素共役と前記第2の高速フーリエ変換部の出力とを乗じる第2の乗算器と、
前記第2の乗算器の乗算結果に対して逆高速フーリエ変換を行う前記信号処理部としての第2の逆高速フーリエ変換部と、
前記第2の逆高速フーリエ変換部の出力のうち、所望のタップ係数以外の箇所をゼロにするゼロ挿入部と、
前記第2のゼロ挿入部の出力に対して高速フーリエ変換を行う前記信号処理部としての第3の高速フーリエ変換部と、
前記第3の高速フーリエ変換部の出力と所定の係数とを乗じる第3の乗算器と、
前記第3の乗算器の出力を累積する累積部と、を有する、
請求項1記載の適応等化器。 - 前記第1の逆高速フーリエ変換部の出力に対して判定帰還型等化処理を行う時間領域フィルタ部、を更に有し、
前記第1~第3の高速フーリエ変換部および前記第1および第2の逆高速フーリエ変換部の前記バタフライ演算器で用いられる乗算器の少なくとも1つが、前記時間領域フィルタ部の畳込み演算用乗算器と共用となっている、
請求項5記載の適応等化器。 - 前記第1~第3の高速フーリエ変換部および前記第1および第2の逆高速フーリエ変換部の前記バタフライ演算器で用いられる乗算器の少なくとも1つが、前記第1~第3の乗算器の少なくとも1つと共用となっている、
請求項5記載の適応等化器。 - 前記第1の逆高速フーリエ変換部の出力に対して判定帰還型等化処理を行う時間領域フィルタ部、を更に有し、
前記第1~第3の高速フーリエ変換部および前記第1および第2の逆高速フーリエ変換部の前記レジスタの少なくとも1つが、前記時間領域フィルタ部のレジスタと共用となっている、
請求項5記載の適応等化器。 - 前記ブロックサイズよりも短い頻度で更新したフィルタ係数を用いて、少なくとも主波の前記第1の逆高速フーリエ変換部の出力に対して判定帰還型等化処理を行う時間領域フィルタ部を更に有する、
請求項5記載の適応等化器。 - マルチキャリア方式復調部を備えた受信装置に設けられ、
前記メモリは、
前記マルチキャリア方式復調部のメモリと共用となっている、
請求項1記載の適応等化器。 - アドレス変換部、シリアル/パラレル変換部、およびパラレル/シリアル変換部を含み、前記メモリの信号の入出力を制御する入出力部と、
前記メモリへのアクセス方法がランダムであるか連続であるかに応じて、前記入出力部の構成を切り替える制御部と、を更に有する、
請求項10記載の適応等化器。 - 前記入出力部は、
前記メモリへのアクセス方法がランダムである場合の書き込みモードにおいて、書き込みを行う前に前記メモリから2Mサンプル分のデータを読み出し、データの上書きを前記メモリの所定の位置に対してのみ行う、
請求項10記載の適応等化器。
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