WO2013057856A1 - 適応等化器 - Google Patents
適応等化器 Download PDFInfo
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- WO2013057856A1 WO2013057856A1 PCT/JP2012/004252 JP2012004252W WO2013057856A1 WO 2013057856 A1 WO2013057856 A1 WO 2013057856A1 JP 2012004252 W JP2012004252 W JP 2012004252W WO 2013057856 A1 WO2013057856 A1 WO 2013057856A1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L25/03159—Arrangements for removing intersymbol interference operating in the frequency domain
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
- G06F17/14—Fourier, Walsh or analogous domain transformations, e.g. Laplace, Hilbert, Karhunen-Loeve, transforms
- G06F17/141—Discrete Fourier transforms
- G06F17/142—Fast Fourier transforms, e.g. using a Cooley-Tukey type algorithm
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
- H04L25/03019—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
- H04L25/03057—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception with a recursive structure
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/01—Equalisers
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L2025/0335—Arrangements for removing intersymbol interference characterised by the type of transmission
- H04L2025/03375—Passband transmission
- H04L2025/03414—Multicarrier
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L2025/03433—Arrangements for removing intersymbol interference characterised by equaliser structure
- H04L2025/03535—Variable structures
- H04L2025/03541—Switching between domains, e.g. between time and frequency
Definitions
- the present invention relates to an adaptive equalizer that performs adaptive equalization processing on a time domain signal in the frequency domain.
- the wireless signal receiving apparatus needs to remove this influence.
- the Advanced Television Systems Committee (ATSC) system is used as a digital television broadcasting system.
- the ATSC system employs single carrier modulation.
- an ATSC receiver is premised on the application of an adaptive equalizer.
- Single carrier modulation generally performs adaptive equalization processing in the time domain.
- the adaptive equalization process in the time domain requires a convolution operation in the filter process and the coefficient update process, and the circuit scale increases as the number of taps increases.
- Patent Document 1, Patent Document 2, and Non-Patent Document 1 there is a technique for performing adaptive equalization processing on a time domain signal in the frequency domain instead of the time domain.
- the techniques described in Patent Document 1, Patent Document 2, and Non-Patent Document 1 (hereinafter referred to as “prior art”) perform adaptive equalization processing after converting a time domain signal into a frequency domain signal by fast Fourier transform. Do. Further, in the conventional technique, the frequency domain signal after the adaptive equalization processing is converted into a time domain signal by inverse fast Fourier transform. In such a single-carrier modulation signal receiving apparatus using the conventional technique, it is possible to improve reception performance while suppressing an increase in circuit scale.
- the conventional technique has a problem that the operation clock frequency required for the adaptive equalizer becomes high when the number of taps required is large or when it is necessary to perform reception processing at high speed.
- the operation clock frequency when the operation clock frequency is increased, the power consumption of the adaptive equalizer is increased, and there is a problem in that it becomes troublesome when mounted on an FPGA (Field-Programmable-Gate-Array). Therefore, it is desirable that an adaptive equalizer that performs adaptive equalization processing for a signal in the time domain in the frequency domain can suppress an increase in circuit scale and an increase in operating clock frequency as much as possible.
- An object of the present invention is to provide an adaptive equalizer that can suppress an increase in circuit scale and an operation clock frequency in an adaptive equalizer that performs an adaptive equalization process on a time domain signal in a frequency domain. is there.
- the adaptive equalizer of the present invention has a signal conversion unit that performs at least one of fast Fourier transform and inverse fast Fourier transform in an adaptive equalizer that performs adaptive equalization processing on a signal in the time domain in the frequency domain.
- the signal conversion unit includes a memory capable of reading and writing signals of 2M (M is a natural number) samples, 2M registers accessible to the memory, M butterfly operation units, and the 2M registers And a switching control unit that switches a connection state between the M butterfly computation units.
- an increase in circuit scale and an increase in operating clock frequency can be suppressed.
- FIG. 1 is a block diagram showing a configuration of an adaptive equalizer according to Embodiment 1 of the present invention.
- the chart figure which shows an example of the processing timing of each signal conversion part in Embodiment 1 of this invention
- the block diagram which shows the 1st example of a structure of the signal conversion part which concerns on Embodiment 1 of this invention.
- the block diagram which shows the 2nd example of a structure of the signal conversion part which concerns on Embodiment 1 of this invention.
- the block diagram which shows the 3rd example of a structure of the signal conversion part which concerns on Embodiment 1 of this invention.
- the block diagram which shows the 1st example of a structure of the adaptive equalizer which concerns on Embodiment 2 of this invention.
- FIG. 5 is a block diagram showing an example of a configuration of a time domain filter according to Embodiment 2 of the present invention.
- the block diagram which shows an example of a structure of the periphery of the butterfly calculating part in Embodiment 2 of this invention The block diagram which shows the 1st example of a structure of the register periphery in Embodiment 2 of this invention.
- FIG. 7 is a block diagram showing a second example of the configuration of the adaptive equalizer according to Embodiment 2 of the present invention.
- Block diagram showing the configuration of an adaptive equalizer according to Embodiment 4 of the present invention The block diagram which shows the structure of the signal conversion part in Embodiment 4 of this invention.
- the block diagram which shows the principal part of the circuit structure of the adaptive equalizer using a single port memory The block diagram which shows the principal part of the circuit structure of the adaptive equalizer which concerns on Embodiment 4 of this invention.
- the block diagram which shows the principal part of the modification of the circuit structure of the adaptive equalizer which concerns on Embodiment 4 of this invention The block diagram which shows the memory peripheral constitution of the adaptive equalizer when the single port memory is used The block diagram which shows the structure of the periphery of the memory of the adaptive equalizer which concerns on Embodiment 4 of this invention. The block diagram which shows the principal part of the further modification of the circuit structure of the adaptive equalizer which concerns on Embodiment 4 of this invention.
- FIG. 1 is a block diagram showing a configuration of an adaptive equalizer according to Embodiment 1 of the present invention.
- the adaptive equalizer 100 includes a second multiplier 112, a second IFFT unit 113, a second zero insertion unit 114, a third FFT unit 115, a third multiplier 116, and a first adder. 117 and a first delay unit 118.
- the storage unit 101 receives time domain signals and sequentially stores a predetermined block size.
- the inter-block connection unit 102 connects the block stored in the storage unit 101 and the latest block and outputs the result.
- the complex conjugate unit 104 outputs the complex conjugate of the first FFT unit 103.
- the first multiplier 105 multiplies the output of the first FFT unit 103 and the output of the first delay unit 118 described later (adaptive equalizer coefficient converted to the frequency domain), and uses the obtained signal. Output.
- the first IFFT unit 106 performs inverse fast Fourier transform on the output of the first multiplier 105, and outputs the obtained signal.
- the block extraction unit 107 extracts the latest signal sequence block from the output of the first IFFT unit 106 and outputs it.
- the determination unit 108 outputs a determination result for the output of the block extraction unit 107.
- the error extraction unit 109 Based on the output of the determination unit 108, the error extraction unit 109 extracts an error from the ideal signal point from the output of the block extraction unit 107 (that is, the output of the first IFFT 106), and outputs the extracted error.
- the first zero insertion unit 110 receives the error extracted by the error extraction unit 109, zeros a portion other than the desired tap coefficient in the error series, and outputs the obtained signal.
- the second multiplier 112 multiplies the output of the complex conjugate unit 104 (that is, the complex conjugate of the output of the first FFT unit 103) and the output of the second FFT unit 111, and outputs the obtained signal.
- the third FFT unit 115 performs a fast Fourier transform on the output of the second zero insertion unit 114 and outputs the obtained signal.
- the adaptive equalizer 100 arranges the second IFFT unit 113, the second zero insertion unit 114, and the third FFT unit 115 in the subsequent stage of the second multiplier 112.
- the adaptive equalizer 100 can remove the influence caused by Fourier transform of a discontinuous signal.
- these parts have a function to return the multiplication result of the error sequence and the input signal in the frequency domain to the time domain, and to convert the invalid part as a tap coefficient to zero, and then convert it to the frequency domain again. is doing.
- the third multiplier 116 multiplies the output of the third FFT unit 115 by a predetermined coefficient ⁇ and outputs the obtained signal.
- the first adder 117 adds the output of the third multiplier 116 and the output of the first delay unit 118 in the subsequent stage, and outputs the obtained signal.
- the first delay unit 118 delays the output of the first adder 117 and outputs it to the first multiplier 105 as an adaptive equalizer coefficient converted to the frequency domain.
- the first adder 117 and the first delay unit 118 function as an accumulating unit that accumulates the output of the third multiplier 116.
- the complex conjugate unit 104 and the part from the determination unit 108 to the first delay unit 118 function as the first coefficient update unit 120 in the adaptive equalizer 100.
- the adaptive equalizer 100 can perform the adaptive equalization processing for the time domain signal in the frequency domain instead of the time domain.
- the fast Fourier transform / inverse fast Fourier transform is performed at five locations of the first to third FFT units 103, 111, 115 and the first and second IFFT units 106, 113.
- these fast Fourier transform / inverse fast Fourier transform a part of the computation processing is executed in parallel, thereby reducing the number of necessary computations and shortening the time required for computation processing of the adaptive equalizer 100. Is possible. Therefore, the adaptive equalizer 100 may execute the fast Fourier transform / inverse fast Fourier transform operation that can be performed in parallel, in parallel.
- a system from the inter-block connecting unit 102 to the first multiplier 105 through the complex conjugate unit 104 is referred to as an A system.
- a system from the first multiplier 105 to the second multiplier 112 of the A system through the determination unit 108 is referred to as a B system.
- the arithmetic processing of the first FFT unit 103 is processing A-1
- the arithmetic processing of the second IFFT unit 113 is processing A-2
- the arithmetic processing of the third FFT unit 115 is processing.
- A-3 the arithmetic processing of the first IFFT unit 106 is represented as processing A-4.
- the calculation process of the second FFT unit 111 is represented as process B-1.
- the first to third FFT units 103, 111, and 115, and the first and second IFFT units 106 and 113 are collectively referred to as “signal conversion units” as appropriate.
- FIG. 2 is a chart showing an example of processing timing of each signal conversion unit of the adaptive equalizer 100.
- Process A-1 and process B-1 are not dependent on each other.
- the adaptive equalizer 100 is provided with two systems for performing fast Fourier transform / inverse fast Fourier transform arithmetic processing. For example, as shown in FIG. 2, processing A-1 and processing B-1 are performed in parallel. Execute. As a result, the adaptive equalizer 100 can reduce the time required for one fast Fourier transform / inverse fast Fourier transform operation.
- the process A-2 depends on the process data of the process B-1, and the process B-1 must be completed before the start timing. Therefore, as shown in FIG. 2, the adaptive equalizer 100 needs to complete the processes A-1 to A-4 within the block size for the A system.
- the adaptive equalizer 100 reduces the fast Fourier transform / inverse fast Fourier transform calculation time required per block size even when the number of circuits is increased to three or more due to the dependency of the signal processing data. It cannot be reduced to less than 4 times.
- the calculation time of the block size is about 38.65 ⁇ sec. . Therefore, in the ATSC standard, the 1024-point fast Fourier transform / inverse fast Fourier transform must be performed a total of 5 times (4 times in the above example) in about 38.65 ⁇ sec. Even if processing time other than the fast Fourier transform / inverse fast Fourier transform is ignored, the calculation process of one fast Fourier transform / inverse fast Fourier transform is completed within 7.73 ⁇ sec (in the above example, 9.66 ⁇ sec). There must be.
- the adaptive equalizer is several hundred taps or more.
- the assumed application system must support a long delay multipath of 40 ⁇ sec or more, and requires a tap number of at least 500 taps or more.
- the adaptive equalizer 100 is configured such that a circuit is configured with registers that are not limited to simultaneous access, and the utilization of a single port memory is realized.
- a memory as means for holding digital data having the same capacity can be realized with an area of a fraction of that of a register.
- the adaptive equalizer 100 according to the present embodiment increases the circuit scale by using a memory capable of reading and writing a plurality of signal samples and a plurality of registers accessible to each signal conversion unit. Can be suppressed.
- FIG. 3 is a block diagram showing a first example of the configuration of the signal conversion unit according to the present embodiment.
- the signal conversion units are the first to third FFT units 103, 111, and 115 and the first and second IFFT units 106 and 113 shown in FIG.
- each operation stage performed by the fast Fourier transform / inverse fast Fourier transform is simply referred to as a “stage”.
- the first wide bit memory 201 and the second wide bit memory 207 are memories having a large word size capable of reading and writing signals (data) of M samples (2 M samples for two times).
- the order of data held in the first wide bit memory 201 and the second wide bit memory 207 is the same as the order of data read by the normal fast Fourier transform / inverse fast Fourier transform operation.
- the first wide bit memory 201 and the second wide bit memory 207 collectively store the data for M samples at one address.
- the first connection switching unit 203 switches the connection state between the first register group 202 and the butterfly operation unit group 204 (hereinafter referred to as “connection state on the first register group 202 side”).
- the butterfly computation unit group 204 is composed of M butterfly computation units, each performing a butterfly computation.
- connection state on the second register group 206 side switches the connection state between the butterfly computation unit group 204 and the second register group 206 (hereinafter referred to as “connection state on the second register group 206 side”).
- the second register group 206 is composed of 2M registers each capable of accessing the second wide bit memory 207.
- the second register group 206 accesses the second wide bit memory 207 twice to perform simultaneous access in which 2M samples are substantially parallelized.
- the operation clock frequency required for memory access of the first register group 202 and the second register group 206 is twice the operation clock frequency of the butterfly operation unit group 204.
- the first register group 202 and the second register group 206 need to perform memory access 2 ⁇ (1024 / M) times to complete one stage.
- the first connection switching unit 203 and the second connection switching unit 205 must appropriately control switching of the connection state between each register and each butterfly calculation unit every two memory accesses. Don't be.
- the first connection switching unit 203 and the second connection switching unit 205 have an output memory, an input memory, and a role of the first wide bit memory 201 and the second wide bit memory 207, respectively.
- the first connection switching unit 203 and the second connection switching unit 205 change the connection state on the first register group 202 side and the connection state on the second register group 206 side to appropriate states.
- the appropriate state is a state in which a signal is input from each appropriate register to each butterfly operation unit and a signal is output from each appropriate register from each butterfly operation unit.
- the butterfly calculation unit group 204 sequentially performs the calculation of each stage according to the switching of the connection state.
- the traveling direction of the signal is switched to the left and right for each stage. That is, when 10 stages of computation are required, for example, the signal advances in the right direction in FIG. 3 in the first stage, and the signal advances in the left direction in FIG. 3 in the next second stage.
- the signal processing unit 200 FFT unit / IFFT unit
- the signal processing unit 200 can prevent an increase in circuit scale by switching the signal traveling direction for each stage and using the circuit repeatedly.
- the signal conversion unit (FFT unit / IFFT unit) 200 can realize reception processing in real time at a low operation clock frequency while avoiding the use of multi-ports whose circuit scale increases.
- the signal converter 200 may use a two-bank wide bit memory.
- FIG. 4 is a block diagram illustrating a second example of the configuration of the signal conversion unit 200.
- the signal conversion unit 200 includes wide bit memories 201a and 201b and register groups 202a and 202b instead of the first wide bit memory 201 and the first register group 202 of FIG. .
- the signal conversion unit 200 includes wide bit memories 207a and 207b and register groups 206a and 206b instead of the second wide bit memory 207 and the second register group 206 of FIG.
- the signal conversion unit 200 can reduce the number of memory accesses by configuring a wide bank memory of two banks. That is, the number of memory accesses required 2 ⁇ (1024 / M) times in the case of one bank configuration (see FIG. 3) is reduced to half. Therefore, the operation clock frequency of the register group can be the same as that of the butterfly operation unit, and can be half that of the configuration shown in FIG. In other words, in the memory access operation, in the case of the one-bank configuration, twice the clock frequency of the butterfly operation unit is required, but in the case of the two-bank configuration, the clock frequency may be maintained as one time.
- the signal conversion unit 200 Even if the signal conversion unit 200 has a one-bank configuration, if a dual port that can access any two addresses at the same time is adopted, the signal conversion unit 200 should remain at a single clock frequency as in the two-bank configuration. Is possible. However, the circuit size of the dual port configuration increases as the number of ports increases. On the other hand, the two-bank configuration is a configuration that cannot access addresses across banks, and an increase in circuit scale with respect to the one-bank configuration is negligible.
- the signal conversion unit 200 has a two-bank configuration as shown in FIG. 4, thereby avoiding the use of multi-ports with an increased circuit scale and performing reception processing in real time at a lower operating clock frequency. It can be realized.
- the rotor wide bit memory 208 is a memory having a large word size capable of reading and writing signals (data) for M rotors.
- the rotor wide bit memory 208 has an address assigned to each stage, and stores a rotor in each stage in advance.
- the rotator register group 209 includes M registers each capable of accessing the rotator wide bit memory 208. That is, the rotator register group 209 performs simultaneous access to the rotator wide bit memory 208 by parallelizing M rotators. Then, the rotator register group 209 reads M corresponding rotators from the rotator wide bit memory 208 for each stage, and passes them to an appropriate butterfly operation unit of the butterfly operation unit group 204.
- the signal conversion unit 200 does not need to provide a memory for holding the rotor for each butterfly operation unit, and can further reduce the circuit scale.
- the adaptive equalizer 100 includes the signal conversion unit 200 using a memory having a large word size and a plurality of registers for accessing the memory. Thereby, the adaptive equalizer 100 can suppress an increase in circuit scale and an increase in operation clock frequency.
- the entire adaptive equalizer 100 according to the present embodiment, the condition that an inverse fast Fourier transform is always performed on a fast Fourier transform once performed.
- a decision feedback type feedback filter (hereinafter referred to as “time domain filter”) by time domain processing is arranged, and the multiplier and register of the signal conversion unit are replaced with the multiplier and register of the time domain filter. This is an example of sharing.
- the time domain filter 131a is a transversal filter, which receives the output of the determination unit 108 and the output of the error extraction unit 109, and outputs a time domain feedback signal.
- the second adder 132a adds the output of the block extraction unit 107 and the feedback signal that is the output of the time domain filter 131a, and outputs the obtained signal. Note that the determination unit 108 and the error extraction unit 109 receive not the output of the block extraction unit 107 but the output of the second adder 132a.
- the time domain filter 131a includes a filter calculation unit 310a and a second coefficient update unit 320a.
- the filter operation unit 310a has N tap coefficients, and includes N multipliers 311a, N registers 312a, an adder 313a, and the like.
- the tap coefficients (wb 0 , wb 1 , wb 2 , wb 3 ,..., Wb N ⁇ 1 ) in the filter calculation unit 310 a are coefficients obtained by the second coefficient update unit 320 a.
- the second coefficient updating unit 320a includes N multipliers 321a, N step size coefficient ( ⁇ ) multipliers 322a, N adders 323a, N registers 324a, and the like.
- the second coefficient updating unit 320a operates as an adaptive filter and obtains tap coefficients (wb 0 , wb 1 , wb 2 , wb 3 ,..., Wb N ⁇ 1 ) in the filter calculation unit 310a.
- signals are input to the time domain filter 131a in units of block sizes.
- the adaptive equalization process in the frequency domain and the adaptive equalization process in the time domain can be executed in parallel.
- adaptive equalizer 100a uses a part of a circuit used in adaptive equalization processing in the frequency domain and adaptive equalization processing in the time domain.
- a part of the circuit can be shared.
- the adaptive equalizer 100a includes a multiplier (not shown in FIG. 3) of each butterfly operation unit of the signal conversion unit 200 (see FIG. 3), a multiplier 311a and a multiplier 321a of the time domain filter 131a. Can be shared.
- the adaptive equalizer 100a can share the first and second register groups 202 and 206 of the signal conversion unit 200 (see FIG. 3) and the registers 312a and 324a of the time domain filter 131a. .
- FIG. 8 is a block diagram showing an example of the configuration around the butterfly computation unit.
- the signal conversion unit (not shown) has a second switching unit 430a disposed between the rotor register 420a holding the rotor and the multiplier 413a, and the third switching unit 430a is connected to the output side of the multiplier 413a.
- the switching unit 440a is arranged.
- the signal conversion unit includes a control unit 450a that controls switching of connection states of the first to third switching units 414a, 430a, and 440a.
- the first switching unit 414a switches one input of the multiplier 413a between the output of the adder 412a and the output of a calculation unit other than the signal conversion unit (hereinafter referred to as “other calculation unit”). It has become.
- the second switching unit 430a switches the other input of the multiplier 413a between the output of the rotator register 420a and the output of another arithmetic unit.
- the third switching unit 440a is configured to switch the output destination of the multiplier 413a between the connection switching unit of the signal conversion unit and another arithmetic unit.
- the control unit 450a controls the first to third switching units 414a, 430a, and 440a so that the normal connection of the butterfly computation unit 410a is established. . That is, the control unit 450a causes the multiplier 413a of the butterfly calculation unit 410a to be used for calculation processing of fast Fourier transform / inverse fast Fourier transform.
- the control unit 450a causes the first to third switching units 414a, 430a, 440a to be connected in reverse to the normal connection.
- the control unit 450a includes the first to third switching units 414a, so that the multiplier 413a of the butterfly calculation unit 410a functions as, for example, the multipliers 311a and 321a (see FIG. 7) of the time domain filter 131a. 430a and 440a are controlled.
- FIG. 9 is a block diagram showing a first example of the configuration around the register.
- the register group arrangement unit 500a includes a register input side switching unit group 510a, a register group 520a, a register output side switching unit group 530a, and a control unit 540a.
- the register group 520a corresponds to the first and second register groups 202 and 206 (see FIG. 3) of the signal conversion unit 200 described in the first embodiment.
- the register input side switching unit group 510a includes 2M register input side switching units 511a arranged one-to-one on the input side of the 2M registers 521a of the register group 520a.
- the register output side switching unit group 530a includes 2M register output side switching units 531a arranged one-to-one on the output side of each register 521a of the register group 520a.
- One of the register input side switching units 511a switches the input of the corresponding register 521a between the signal conversion unit 200 (see FIG. 3) and the determination unit 108 (see FIG. 6). Then, the other register input side switching unit 511a switches the input of the corresponding register 521a between the signal conversion unit 200 (see FIG. 3) and the output of the register 521a adjacent to the corresponding register 521a.
- the register output side switching unit 531a sets the output destination of the corresponding register 521a to the signal conversion unit 200 (see FIG. 3) and the input side of the register 521a adjacent to the corresponding register 521a (the input side of the register input side switching unit 511a). ).
- the control unit 540a controls the register input side switching unit group 510a and the register output side switching unit group 530a so that the connection is the reverse of the normal connection. To do. Specifically, the control unit 540a connects adjacent registers 521a so that the entire register group 520a functions as a shift register. The control unit 540a controls the register input side switching unit group 510a and the register output side switching unit group 530a so that the register group 520a functions as the register 312a (see FIG. 7) of the filter operation unit 310a of the time domain filter 131a. To do.
- FIG. 10 is a block diagram showing a second example of the configuration around the register, and corresponds to FIG.
- the same parts as those in FIG. 9 are denoted by the same reference numerals, and description thereof will be omitted.
- each register input side switching unit 511a receives the input of the corresponding register 521a from the signal conversion unit 200 (see FIG. 3) and the adder 323a of the second coefficient update unit 320a of the time domain filter 131a (see FIG. 10). 7).
- control unit 550a controls the register input side switching unit group 510a and the register output side switching unit group 530a so as to achieve the above-described normal connection.
- the control unit 550a controls the register input side switching unit group 510a and the register output side switching unit group 530a so that the connection is reverse to the normal connection. To do.
- the control unit 550a includes a register input side switching unit group 510a and a register output side switching unit group so that the register group 520a functions as the register 324a (see FIG. 7) of the second coefficient updating unit 320a of the time domain filter 131a. 530a is controlled.
- the register 324a of the second coefficient updating unit 320a needs to hold past coefficient values. Therefore, as in this embodiment, when the register of the signal conversion unit and the register 324a of the second coefficient update unit 320a are shared, the register data is stored in the memory before switching, and the switching is performed. It is necessary to read data from the memory again later.
- the register input side switching unit 511a further has a memory value reading unit (not shown) of a coefficient value memory for holding past coefficient values on the input side of the corresponding register 521a. Switch to the output side of and connect. Further, the register output side switching unit 531a further switches and connects the output side of the corresponding register 521a to a memory writing unit (not shown) of the coefficient value memory. Then, the control unit 560a performs the same control as the above-described control unit 550a. Further, the control unit 560a sets the register input side switching unit group 510a and the register output side switching unit group 530a so that the coefficient values are read from and written to the coefficient value memory in the calculation process of the time domain filter 131a. Control.
- the adaptive equalizer 100a can improve the reception performance while suppressing an increase in circuit scale.
- the frequency of feedback in the time domain (frequency of updating the coefficient of the time domain filter 131a) can be a ratio once per block size. This is the same as the frequency of feedback in the frequency domain (coefficient update frequency of the first coefficient update unit 120a in FIG. 6). In this case, the second coefficient updating unit 320a of the time domain filter 131a is not necessary.
- FIG. 12 is a block diagram showing a second example of the configuration of the adaptive equalizer 100a, and corresponds to FIG.
- the same parts as those in FIG. 6 are denoted by the same reference numerals, and description thereof will be omitted.
- the adaptive equalizer 100a shown in FIG. 12 does not include the second coefficient update unit 320a described in FIG. 7 in the time domain filter 131a.
- An adaptive equalizer 100a shown in FIG. 12 replaces the second coefficient updating unit 320a with a fourth FFT unit 141a, a fourth multiplier 142a, a third IFFT unit 143a, a fifth multiplier 144a, A third adder 145a and a second delay unit 146a are included.
- the fourth FFT unit 141a performs a fast Fourier transform (transformation to the frequency domain) on the output (feedback signal after determination) of the determination unit 108, and outputs the obtained signal.
- the fourth multiplier 142a multiplies the output of the second FFT unit 111 and the output of the fourth FFT unit 141a, and outputs the obtained signal.
- the third IFFT unit 143a performs inverse fast Fourier transform (transformation into the time domain) on the output (error component from the determination value) of the fourth multiplier 142a, and outputs the obtained signal.
- the fifth multiplier 144a multiplies the output of the third IFFT unit 143a and the coefficient update step size ( ⁇ ), and outputs the obtained signal.
- the third adder 145a adds the output of the fifth multiplier 144a and the output of the second delay unit 146a in the subsequent stage, and outputs the obtained signal.
- the second delay unit 146a delays the output of the third adder 145a and outputs it to the time domain filter 131a as an adaptive equalizer coefficient converted to the time domain.
- the third adder 145a and the second delay unit 146a function as an accumulating unit that accumulates the output of the fifth multiplier 144a.
- the adaptive equalizer 100a can reduce the number of multipliers and registers necessary for the transversal filter even when the feedback unit must have a large number of coefficients. Can be reduced.
- the third embodiment of the present invention is an example in which the wide bit memory of the signal conversion unit is shared with the memory of another device unit.
- the OFDM demodulator (multi-carrier demodulator)
- the number of fast Fourier transform operations required for basic demodulation processing is only one, and there is a feedback system that requires adaptive processing. No.
- the OFDM demodulator can perform arithmetic processing by a plurality of circuits simultaneously in a pipeline manner, and real-time processing is possible without using the configuration of the signal converter of the present invention.
- the memory essential to the OFDM demodulator is shared with the memory of the adaptive equalizer 100, so that the entire apparatus by adding the adaptive equalizer 100 can be reduced. It is conceivable to suppress an increase in circuit scale.
- the OFDM demodulator is a method of converting a time domain signal into a frequency domain signal by fast Fourier transform and equalizing based on a channel estimation value. Therefore, the configuration of the OFDM demodulator is significantly different from that of the adaptive equalizer, and there are few parts common to these. For this reason, when realizing a circuit that can handle both the ATSC system and the OFDM system, a large area is conventionally required, and an increase in cost is inevitable.
- the receiving apparatus employing the adaptive equalizer 100 according to the present embodiment can reduce the circuit scale of a circuit that can handle both the ATSC system and the OFDM system by sharing the memory. Is possible.
- FIG. 13 is a block diagram showing a first example of the configuration around the memory according to the present embodiment.
- the adaptive equalizer (not shown) according to the present embodiment includes an address conversion unit 620b, a serial / parallel conversion unit 630b, a parallel / serial conversion unit 640b, and an ATSC / OFDM switching unit 650b.
- an address conversion unit 620b a serial / parallel conversion unit 630b, a parallel / serial conversion unit 640b, and an ATSC / OFDM switching unit 650b.
- the wide bit memory 610b corresponds to the first wide bit memory 201 and the second wide bit memory 207 (see FIG. 3) described in the first embodiment.
- the wide bit memory 610b reads / writes data according to these signals.
- the address conversion unit 620b shifts the address signal to the right by Log 2 (M) bits and inputs only the upper bits to the wide bit memory 610b in the OFDM mode in which the operation for OFDM is performed.
- the address conversion unit 620b inputs the bits truncated by the right shift to the serial / parallel conversion unit 630b and the parallel / serial conversion unit 640b. That is, the serial / parallel converter 630b and the parallel / serial converter 640b are designated as to which position of the data held together for M samples.
- the serial / parallel converter 630b inputs the input data as it is to the wide bit memory 610b without conversion.
- the parallel / serial conversion unit 640b uses the data for M samples output from the wide bit memory 610b as output data without conversion.
- the M counter 660b starts counting at the timing when the input bit (the truncated bit) is zero. Then, every time the count value reaches M, the M counter 660b inputs a signal indicating the timing to the serial / parallel converter 630b and the parallel / serial converter 640b.
- Embodiment 4 of the present invention is an example in which an increase in the total number of wirings connecting between memory and logic and between memory and memory is suppressed.
- the number of FFT and IFFT operations that must be executed for each block can be reduced by performing a parallel operation by dividing the system into a plurality of systems (see FIG. 2). .
- the conditions for the processing time allowed for the FFT and IFFT are relaxed.
- FIG. 15 is a block diagram showing a configuration of adaptive equalizer 1500 according to the present embodiment.
- the output of the first FFT unit 103 is input to the first multiplier 105 and the complex conjugate unit 104 in the configuration of the adaptive equalizer 1500 shown in FIG.
- the output of the complex conjugate unit 104 is input to the second multiplier 112.
- the reception signal and the filter coefficient are multiplied.
- the operation of the second multiplier 112 multiplies the received signal and the error to derive an update component of the filter coefficient. .
- the wide bit simple dual port memory 1601 can simultaneously read (Read) and write (Write) to different addresses for signals of 2M samples.
- Read Read
- Write write
- a general full dual port memory reading and reading, or writing and writing can be performed simultaneously for different addresses.
- the simple dual port memory can only perform reading and writing at the same time.
- the simple dual port memory is realized with a smaller area than a general full dual port memory.
- the adaptive equalizer 1700 when using a single port memory includes a determination unit 108, an error extraction unit 109, a first adder 117, a first memory 1701, a second memory 1702, and a third Memory 1703, fourth memory 1704, fifth memory 1705, first selection unit 1706, first data conversion unit 1707, FFT / IFFT operation unit 1708, and second data conversion unit 1709 And a switching unit 1710, a second selection unit 1711, a sixth memory 1712, a seventh memory 1713, and an FFT operation unit 1714.
- FIG. 17 parts having the same configuration as in FIG. 15 are denoted by the same reference numerals and description thereof is omitted.
- the first selection unit 1706 selects the first memory 1701, the third memory 1703, or the fifth memory 1705, and reads or writes data.
- the FFT / IFFT calculation unit 1708 performs FFT calculation, IFFT calculation, or multiplication.
- the second data conversion unit 1709 performs multiplication processing of the FFT result and the time constant, complex conjugation, or the like.
- the switching unit 1710 switches between the output to the first selection unit 1706 and the output to the second selection unit 1711 of the addition result input from the first adder 117.
- the sixth memory 1712 stores the FFT result or the IFFT result.
- the FFT operation unit 1714 performs an FFT operation.
- the calculation of the FFT calculation unit 1714 corresponds to the calculation performed by the second FFT unit 111.
- the calculation performed by the second multiplier 112 (see FIG. 15) is performed by combining the FFT result stored in the sixth memory 1712 or the seventh memory 1713 and the FFT result stored in the first memory 1701. Corresponds to the operation of multiplying the conjugate.
- Multiplication corresponding to the multiplication performed by the second multiplier 112 is performed in the FFT / IFFT arithmetic unit 1708.
- the multiplication result is stored in the third memory 1703.
- the FFT / IFFT operation unit 1708 is configured to be able to share the multiplier of the butterfly operation unit in multiplications other than FFT and IFFT.
- the processing corresponding to the processing performed by the second zero insertion unit 114 is performed by the second data conversion unit 1709.
- the FFT / IFFT arithmetic unit 1708 performs FFT of the multiplication result stored in the third memory 1703.
- the multiplication result stored in the third memory 1703 corresponds to the multiplication result in the third FFT unit 115.
- the data reciprocates between the third memory 1703 and the first memory 1701 five times. The result of the FFT is overwritten and saved in the third memory 1703.
- the FFT result stored in the third memory 1703 is multiplied by the updated time constant ⁇ in the second data converter 1709.
- the operation of multiplying the time constant ⁇ is sufficient by a simple process such as bit shift in order to reduce the circuit scale. Therefore, the operation of multiplying by the time constant ⁇ is performed in the second data conversion unit 1709.
- Data multiplied by the time constant ⁇ is added to past filter coefficients.
- past filter coefficients are stored in the fourth memory 1704.
- the data multiplied by the time constant ⁇ is added to the filter coefficient stored in the fourth memory 1704 in the first adder 117.
- the addition result is switched for each block by the switching unit 1710 and stored as a filter coefficient in the fifth memory 1705 on the opposite side to the fourth memory 1704.
- the filter coefficient stored in the fifth memory 1705 is multiplied by the calculation result stored in the first memory 1701 (the calculation result in the FFT / IFFT calculation unit 1708 already performed).
- the multiplication result is overwritten and saved in the third memory 1703.
- the multiplication result stored in the third memory 1703 is IFFT.
- This IFFT calculation corresponds to the calculation performed by the first IFFT unit 106 (see FIG. 15). Also, the IFFT calculation is performed in the FFT / IFFT calculation unit 1708 by replacing the setting of the FFT calculation with the setting of the IFFT calculation. In order to use the FFT operation unit as the IFFT operation, the memory access address control order may be reversed from that of the FFT.
- the data reciprocates between the third memory 1703 and the second memory 1702 five times. The calculation result in the first IFFT 103 is overwritten and stored in the third memory 1703 and output as an equalized result.
- the calculation result in the first IFFT 103 is output from the third memory 1703 in symbol units in order to perform the determination in the determination unit 108 and the error extraction in the error extraction unit 109.
- the extracted error is stored in the sixth memory 1712 of the FFT calculation unit 1714.
- the FFT computation unit 1714 performs computation by reciprocating data between the sixth memory 1712 and the seventh memory 1713.
- the calculation of the FFT calculation unit 1714 corresponds to the calculation performed by the second FFT unit 111.
- This calculation result is stored in the sixth memory 1712 or the seventh memory 1713.
- the above calculation in the FFT calculation unit 1714 can be performed in parallel at the same timing as the calculation in the FFT / IFFT calculation unit 1708 (the calculation corresponding to the calculation performed in the first FFT 103), as shown in FIG. It is.
- FIG. 18 is a block diagram showing a main part of the circuit configuration of adaptive equalizer 1500 according to the present embodiment.
- FIG. 18 shows a case where the wide bit simple dual port memory 1601 shown in FIG. 16 is used.
- FIG. 18 illustrates a circuit configuration (connection relationship between a memory and an arithmetic circuit) that realizes the adaptive equalizer 1500 according to the present embodiment.
- the first memory 1801 stores an FFT calculation result, an IFFT calculation result, or a filter coefficient.
- the second selection unit 1805 selects the FFT calculation result input from the FFT / IFFT calculation unit 1804 or the addition result input from the first adder 117 and outputs the selected result to the first memory 1801.
- the S / P unit 1806 converts the data input from the first selection unit 1803 from a serial data format to a parallel data format, and outputs the converted data to the first adder 117.
- the second memory 1807 stores the FFT result or the IFFT result.
- the FFT operation unit 1808 performs an FFT operation or an IFFT operation.
- FIG. 18 Comparing FIG. 17 with FIG. 18, the configuration of FIG. 18 reduces the number of memories (increases the address space per memory) and reduces the concentration of wiring compared to the configuration of FIG. .
- the address space of the wide bit simple dual port memory 1601 (see FIG. 16) is expanded.
- the update result obtained by performing the FFT on the filter coefficient is stored in an address space different from the address space for FFT operation and IFFT operation in the wide bit simple dual port memory 1601.
- the present embodiment is only connected to the same memory bank, and can prevent an increase in wiring area.
- a signal for delaying the result of the calculation in the first FFT unit 103 by one block is an address space obtained by further expanding the address space of the wide bit simple dual port memory 1601 more than twice. Save to.
- FIG. 19 is a block diagram showing a main part of a modified example of the circuit configuration of adaptive equalizer 1500 according to the present embodiment.
- wide bit simple dual port memories 1601a and 1601b are used, and the number of memory accesses is halved.
- a rotor wide bit memory 1902 and a rotor register group 1903 are added. Further, in the configuration of FIG. 19, as compared with FIG. 5, instead of the first wide bit memory 201 and the second wide bit memory 207, wide bit simple dual port memories 1601a, 1601b having an address space twice as large. Have
- the rotor wide bit memory 1902 has the same configuration as the rotor wide bit memory 208, and the rotor register group 1903 has the same configuration as the rotor register group 209.
- the wide bit simple / dual port memories 1601a and 1601b have the same configuration as the wide bit simple / dual port memory 1601, and the description thereof will be omitted.
- the memory configuration for storing the data obtained by FFT of the filter coefficient, the data obtained by FFT of the reception signal one block before, etc. is preferable if the address space of the wide bit simple dual port memories 1601a and 1601b is expanded more than twice. It is.
- FIG. 20 is a block diagram showing a configuration around the memory of the adaptive equalizer when a single port memory is used.
- the adaptive equalizer using the single port memory includes the third multiplier 116, the first adder 117, the FFT result single port memory 2001 storing the FFT result, and the first switching.
- Unit 2002 a first single port memory 2003 for storing filter coefficients, a second single port memory 2004 for storing filter coefficients, and a second switching section 2005.
- parts having the same configuration as in FIG. 15 are denoted by the same reference numerals and description thereof is omitted.
- the FFT result single port memory 2001 corresponds to, for example, the second wide bit memory 207 in FIG.
- the FFT result single port memory 2001 stores the input FFT result.
- the first switching unit 2002 outputs the addition result input from the first adder 117 to the first single port memory 2003 or to the second single port memory 2004.
- the first single port memory 2003 stores the FFT result input from the first switching unit 2002.
- the second single port memory 2004 stores the FFT result input from the first switching unit 2002.
- the second switching unit 2005 selects the FFT result stored in the first single port memory 2003 and the FFT result stored in the second single port memory 2004 to select the first adder 117. Output to.
- the FFT result single port memory 2001 corresponds to, for example, the second wide bit memory 207 in FIG.
- the FFT result single port memory 2001 stores the FFT results for the updated filter coefficients.
- FFT result The FFT result stored in the single-port memory 2001 is read when the coefficient is updated.
- the third multiplier 116 multiplies the FFT result stored in the FFT result single port memory 2001 by the updated time constant ⁇ .
- the first adder 117 the output from the first single port memory 2003 or the second single port memory 2004 in which the FFT results of the past filter coefficients are accumulated, and the third multiplier 116
- the multiplication result is added.
- the addition result is written in the memory bank on the opposite side of the read single-port memory bank from the first single-port memory 2003 and the second single-port memory 2004.
- the switching between the first single port memory 2003 and the second single port memory 2004 in the first switching unit 2002 and the second switching unit 2005 is performed in block units. Since the single port memory cannot read and write at the same time, it has to wait for the write clock cycle after the read clock cycle, and during that time, the next address cannot be read. For this reason, in the case of a single port memory, only one memory bank requires twice as many cycles. Accordingly, if the number of processing cycles is severely limited, two memory banks, the first single port memory 2003 and the second single port memory 2004, must be configured. That is, when an adaptive equalizer is configured with a single port memory, a plurality of memories of the first single port memory 2003 and the second single port memory 2004 are prepared in order to save the number of filter coefficient update cycles. There is a need.
- FIG. 21 is a block diagram showing a peripheral configuration of the memory of adaptive equalizer 1500 according to the present embodiment.
- an adaptive equalizer 1500 includes a third multiplier 116, a first adder 117, an FFT result single-port memory 2101 for storing FFT results, and a wide bit simple dual for storing filter coefficients.
- a port memory 2102. In FIG. 21, parts having the same configuration as in FIG.
- FFT result single port memory 2101 stores the input FFT result.
- the wide bit simple dual port memory 2102 stores the addition result input from the first adder 117.
- the wide bit simple dual port memory 1601 When the wide bit simple dual port memory 1601 is used as in this embodiment, only one memory bank such as the wide bit simple dual port memory 2102 is required. However, the wide bit simple dual port memory 2102 requires twice the address space. In the wide bit simple dual port memory 2102, switching is performed for each block between reading from the upper address and writing to the lower address and reading from the lower address and writing to the upper address.
- the wide bit simple dual port memory 2102 stores the FFT result for the filter coefficient update, which is the addition result in the first adder 117.
- the FFT result stored in the wide bit simple dual port memory 2102 is read when the filter coefficient is updated.
- the third multiplier 116 multiplies the FFT result stored in the FFT result single port memory 2101 by the updated time constant ⁇ .
- the first adder 117 adds the output from the wide bit simple dual port memory 2102 in which the FFT result of the past filter coefficient is stored and the multiplication result in the third multiplier 116. This addition result is written into the wide bit simple dual port memory 2102.
- the address space of the wide bit simple / dual port memory 1601 or the address space of the wide bit simple / dual port memories 1601a and 1601b is expanded.
- the configuration shown in FIG. 21 can be realized, so that there is no need for a new wiring as in the case of a single port memory.
- FFT results for filter coefficient updates can be stored on the wide bit simple dual port memory 1601a side
- FFT results of past filter coefficients can be stored on the wide bit simple dual port memory 1601b side.
- the accumulated FFT result and the updated filter coefficient can be read at the same time, and can be written into the wide bit simple dual port memory 1601b after performing an addition operation or the like.
- the next address can be read from both the wide bit simple dual port memories 1601a and 1601b at the same time, the number of cycles is not increased.
- not all of the FFT results for the filter coefficient update and the FFT results of the past filter coefficients are stored in one wide bit simple dual-port memory.
- the FFT results for the filter coefficient update and the FFT results for the past filter coefficients are stored in half in two wide bit simple dual-port memories.
- the FFT result for updating the filter coefficient and the FFT result for the past filter coefficient are stored separately in the two wide-bit simple dual-port memories 1601a and 1601b.
- the upper address and the lower address in the wide bit simple / dual port memory 1601a and the wide bit simple / dual port memory 1601b are arranged so as to be reversed. Thereby, in this Embodiment, filter coefficient update data and the past filter coefficient data can be read simultaneously.
- the data corresponding to the upper address is stored in the wide bit simple dual port memory 1601a.
- the data corresponding to the lower address of the FFT result of the past filter coefficient is stored in the wide bit simple dual port memory 1601b.
- the data corresponding to the lower address side of the FFT result of the filter coefficient updating unit is stored in the wide bit simple / dual port memory 1601a.
- the data corresponding to the upper address of the FFT result of the filter coefficient updating unit is stored in the wide bit simple / dual port memory 1601b.
- the past filter coefficients can be read from the wide bit simple dual port memory 1601b.
- the updated filter coefficient can be read from the wide bit simple dual port memory 1601b.
- past filter coefficients can be read from the wide bit simple dual port memory 1601a.
- FIG. 22 is a block diagram showing a main part of a further modification of the circuit configuration of adaptive equalizer 1500 according to the present embodiment.
- parts having the same configuration as in FIG. 22 are identical to FIG. 22.
- the memories 1801a and 1801b have the same configuration as the first memory 1801 except that the number of memory banks is doubled.
- the data converters 1802a and 1802b have the same configuration as the data converter 1802.
- the selection units 1803a and 1803b have the same configuration as the first selection unit 1803.
- the selection units 1805a and 1805b have the same configuration as the second selection unit 1805.
- the memories 1807a and 1807b have the same configuration as the second memory 1807 except that the number of memory banks is doubled. From the above, description of these configurations is omitted.
- the switching unit 2201 switches between the output of the addition result in the first adder 117 to the selection unit 1805a and the output to the selection unit 1805b.
- the selection unit 2202 selects any one of the data stored in the memory 1801a and the data stored in the memory 1801b, outputs the data to the determination unit 108, and outputs the data to the outside.
- Fig. 22 the number of memory accesses is reduced by half using a simple dual port memory. Comparing FIG. 18 and FIG. 22, although the number of memory banks is doubled, the memory access clock speed may be the same as the clock speed required for the butterfly operation of the FFT operation, and low power consumption is achieved. I can expect.
- this embodiment only one wide-bit simple dual-port memory that can simultaneously read and write signals for 2M samples to different addresses is provided. As a result, this embodiment can suppress an increase in the total number of wirings connecting between the memory and the logic and between the memory and the memory.
- the manner of sharing the circuit of the signal conversion unit is not limited to the example of each embodiment described above.
- the adaptive equalizer may be configured to share the first to third multipliers and the time domain filter multiplier.
- An adaptive equalizer has a signal conversion unit that performs at least one of a fast Fourier transform and an inverse fast Fourier transform in an adaptive equalizer that performs adaptive equalization processing on a time domain signal in a frequency domain.
- the signal conversion unit includes a memory capable of reading and writing a signal of 2M (M is a natural number) samples, 2M registers accessible to the memory, M butterfly calculation units, and the 2M pieces A switching control unit that switches a connection state between the register and the M butterfly computation units.
- the signal conversion unit includes two sets of the memory and the 2M registers
- the switching control unit includes fast Fourier transform / inverse fast Fourier transform.
- the connection state between the 2M registers of one set and the M butterfly operation units so that the role of the memory is switched between the output memory and the input memory for each stage of conversion.
- the connection state between the 2M registers of the other set and the M butterfly operation units is switched.
- the adaptive equalizer according to the present invention in the configuration described above, includes a first signal conversion unit as the signal conversion unit that performs fast Fourier transform, and a signal that has been subjected to fast Fourier transform by the first signal conversion unit.
- a second signal conversion unit as the signal conversion unit for performing inverse fast Fourier transform on the first signal conversion unit, the first signal conversion unit does not perform bit reverse rearrangement in the fast Fourier transform, The second signal conversion unit does not perform bit reverse rearrangement in the inverse fast Fourier transform.
- the signal conversion unit is a rotation that stores a rotator in each stage of fast Fourier transform / inverse fast Fourier transform and can read and write signals of M samples.
- the adaptive equalizer inputs the time-domain signal and connects the accumulation unit that sequentially accumulates a predetermined block size, and the previously accumulated block and the latest block.
- An inter-block connecting unit, a first fast Fourier transform unit as the signal converting unit that performs fast Fourier transform on the output of the inter-block connecting unit, and an output and frequency domain of the first fast Fourier transform unit A first multiplier that multiplies the adaptive equalizer coefficient converted into the first multiplier, and a first inverse fast Fourier transform unit as the signal transforming unit that performs an inverse fast Fourier transform on the output of the first multiplier
- a block extraction unit that extracts the latest signal sequence block from the output of the first inverse fast Fourier transform unit, and an error that extracts an error from the ideal signal point from the output of the first inverse fast Fourier transform unit
- Fast Fourier transform is performed on the output of the output unit, the first zero insertion unit that zeros a portion other than the desired tap coefficient in the extracted error series, and the second
- the adaptive equalizer according to the present invention further includes a time-domain filter unit that performs a decision feedback type equalization process on the output of the first inverse fast Fourier transform unit in the configuration described above. At least one of the multipliers used in the butterfly computing unit of the third fast Fourier transform unit and the first and second inverse fast Fourier transform units is shared with the convolution computation multiplier of the time domain filter unit. It has become.
- the adaptive equalizer according to the present invention has at least one of the multipliers used in the butterfly computing unit of the first to third fast Fourier transform units and the first and second inverse fast Fourier transform units in the configuration. One is shared with at least one of the first to third multipliers.
- the adaptive equalizer according to the present invention further includes a time-domain filter unit that performs a decision feedback type equalization process on the output of the first inverse fast Fourier transform unit in the configuration described above. At least one of the registers of the third fast Fourier transform unit and the first and second inverse fast Fourier transform units is shared with the register of the time domain filter unit.
- the adaptive equalizer according to the present invention is provided in a receiving apparatus having a multicarrier demodulation unit in the above configuration, and the memory is shared with the memory of the multicarrier demodulation unit.
- the adaptive equalizer according to the present invention includes an address conversion unit, a serial / parallel conversion unit, and a parallel / serial conversion unit in the above configuration, and an input / output unit that controls input / output of signals of the memory, and the memory And a control unit that switches the configuration of the input / output unit according to whether the access method is random or continuous.
- the input / output unit receives data of 2M samples from the memory before writing in a write mode in a case where a method of accessing the memory is random. Reading and data overwriting are performed only on a predetermined position of the memory.
- the signal conversion unit includes one memory that can simultaneously read and write signals of 2M samples at different addresses.
- the present invention is useful as an adaptive equalizer that can suppress an increase in circuit scale and an operation clock frequency in an adaptive equalizer that performs an adaptive equalization process on a signal in the time domain in the frequency domain.
- the present invention is suitable for an adaptive equalizer of a receiving apparatus that supports multilevel VSB (Vestigial Sideband) modulation, which is employed in ATSC and the like.
- the present invention is suitable for various digital adaptive equalizers such as a speech echo canceller and a noise canceller that require a large number of taps in addition to an adaptive equalizer for wireless transmission.
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Abstract
Description
図1は、本発明の実施の形態1に係る適応等化器の構成を示すブロック図である。
<1024の関係から、少なくとも1024ポイントが必要である。すなわち、416/5=83.2シンボルに1度の割合で、1024ポイントの高速フーリエ変換/逆高速フーリエ変換の演算を完了させる必要がある。
本発明の実施の形態2は、時間領域処理による判定帰還型のフィードバックフィルタ(以下「時間領域フィルタ」という)を配置し、信号変換部の乗算器およびレジスタを、時間領域フィルタの乗算器およびレジスタと共用にした例である。
本発明の実施の形態3は、信号変換部のワイドビットメモリを他の装置部のメモリと共用にした例である。
本発明の実施の形態4は、メモリ-ロジック間及びメモリ-メモリ間を接続する配線の総本数の増大を抑えた例である。
101 蓄積部
102 ブロック間連結部
103 第1のFFT部
104 複素共役部
105 第1の乗算器
106 第1のIFFT部
107 ブロック抽出部
108 判定部
109 誤差抽出部
110 第1のゼロ挿入部
111 第2のFFT部
112 第2の乗算器
113 第2のIFFT部
114 第2のゼロ挿入部
115 第3のFFT部
116 第3の乗算器
117 第1の加算器
118 第1の遅延部
120、120a 第1の係数更新部
131a 時間領域フィルタ
132a 第2の加算器
141a 第4のFFT部
142a 第4の乗算器
143a 第3のIFFT部
144a 第5の乗算器
145a 第3の加算器
146a 第2の遅延部
200 信号変換部
201 第1のワイドビットメモリ
201a、201b、207a、207b ワイドビットメモリ
202 第1のレジスタ群
202a、202b、206a、206b レジスタ群
203 第1の接続切替部
204 バタフライ演算部群
205 第2の接続切替部
206 第2のレジスタ群
207 第2のワイドビットメモリ
208 回転子用ワイドビットメモリ
209 回転子用レジスタ群
310a フィルタ演算部
311a、321a、413a 乗算器
312a、521a レジスタ
313a、323a、411a、412a 加算器
320a 第2の係数更新部
322a ステップサイズ係数乗算器
324a レジスタ
410a バタフライ演算部
414a 第1の切替部
420a 回転子レジスタ
430a 第2の切替部
440a 第3の切替部
450a、540a、550a、560a 制御部
500a レジスタ群配置部
510a レジスタ入力側切替部群
511a レジスタ入力側切替部
520a レジスタ群
530a レジスタ出力側切替部群
531a レジスタ出力側切替部
610b ワイドビットメモリ
620b アドレス変換部
630b シリアル/パラレル変換部
640b パラレル/シリアル変換部
650b ATSC/OFDM切替部
660b Mカウンタ
Claims (12)
- 時間領域の信号に対する適応等化処理を周波数領域で行う適応等化器において、
高速フーリエ変換および逆高速フーリエ変換の少なくとも1つを行う信号変換部を有し、
前記信号変換部は、
2M(Mは自然数)サンプル分の信号を読み書きすることができるメモリと、
前記メモリにアクセス可能な2M個のレジスタと、
M個のバタフライ演算部と、
前記2M個のレジスタと前記M個のバタフライ演算部との間の接続状態を切り替える切替制御部と、を有する、
適応等化器。 - 前記信号変換部は、
前記メモリと前記2M個のレジスタとの組を2組有し、
前記切替制御部は、
高速フーリエ変換/逆高速フーリエ変換のステージごとに、前記メモリの役割が、出力用メモリと入力用メモリとの間で切り替わるように、一方の組の前記2M個のレジスタと前記M個のバタフライ演算部との間の接続状態、および、他方の組の前記2M個のレジスタと前記M個のバタフライ演算部との間の接続状態を切り替える、
請求項1記載の適応等化器。 - 高速フーリエ変換を行う前記信号変換部としての第1の信号変換部と、前記第1の信号変換部により高速フーリエ変換が行われた信号に対して逆高速フーリエ変換を行う前記信号変換部としての第2の信号変換部と、を有し、
前記第1の信号変換部は、
高速フーリエ変換におけるビットリバースの並べ替えを実施せず、
前記第2の信号変換部は、
逆高速フーリエ変換におけるビットリバースの並べ替えを実施しない、
請求項2記載の適応等化器。 - 前記信号変換部は、
高速フーリエ変換/逆高速フーリエ変換の各ステージにおける回転子を格納した、Mサンプル分の信号を読み書きすることができる回転子用メモリと、
前記回転子用メモリにアクセス可能であって、前記回転子を取得して前記M個のバタフライ演算部へ渡すM個の回転子用レジスタと、を更に有する、
請求項1記載の適応等化器。 - 前記時間領域の信号を入力し、逐次的に所定のブロックサイズ分を蓄積する蓄積部と、
前回蓄積されたブロックと最新のブロックとを連結するブロック間連結部と
前記ブロック間連結部の出力に対して高速フーリエ変換を行う前記信号変換部としての第1の高速フーリエ変換部と、
前記第1の高速フーリエ変換部の出力と周波数領域に変換された適応等化器係数とを乗じる第1の乗算器と、
前記第1の乗算器の出力に対して逆高速フーリエ変換を行う前記信号変換部としての第1の逆高速フーリエ変換部と、
前記第1の逆高速フーリエ変換部の出力から最新の信号系列ブロックを抽出するブロック抽出部と、
前記第1の逆高速フーリエ変換部の出力から理想信号点との誤差を抽出する誤差抽出部と、
抽出された前記誤差の系列のうち、所望のタップ係数以外の箇所をゼロにする第1のゼロ挿入部と、
前記第2のゼロ挿入部の出力に対して高速フーリエ変換を行う前記信号変換部としての第2の高速フーリエ変換部と、
前記第1の高速フーリエ変換部の出力の複素共役と前記第2の高速フーリエ変換部の出力とを乗じる第2の乗算器と、
前記第2の乗算器の乗算結果に対して逆高速フーリエ変換を行う前記信号処理部としての第2の逆高速フーリエ変換部と、
前記第2の逆高速フーリエ変換部の出力のうち、所望のタップ係数以外の箇所をゼロにするゼロ挿入部と、
前記第2のゼロ挿入部の出力に対して高速フーリエ変換を行う前記信号処理部としての第3の高速フーリエ変換部と、
前記第3の高速フーリエ変換部の出力と所定の係数とを乗じる第3の乗算器と、
前記第3の乗算器の出力を累積する累積部と、を有する、
請求項1記載の適応等化器。 - 前記第1の逆高速フーリエ変換部の出力に対して判定帰還型等化処理を行う時間領域フィルタ部、を更に有し、
前記第1~第3の高速フーリエ変換部および前記第1および第2の逆高速フーリエ変換部の前記バタフライ演算器で用いられる乗算器の少なくとも1つが、前記時間領域フィルタ部の畳込み演算用乗算器と共用となっている、
請求項5記載の適応等化器。 - 前記第1~第3の高速フーリエ変換部および前記第1および第2の逆高速フーリエ変換部の前記バタフライ演算器で用いられる乗算器の少なくとも1つが、前記第1~第3の乗算器の少なくとも1つと共用となっている、
請求項5記載の適応等化器。 - 前記第1の逆高速フーリエ変換部の出力に対して判定帰還型等化処理を行う時間領域フィルタ部、を更に有し、
前記第1~第3の高速フーリエ変換部および前記第1および第2の逆高速フーリエ変換部の前記レジスタの少なくとも1つが、前記時間領域フィルタ部のレジスタと共用となっている、
請求項5記載の適応等化器。 - マルチキャリア方式復調部を備えた受信装置に設けられ、
前記メモリは、
前記マルチキャリア方式復調部のメモリと共用となっている、
請求項1記載の適応等化器。 - アドレス変換部、シリアル/パラレル変換部、およびパラレル/シリアル変換部を含み、前記メモリの信号の入出力を制御する入出力部と、
前記メモリへのアクセス方法がランダムであるか連続であるかに応じて、前記入出力部の構成を切り替える制御部と、を更に有する、
請求項9記載の適応等化器。 - 前記入出力部は、
前記メモリへのアクセス方法がランダムである場合の書き込みモードにおいて、書き込みを行う前に前記メモリから2Mサンプル分のデータを読み出し、データの上書きを前記メモリの所定の位置に対してのみ行う、
請求項9記載の適応等化器。 - 前記信号変換部は、
前記2Mサンプル分の信号の読み込みと書き込みとを各々異なるアドレスに対して同時に実施可能な1つの前記メモリを有する、
請求項1記載の適応等化器。
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