WO2013098638A2 - Method and device for data buffering for multiple-stream - Google Patents

Abstract

The invention proposes a method of buffering for multi-stream, wherein, the read operation and write operation share one common buffer, the method comprises: I. performing read operation on the buffer to flush the content in a part of the addresses of the buffer; II. writing data into the part of addresses that have been flushed.

Description

Method and Device for Data Buffering for Multiple-Stream

Technical field

The invention relates to FFT/IFFT buffer, and more particular to method and device for data buffering for multiple- stream.

Background of the invention

Fast Fourier Transform (FFT) and Inverse Fast Fourier Transform (IFFT) are widely used in digital signal processing application such as digital communication, radar system and image processing and so on.

As number of parallel data stream increases and integration level of implemented system become higher, the silicon area occupied by FFT/IFFT related Very Large Scale Integrated Circuit (VLSI) implementation become not negligible any longer. A typical example is multiple stream FFT/IFFT application in Multi-Input Multi-Output- Orthogonal Frequency Division Multiplexing (MIMO-OFDM) communication system. To implement high throughput FFT or IFFT, technical requirements are raised to satisfy higher data throughput with cost and area effective VLSI design methodology. Pipeline-based FFT/IFFT is a preferred way for high data throughput application because of its advantage of minimized silicon area and maximized processing efficiency. However, for efficient use of the kind of Pipeline FFT/IFFT architecture, continuous input data streams are required and buffer has to been used to balance different data rate and data format between input data and output data of FFT/IFFT. The buffer will consume large number of memory and the size is proportional to number of parallel data streams.

Fig. 1 shows the frequently used Ping-Pong buffer based multiple- stream FFT system. In multiple-stream FFT-based system, simultaneous parallel FFT symbols are converted to one serial high-throughput FFT stream by Parallel-to-Serial converter, then to feed one pipeline FFT processor in pipelined way, as shown in Fig . 1. In order to continuously process current stream and next stream, two buffers for even stream and odd stream are usually used to unload current serial stream in pipelined way, collect and load next parallel FFT symbols at the same time. This kind of buffer pair is often named as ping-pong buffer or double buffer.

On the other hand, the counterpart is multiple stream IFFT-based system, a ping-pong buffer is also needed to unload current parallel IFFT symbols, load next serial stream simultaneously. Fig. 2 shows the frequently used IFFT system based on Ping-Pong buffer.

Summary of the invention

In this description, a compact FFT/IFFT buffer is designed in multiple-stream FFT/IFFT system to replace conventional ping-pong buffer or double buffer. A new memory addressing scheme is designed to save the memory size by 50% compared with ping-pong buffer.

According to a first aspect of the present invention, there is provided a method of buffering for multi-stream, wherein, the read operation and write operation share one common buffer, the method comprises: I. performing read operation on the buffer to flush the content in a part of the addresses of the buffer; II. writing data into the part of addresses that have been flushed.

According to a second aspect of the present invention, there is provided a data buffer device for multi-stream, the read operation and write operation share one common buffer, the device comprises:

- reading unit, for performing read operation on the buffer to flush the content in a part of the addresses of the buffer;

- writing unit, for writing data into the part of addresses that have been flushed.

By using the solution of the present invention, only one buffer is needed which save 50%) buffer size compared with the ping-pang buffer.

Brief description of drawings

Features, aspects and advantages of the present invention will become obvious by reading the following description of non-limiting embodiments with the aid of appended drawings.

Fig. 1 shows the frequently used Ping-Pong buffer based multiple- stream FFT system in the prior art;

Fig. 2 shows the frequently used Ping-Pong buffer based multiple- stream IFFT system in the prior art;

Fig. 3 shows a schematic flow chart of the multiple- stream FFT system according to an embodiment of the present invention;

Fig. 4 shows a multiple- stream FFT system according to an embodiment of the present invention;

Fig. 5 shows a multiple- stream FFT system according to an embodiment of the present invention;

Fig. 6-Fig. 8 show a schematic view for FFT buffer for 4-stream 16-point FFT.

Wherein, same or similar reference numerals refer to the same or similar steps or means.

Detailed description of embodiments

Normally there are multiple low data rate FFT/IFFT symbols which are transferred at the same time for multiple-stream system. It is assumed that the number of multiple low rate FFT/IFFT symbols is M. Without loss of generality, if one high-throughput FFT/IFFT processor is used, its sample rate is required to be more than M times of sample rate of one of parallel FFT/IFFT symbols so as to satisfy the total throughput requirement of system. Here possible overhead are excluded, for example, in some FFT/IFFT based system, like OFDM-based modulation or demodulation, some data overhead like cyclic prefix (CP) or data gap are introduced in the system.

Pipeline FFT/IFFT processor need to work symbol by symbol continuously so as to achieve maximized efficiency. With regard to pipeline FFT/IFFT processor, referring to Fig. 4, for FFT system, it works by unloading symbol serially from buffer and at the same time incoming multiple symbols are loaded into buffer.

As shown in Fig. 5, accordingly pipeline IFFT processor works and loads symbol serially into buffer and simultaneously multiple low rate symbols are unloaded from the buffer. The proposed scheme is to use the same buffer when loading incoming data by reusing the available memory space which has been unloaded at the same time, that is to say, loading data (perform write operation to the buffer) and unloading data (performing read operation to the buffer) use the same buffer. Fig. 3 shows a schematic flow chart of the multiple- stream FFT system according to an embodiment of the present invention. Wherein, four streams are alternately written into the buffer in parallel, while these data are read out in serial.

The folio wings give the description of the buffer entity and corresponding addressing control scheme. A geometric model is also illustrated as example of buffering four simultaneous 16-Point symbols' FFT processing shown in Fig. 6(a)- Fig. 8(b).

It is assumed that the Number of parallel stream is denoted as ^ = 2^m _? sample size of FFT symbol is denoted as N = 2" _? and bit-width of each sample is denoted as B . So the total buffer memory size can be computed as

BufferDepth = M N = 2^m+"

BufferWidth = B (bits)

BufferSize = 2^m+n B (bits)

In order to guarantee simultaneous write and read operation, a buffer which has individual write port and read port with different address has to be used in this kind of application.

The address of write port is expressed with binary encoding style as Addra = a[m + n - a[m + n - 2],...,a[ ] _{^ among which} Aj = aj[n - 1], ...,a [0] _{are used for} addressing N samples and ^ ^{~ a}^ ^{m ~} Ό >^■■■ > 3/ [0] _{are use(}j _{or a(}jd_ressmg M parallel streams.

Accordingly the address of read port is expressed as ^Addrb = b[m + n - ^,b[m + n - 2],...,b[0]

The addressing scheme is described as below:

Proposed Pipeline FFT/IFFT buffer addressing control :

Stagel : Initialization

At the first time to buffer incoming data, initialize the address of stream 0 with

write : Addra₀ = Aj,Ak

read : Addrb₀ = Addra₀

Stage2 : Iteration

For the data buffering of stream ' , ^ and Ak _in write address are circularly shifted by ^m bits compared with those of stream ' - 1 . Whether the circular shift is left shifted or right shifted are decided by FFT or IFFT application. For the i-th stream, the address is expressed as

[Addra, = CircularLeftShiftlAddra: m), for FFT processing write : <

[Addra_i = CircularRightShift(Addra_i __v m), for IFFT processing read : Addrty = Addra_{ Stage3 : Reinitialization

During the time when FFT operation become idle, reinitialize the read and write address as initial value. This is especially useful when FFT buffer is needed to be initialized periodically.

write : Addra₀ = Aj,Ak

read : Addrb₀ = Addra₀

denote 9^cd(x,y) _{as me} g_reatest common divisor of integer number x and y, and denote the iteration number of the address which can automatically return to initial value as P , then

P can be computed as:

p _ n ⁺ m

gcd(n + m,m)

So intentional periodical initialization or automatic initialization are both feasible and the selection is implementation specific.

The figures 6-8 are show below to illustrate an example of proposed FFT buffer for 4-stream 16-point FFT. A cubic geometric model is used as description of FFT buffer, and index A is used to indicate different stream and index S is to indicate different sample. Here P is equal to 3, so 3 iterations are needed for different write/read addressing, after that this kind of addressing pattern are repeated periodically. The figure show that if the current stream's read operation and next stream's write operation happen simultaneously, the memory access collision can be avoided effectively. Figure 6 (a) and (b) represent that write/read addressing of stream index, mod(index,3) = 0; Figure 7 (a) and (b) represent that write/read addressing of stream index, mod(index,3) = 1 and Figure 8 (a) and (b) represent that write/read addressing of stream index, mod(index,3) = 2.

As shown in Fig. 6(a), write operation is first carried out to the buffer. The write operation is carried out along the z axis, sequentially write into 16 addresses. First, 16 addresses A0S0-A0S3 , A1 S0-A1 S3 , A2S0-A2S3 , A3S0-A3S3 are written in parallel, then another 16 addresses A0S4-A0S7 , A1 S4-A1 S7 , A2S4-A2S7 , A3S4-A3S7 are written in parallel; then another 16 addresses A0S8-A0S 1 1 . A1 S8-A1 S 1 1 , A2S8-A2S 1 1 , A3S8-A3S 1 1 , are written in parallel; then another 1 6 addresses A0 S 12-A0S 15 , A1 S 12-A1 S 15 , A2S 12-A2S 15 , A3S 12-A3S 15 are written in parallel.

Then, as shown in Fig. 6(b), the written data is read out in serial along the x axis, and the part of flushed addresses are written according to predetermined sequence. First, the 16 addresses A0S1 , A0S2 AOS 15 are read out in serial. After these 16 addresses are flushed, the 16 flushed addresses are again written with A0S0-A0S3 , A1S0-A1S3 ,

A2S0-A2S3 , A3S0-A3S3 in parallel. Then, the 16 addresses Al SI , A1S2 A1S15 are read out in serial. After these 16 addresses are flushed, the 16 flushed addresses are again written with A0S4-A0S7 ,A1S4-A1S7 , A2S4-A2S7 , A3S4-A3S7 in parallel. Then, the 16 addresses A2S1 , A2S2 A2S15 are read out in serial. After these 16 addresses are flushed, the 16 flushed addresses are again written with A0S8-A0S11 , A1S8-A1S11 , A2S8-A2S11 ,A3S8-A3S11 in parallel. Then, the 16 addresses A3 SI ,A3S2 A3S15 are read out in serial. After these 16 addresses are flushed, the 16 flushed addresses are again written with AOS 12- AOS 15 , A1S12-A1S15 , A2S12-A2S15 , A3S12-A3S 15 in parallel.

Then, as shown in Fig.7(b), the written data is read out in serial along the y axis, and the part of flushed addresses are written according to predetermined sequence. First, the 16 addresses A0S1 , A0S2 AOS 15 are read out in serial. After these 16 addresses are flushed, the 16 flushed addresses are again written with A0S0-A0S3 , A1S0-A1S3 ,

A2S0-A2S3 , A3S0-A3S3 in parallel. Then, the 16 addresses A1S1 , A1S2 A1S15 are read out in serial. After these 16 addresses are flushed, the 16 flushed addresses are again written with A0S4-A0S7 ,A1S4-A1S7 , A2S4-A2S7 , A3S4-A3S7 in parallel. Then, the 16 addresses A2S1 , A2S2 A2S15 are read out in serial. After these 16 addresses are flushed, the flushed part of addresses are again written with A0S8-A0S11 , A1S8-A1S11 ,

A2S8-A2S11 ,A3S8-A3S11 in parallel. Then, the 16 addresses A3S1 ,A3S2 A3S15 are read out in serial. After these 16 addresses are flushed, the flushed part of addresses are again written with AOS 12-A0S15 , A1S12-A1S15 , A2S12-A2S15 , A3S12-A3S15 in parallel. The buffer after the operation is shown in Fig.8(a).

Then, as shown in Fig.8(b), the written data is read out in serial along the z axis, that is to say, first, the 16 addresses A0S1 , A0S2 A0S15 are read out in serial. After these 16 addresses are flushed, the 16 flushed addresses are again written with A0S0-A0S3 ,

A1S0-A1S3 ,A2S0-A2S3 .A3S0-A3S3 in parallel. Then, the 16 addresses A1S1 ,A1S2

A1S15 are read out in serial. After these 16 addresses are flushed, the 16 flushed addresses are again written with AO S4-A0S7 , A1S4-A1S7 , A2S4-A2S7 , A3S4-A3S7 in parallel. Then, the 16 addresses A2S 1 , A2S2 A2S 15 are read out in serial. After these 16 addresses are flushed, the flushed part of addresses are again written with AOS 8- AOS 1 1 , A1 S8-A1 S 1 1 , A2S8-A2S 1 1 , A3S8-A3S1 1 in parallel. Then, the 16 addresses A3S 1 ,

A3S2 A3S 15 are read out in serial. After these 16 addresses are flushed, the flushed part of addresses are again written with A0S 12-A0S 15 , A1 S 12-A1 S 15 , A2S 12-A2S 15 , A3S 12-A3S 15 in parallel, after the above three round of cycle, the buffer restore to the initial state.

The above parts describe the method of the embodiments of the present invention. The folio wings will describe the device embodiments of the present invention.

The invention also discloses a data buffer device for multi-stream, the read operation and write operation share one common buffer, the device comprises: reading unit, for performing read operation on the buffer to flush the content in a part of the addresses of the buffer; writing unit, for writing data into the part of addresses that have been flushed.

The reading unit is further used for: performing, in serial, read operation on the buffer, to flush the content in the part of the addresses; and the writing unit is further used for: writing, in parallel, the data into the part of addresses.

The reading unit and the writing unit are configured for repeating its own operation respectively, until all content in the buffer is flushed, or until re-initialization of the buffer.

The buffer is used for FFT operation or IFFT operation, and the device further comprises: a re-initializing unit, for re-initializing the buffer when the FFT operation or IFFT operation is idle.

The device may further comprise a control unit, for determining the need to performing read operation or write operation to the buffer;

controlling the reading unit to perform its operation when read operation is needed to perform to the buffer;

controlling the writing unit to perform its operation when write operation is needed to perform to the buffer.

In another embodiment, the number of the streams written into the buffer is denoted as M = 2^m , the number of the samples of the FFT or IFFT written into the buffer is denoted N = 2" , the write address is denoted as Addra = a[m + n - ^,a[m + n - 2],...,a[0] , wherein Aj = aj[n - 1], ...,a/[0] denotes N samples, and Ak = a/ [m - 1], ..., a/ [0] denotes M streams, and the read address is denoted as Addrb = b[m + n - b[m + n - 2],...,b[0] , the re-initializing unit is used for:

- for stream 0, respectively initializing the write address as Addrao=Aj, Ak, and initializing the read address as Addrbo= Addrao;

the reading unit and the writing unit are further used for:

- for stream i,

with respect to write operation, the writing unit cyclic shifts address Addraui by m bit so as to obtain Addra and

with respect to read operation, the reading unit obtains the read address

Addrcii.

In another embodiment, the writing unit is further used for:

- left cyclic shifting address Addraui by m bit so as to obtain Addra when the buffer is used for FFT;

- right cyclic shifting address Addraui by m bit so as to obtain Addra when the buffer is used for IFFT.

Those ordinary skilled in the art could understand and realize modifications to the disclosed embodiments, through studying the description, drawings and appended claims. All such modifications which do not depart from the spirit of the invention are intended to be included within the scope of the appended claims. The word "comprising" does not exclude the presence of elements or steps not listed in a claim or in the description. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. In the practice of present invention, several technical features in the claim can be embodied by one component. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim

Claims

What is claimed is:

1. A method of buffering for multi-stream, wherein, the read operation and write operation share one common buffer, the method comprises:

I. performing read operation on the buffer to flush the content in a part of the addresses of the buffer;

II. writing data into the part of addresses that have been flushed.

2. A method according to claim 1, wherein, said step I further comprises:

- performing, in serial, read operation on the buffer, to flush the content in the part of the addresses;

said step II further comprises:

- writing, in parallel, the data into the part of addresses.

3. A method according to claim 1, further comprising:

- repeating said steps I and II, until all content in the buffer is flushed, or until re-initialization of the buffer.

4. A method according to claim 3, wherein the buffer is used for FFT operation or IFFT operation, and the re-initialization comprises:

- re-initializing the buffer when the FFT operation or IFFT operation is idle.

5. A method according to claim 1, further comprising the step before said step I:

- determining the need to performing read operation or write operation to the buffer;

- performing said step I when read operation is needed to perform to the buffer;

- performing said step II when write operation is needed to perform to the buffer.

6. A method according to claim 3, wherein the number of the streams written into the buffer is denoted as M = 2^m, the number of the samples of the FFT or IFFT written into the buffer is denoted N = 2" , the write address is denoted as Addra = a[m + n - ^,a[m + n - 2],...,a[0], wherein Aj = aj[n -1],...,a/[0] denotes N samples, and Ak = ak[m - \,...,ak[0] denotes M streams, and the read address is denoted as Addrb = b[m + n - b[m + n -2],...,b[0] , the method further comprises the step before said step I:

- for stream 0, respectively initializing the write address as Addrao=Aj, Ak, and initializing the read address as Addrbo= Addrao.

7. A method according to claim 6, wherein, repeating said steps I and II further comprises:

- for stream i,

with respect to write operation, cyclic shifting address Addraui by m bit so as to obtain Addra and

with respect to read operation, obtaining the read address

Addrai.

8. A method according to claim 7, wherein the cyclic shifting by m bit further comprises:

- left cyclic shifting address Addraui by m bit so as to obtain Addrau when the buffer is used for FFT;

- right cyclic shifting address Addraui by m bit so as to obtain Addrau when the buffer is used for IFFT.

9. A data buffer device for multistream, the read operation and write operation share one common buffer, the device comprises:

- reading unit, for performing read operation on the buffer to flush the content in a part of the addresses of the buffer;

- writing unit, for writing data into the part of addresses that have been flushed.

10. A device according to claim 9, wherein, said reading unit is further used for:

- performing, in serial, read operation on the buffer, to flush the content in the part of the addresses;

said writing unit is further used for:

- writing, in parallel, the data into the part of addresses.

1 1. A device according to claim 9, wherein:

the reading unit and the writing unit are configured for repeating its own operation respectively, until all content in the buffer is flushed, or until re-initialization of the buffer.

12. A device according to claim 1 1 , wherein the buffer is used for FFT operation or IFFT operation, and the device further comprises:

a re-initializing unit, for re-initializing the buffer when the FFT operation or IFFT operation is idle.

13. A device according to claim 9, further comprising:

- a control unit, for determining the need to performing read operation or write operation to the buffer ;

- controlling the reading unit to perform its operation when read operation is needed to perform to the buffer;

- controlling the writing unit to perform its operation when write operation is needed to perform to the buffer.

14. A device according to claim 11, wherein the number of the streams written into the buffer is denoted as M = 2^m , the number of the samples of the FFT or IFFT written in to the buffer is denoted N = 2" , the write address is denoted as Addra = a[m + n - ^,a[m + n - 2],...,a[0], wherein Aj = aj[n -1],...,a/[0] denotes N samples, and Ak = ak[m - \,...,ak[0] denotes M streams, and the read address is denoted as Addrb = b[m + n - 1] , b[m + n-2],..., b[0] , the re-initializing unit is used for:

- for stream 0, respectively initializing the write address as Addrao=Aj, Ak, and initializing the read address as Addrbo= Addrao;

the reading unit and the writing unit are further used for:

- for stream i,

with respect to write operation, the writing unit cyclic shifts address Addraui by m bit so as to obtain Addra and

with respect to read operation, the reading unit obtains the read address

Addrcii.

15. A device according to claim 14, wherein the writing unit is further used for:

- left cyclic shifting address Addraui by m bit so as to obtain Addra when the buffer is used for FFT;

- right cyclic shifting address Addraui by m bit so as to obtain Addra when the buffer is used for IFFT.