CN102122971B - Method for quickly capturing broadband carrier signal - Google Patents
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- CN102122971B CN102122971B CN 201110002622 CN201110002622A CN102122971B CN 102122971 B CN102122971 B CN 102122971B CN 201110002622 CN201110002622 CN 201110002622 CN 201110002622 A CN201110002622 A CN 201110002622A CN 102122971 B CN102122971 B CN 102122971B
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Abstract
The invention provides a method for quickly capturing a broadband carrier signal. The method is implemented by the following technical scheme which comprises the following steps of: (1) designing at least one direct digital synthesizer (DDS), a first in first out (FIFO) and a loop filter (LPF) in a field programmable gate array (FPGA), wherein the DDS is used for synthesizing local oscillator signals at different frequencies and performing down-conversion on an input signal; a frequency control word of the DDS is set by a digital signal processor (DSP); the FIFO is used for acquiring and storing the signal subjected to down-conversion, and the FIFO is controlled by the DSP; the LPF filters the signal which is subjected to down-conversion in a closed loop so as to adjust the frequency of the DDS; (2) setting a fast Fourier transform (FFT) operation length N in the DSP, dividing a signal bandwidth into M sections and calculating a control word corresponding to the central frequency of each section; designing an FFT operation program and a related logic control program by using a related function; and (3) calculating a Doppler value by using the operation programs and combining the preset local oscillator frequency, wherein the DSP inquires a carrier loop state in real time until a tracking receiver is locked. By the processing method combined with the FPGA and the DSP, the tracking receiver broadband carrier can be captured quickly and flexibly.
Description
Technical field
The invention relates to be mainly used in and finish binary channels or single channel track receiver, utilize Fourier transform (FFT) algorithm to realize the implementation method that bandwidth carrier is caught fast.
Background technology
At present, track receiver capturing carrier, tracking all are to adopt the fast Fourier transform (FFT) algorithm to realize, hope is under the low signal-to-noise ratio condition, and realization is caught fast to broadband signal, and this has just challenged speed, precision and the scope of FFT computing in the track receiver.Prior art mainly utilizes three kinds of methods to realize: a kind of is to utilize the embedded IP kernel of field programmable gate array chip (FPGA), and by its rich in natural resources realization FFT computing, but FPGA does not have realization floating-point operation truly, fixed-point calculation can reduce the FFT precision, and the fixed-point number dynamic range is little, overflow easily, the computing length of FFT is to FPGA built-in storage space requirement height simultaneously.Existing IP kernel configuration property is underaction also; Second method is to utilize the nextport universal digital signal processor NextPort (DSP) of being good at high-speed computation to realize the FFT computing, but the memory of DSP has limited the computing length of FFT greatly, and DSP serial process pattern has also influenced the FFT arithmetic speed.The third method is to adopt special-purpose FFT process chip, though speed can reach requirement, and its poor expandability.
Summary of the invention
In order to overcome FFT implementation method above shortcomings in the existing track receiver, the present invention proposes a kind of simple and flexible, is easy to expansion, the implementation method of the fft algorithm of the broadband of FPGA+DSP low signal-to-noise ratio fast carrier capture.To improve the track receiver acquisition sensitivity.
Above-mentioned purpose of the present invention can reach by following measure: a kind of method of catching the bandwidth carrier signal fast is characterized in that comprising the steps:
(1) in programmable gate array chip (FPGA), design at least one digital frequency synthesizer (DDS), at least one memory (FIFO) and a loop filter (LPF), DDS is in order to the local oscillation signal of synthetic different frequency, and utilizes the input signal of DDS to carry out down-conversion and frequency control word is set, FIFO be used for gathering and the storage down-conversion after signal, FIFO is controlled by DSP, LPF to the signal filtering after the down-conversion, thereby adjusts the frequency of DDS when closed loop;
(2) require and signal bandwidth according to signal to noise ratio, FFT computing length N is set in DSP, signal bandwidth is divided into the M section and calculates the control word of each section centre frequency correspondence, be used for presetting different local frequency fi for many times to FPGA, utilize correlation function design FFT operation program and interrelated logic control program, in order to carry out work such as status poll and startup FIFO read-write control signal;
(3) use the FFT operation program, calculate doppler values in conjunction with presetting local frequency, operation result is delivered to FPGA intercarrier ring, DSP inquires about the carrier wave ring status in real time, when the loop non-locking, carries out the FFT loop computation repeatedly, and loop-locking then enters tracking mode.
The present invention has following beneficial effect than prior art:
Be easy to expansion.The present invention is based on the FFT implementation method of FPGA+DSP, can effectively utilize logical resource and memory resource abundant in the FFT, under the situation that resource allows, it is N that memory depth is set, and can select to carry out the N point as required, the N/2 point, N/4 ... the FFT of different depth, the degree of depth is arranged by DSP.In the FFT calculating process, utilize the waveform viewing tool of DSP Integrated Development Environment CCS software to overflow in real time to judge and displacement is selected dynamic range expanded.
Simple and flexible.In described FFT computing, the computing length N can change flexibly, calculates minimum DOPPLER RESOLUTION according to the acquisition sensitivity of track receiver, can draw minimum length N in conjunction with sample rate, and N determines the minimum-depth of FIFO simultaneously.
Carry out the FFT computing in DSP, it is abundant to give full play to the DSP built-in function, and the high advantage of precision has been avoided complex work such as FFT computing inverted order.M FFT handles to need only in DSP and uses a simple Do statement, just can realize the FFT computing flexibly and effectively, makes track receiver under the low signal-to-noise ratio condition, realizes catching fast broadband signal.
Description of drawings
Below in conjunction with drawings and Examples invention is further specified.
Fig. 1 is that the FPGA+DSP system that the present invention proposes forms schematic diagram.
Fig. 2 is the control flow block diagram of DSP program of the present invention.
Embodiment
Consult Fig. 1.In following examples, the realization that realizes the fft algorithm that bandwidth carrier is caught fast be by design in FPGA digital signal processing module and the control program in the DSP unite realization.
In programmable gate array chip (FPGA), design a digital frequency synthesizer (DDS) in order to the local oscillation signal of synthetic different frequency, and utilize it that input signal is carried out down-conversion, the frequency control word of DDS is arranged by DSP; Design a mass storage (FIFO), for the signal after the collection down-conversion, FIFO is controlled by DSP; Design a loop filter (LPF), LPF to the signal filtering after the down-conversion, thereby adjusts the frequency of DDS when closed loop, and the open loop closed signal of LPF is controlled by DSP.Also can design two DDS during enforcement, one is exclusively used in down-conversion DDS, one when being exclusively used in carrier wave ring DDS, needn't carry out the open loop closed-loop control to the DSP loop in this case.
In DSP, require and signal bandwidth according to signal to noise ratio, FFT computing degree of depth N is set, signal bandwidth is divided into the M section and calculates the control word of each section centre frequency correspondence, utilize correlation function design FFT operation program and interrelated logic control program, be used for presetting different frequency f for many times to FPGA
iAnd startup FIFO read-write control signal.Behind the system initialization, before the FFT computing, DSP control open loop closed-loop control signal makes loop be in open loop situations, the DDS in the FPGA is arranged frequency control word, the local oscillator f that 70M intermediate frequency input signal and the DDS that presets produce
iI road output signal carry out down-conversion, start FIFO simultaneously and write enable signal, FIFO begins to sample and stores and prepare to deliver in the DSP, after collecting the N point data that presets as FIFO, notice DSP writes full, DSP closes FIFO and writes to enable to start and read to enable, run through the N point data, notice DSP reads sky FIFO, close that FIFO reads to enable and to the FIFO zero clearing, utilize the related libraries function to carry out the FFT computing, call the waveform viewing tool of DSP Integrated Development Environment CCS software, the sampled data that FIFO sends here is overflowed judgement and displacement selection in real time, carry out dynamic range expansion.After the FFT computing finishes for the first time, ask for the amplitude peak in the current operation result, storage amplitude peak and corresponding Doppler frequency value thereof, the doppler values of every section correspondence of computing need add the frequency of predetermined frequency control word correspondence, computing finishes FFT operation times counter and adds 1, DSP presets next frequency control word and carries out FFT computing next time to DDS then, and segmentation is computing repeatedly, circulates successively up to finishing M FFT computing.DSP is the amplitude peak of M FFT computing relatively, get the Doppler frequency of amplitude peak correspondence and deliver to DDS in the FPGA, controlling open loop closed-loop control signal simultaneously makes loop be in the closed loop state, the frequency of adjusting DDS is united in the FREQUENCY CONTROL value addition that the output of LPF and DSP preset makes it progressively to equal carrier frequency, 70M intermediate frequency input signal and the local oscillator f that adjusts back DDS generation
iQ road output signal carry out down-conversion, behind process certain time of integration of the t, integrated value and lock-in threshold compare, integrated value surpasses then locking signal output high level of lock door limit value, otherwise be low level, DSP inquiry integration judging module result, loop-locking then enters tracking mode, otherwise DSP carries out the FFT loop computation again until locking.
Described method, can the combined with hardware resource and acquisition sensitivity carrier frequency is carried out segmentation flexibly, before each FFT computing, DDS in the FPGA of DSP arranges frequency control word, input signal and respective frequencies are carried out mixing, FIFO samples and delivers to and prepare computing in the DSP then, calculates corresponding doppler values at last.The doppler values of every section correspondence of computing will add the frequency of predetermined frequency control word correspondence, and computing finishes to preset next frequency control word to DDS, thus segmentation repeatedly computing realize that bandwidth carrier catches.
System initialization.In DSP, at first according to signal to noise ratio requirement and signal bandwidth FFT computing length N is set, signal bandwidth is divided into the M section, and calculates the frequency control word of each section centre frequency correspondence, frequency control word Φ is according to formula Φ=f
i2
N/ f
ClkCalculate, wherein fi is required local frequency, f
ClkBe the DDS work clock, N is DDS accumulator length; FFT operation times counter is put 1, and control open loop closed-loop control signal makes loop be in open loop situations, finishes the initialization of relevant parameter.
Gather the down-conversion data.DSP presets the frequency control word Φ 1 of first frequency range centre frequency correspondence to the DDS in the fpga chip, DDS produces corresponding local frequency, its sinusoidal output as I road signal in order to 70M intermediate frequency input signal is carried out down-conversion, signal after the frequency conversion divides two-way, one the tunnel is input to the loop filter LPF module in the FPGA, and output does not have influence to system after the filtering under open loop situations; One the tunnel is input to FIFO, and FIFO is in the read-write that DSP sends over, and enables to start sampling under the control signal, and store sample, collects N point back and reports to DSP and write full signal, and DSP closes FIFO and writes to enable to open and read to enable, and begins to read the N point sampling of storing in the FIFO.
The FFT computing.After N point sampling in the FIFO is read out, on DSP, enter for spacing wave, DSP closes and reads enable signal, call the FFT subfunction simultaneously and start FFT computing for the first time, computing finishes, and the N point range value that calculates is asked absolute value, and get maximum with the bubbling method, record amplitude peak and corresponding Doppler frequency, calculating Doppler frequency is according to formula
F wherein
sBe sample frequency, f
iBe the centre frequency of current frequency range correspondence, k is counting of amplitude peak correspondence, owing to be that the data after the frequency conversion are carried out the FFT computing, so add the centre frequency f that presets
iBe only real Doppler frequency.
The FFT circulation.After finishing a FFT computing, the FFT operation times counter among the DSP adds 1 automatically, and DDS in the FPGA is preset the frequency control word of second frequency range centre frequency, and beginning is the FFT computing for the second time, circulates successively until finishing M FFT computing.M the amplitude peak that M the FFT computing of DSP draws compares, and gets the frequency control word of amplitude peak correspondence and inserts DDS, controls open loop closed-loop control signal simultaneously and makes loop be in the closed loop state.
The integration judgement.After closed loop, after the frequency control word of the amplitude peak correspondence that DSP sends here and the loop filter filtering after the output addition as the frequency control word of DDS, the I road signal of the local oscillation signal that produces enters loop filter again, loop filter is a low pass filter, the filtering high fdrequency component, keep low frequency component, make after the filtering output progressively near frequency input signal until with input signal with frequently, the cosine signal of the local oscillation signal after the adjustment of filtering simultaneously carries out the mixing integration as Q road signal and input signal, adjudicate with lock-in threshold behind the integration, surpass then loop-locking of thresholding, be lower than then losing lock of thresholding.
DSP inquiry and state control.Loop is through the certain t time of integration, and DSP inquires about court verdict, and loop-locking then enters tracking mode, enters the FFT loop computation until locking otherwise DSP starts associated control signal.
Consult Fig. 2.Concrete DSP implements control flow, according to signal to noise ratio requirement and signal bandwidth FFT computing length N is set, and signal bandwidth is divided into the M section, and calculates the control word of each frequency range centre frequency correspondence, and N and M are stored in DSP as constant.After start DSP starts, the initialization relevant parameter, the FFT operation times puts 1, and DDS in the FGPA is preset the centre frequency control word of first frequency range, opens the carrier wave ring simultaneously, starts FIFO and writes.FIFO gathers the signal of storage after first local frequency mixing.Collect after the N point data that presets notice DSP as FIFO and write fullly, DSP closes FIFO and writes to enable to start and read to enable, and runs through the N point data, closes that FIFO reads to enable and to the FIFO zero clearing, utilize the related libraries function to carry out the FFT computing simultaneously.After the FFT computing finishes, ask for the amplitude peak in the current operation result, storage amplitude peak and corresponding Doppler frequency value thereof, the FFT operation times adds 1, the DSP centre frequency control word that presets second frequency range is carried out the FFT computing second time then, circulates successively up to finishing M FFT computing.DSP is the amplitude peak of M computing relatively, getting the frequency of amplitude maximum correspondence sends the interior DDS of FPGA back to and closes the carrier wave ring, after waiting for loop process certain time of integration of t, integrated value and lock-in threshold court verdict in the DSP inquiry FPGA, loop-locking then enters tracking mode, otherwise DSP carries out the FFT loop computation again until locking.
Described method, can the combined with hardware resource and acquisition sensitivity carrier frequency is carried out segmentation flexibly, before each FFT computing, DDS in the FPGA of DSP arranges frequency control word, input signal and respective frequencies are carried out mixing, FIFO samples and delivers to and prepare computing in the DSP then, calculates corresponding doppler values at last.The doppler values of every section correspondence of computing will add the frequency of predetermined frequency control word correspondence, and computing finishes to preset next frequency control word to DDS, thus segmentation repeatedly computing realize that bandwidth carrier catches.
Above-described only is the preferred embodiments of the present invention.Should be understood that, for the person of ordinary skill of the art, under the prerequisite that does not break away from the principle of the invention, can also make some distortion and improvement, such as, from top description as can be seen, as long as resource is enough abundant in the FPGA, can design two DDS, one is exclusively used in down-conversion, one is exclusively used in the carrier wave ring, and DSP needn't carry out the open loop closed-loop control like this.Also can design M the identical input signal of FIFO of the degree of depth and carry out parallel sampling in FPGA, DSP carries out computing respectively and shortens capture time with this then, and these changes and change should be considered as belonging to protection scope of the present invention.
Claims (8)
1. a method of catching the bandwidth carrier signal fast is characterized in that comprising the steps:
(1) in programmable gate array chip (FPGA), design at least one digital frequency synthesizer (DDS), at least one First Input First Output data buffer (FIFO) and a loop filter (LPF), DDS is in order to the local oscillation signal of synthetic different frequency, and utilize the input signal of DDS to carry out down-conversion and frequency control word is set, FIFO is used for the signal after collection and the storage down-conversion, FIFO is controlled by digital signal processor (DSP), LPF is when closed loop, to the signal filtering after the down-conversion, thus the frequency of adjustment DDS;
(2) require and signal bandwidth according to signal to noise ratio, fast Fourier transform (FFT) computing length N is set in DSP, signal bandwidth is divided into the M section and calculates the control word of each section centre frequency correspondence, be used for presetting different local frequency f for many times to FPGA
i, utilize correlation function design FFT operation program and interrelated logic control program, in order to carry out status poll and to start the FIFO read-write control signal;
(3) use the FFT operation program, calculate doppler values in conjunction with presetting local frequency, operation result is delivered to DDS, DSP inquires about the carrier wave ring status in real time, when the loop non-locking, carries out the FFT loop computation repeatedly, and loop-locking then enters tracking mode.
2. method of catching the bandwidth carrier signal fast as claimed in claim 1, it is characterized in that before each FFT computing, the DDS in the FPGA of DSP arranges frequency control word, input signal and respective frequencies are carried out mixing, and FIFO samples and delivers to and prepare computing in the DSP then.
3. method of catching the bandwidth carrier signal fast as claimed in claim 1, it is characterized in that, after collecting the N point data that presets as FIFO, notice DSP writes full, DSP closes FIFO and writes to enable to start and read to enable, and runs through the N point data, closes that FIFO reads to enable and to the FIFO zero clearing, utilize the related libraries function to carry out the FFT computing simultaneously, and calculate corresponding doppler values.
4. method of catching the bandwidth carrier signal fast as claimed in claim 1, it is characterized in that, in DSP, utilize correlation function design fast Fourier transform (FFT) operation program, utilize the waveform viewing tool of DSP Integrated Development Environment CCS software, the sampled data that FIFO sends here is overflowed judgement and displacement selection in real time, and carry out dynamic range expansion.
5. method of catching the bandwidth carrier signal fast as claimed in claim 1 is characterized in that, the doppler values of every section correspondence of computing adds the frequency of predetermined frequency control word correspondence, and computing finishes to preset next frequency control word to DDS, and segmentation is computing repeatedly.
6. method of catching the bandwidth carrier signal fast as claimed in claim 1, it is characterized in that, after the FFT computing finishes for the first time, ask for the amplitude peak in the current operation result, storage amplitude peak and corresponding Doppler frequency value thereof, the FFT operation times adds 1, and the DSP centre frequency control word that presets second frequency range is carried out the FFT computing second time then, circulates successively up to finishing M FFT computing.
7. method of catching the bandwidth carrier signal fast as claimed in claim 1, it is characterized in that, DSP is the amplitude peak of M FFT computing relatively, get the Doppler frequency of amplitude peak correspondence and deliver to DDS in the FPGA, after waiting for loop process certain time of integration of t, inquiry FPGA intercarrier ring status, loop-locking then gets the hang of and inquires about circulation, otherwise DSP carries out the FFT loop computation again until locking.
8. method of catching the bandwidth carrier signal fast as claimed in claim 1 is characterized in that, when one of design is exclusively used in down-conversion DDS, one when being exclusively used in carrier wave ring DDS, DSP does not carry out open loop, closed-loop control.
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| CN103186476B (en) * | 2011-12-30 | 2017-07-28 | 上海贝尔股份有限公司 | A kind of data cache method and device for multithread |
| CN102594393B (en) * | 2012-01-29 | 2013-12-25 | 北京航空航天大学 | Universal pseudocode synchronization system of comprehensive satellite baseband equipment |
| CN102916722B (en) * | 2012-10-09 | 2015-04-22 | 中国电子科技集团公司第十研究所 | Method for generating high-precision frame synchronous pulse signal of spread spectrum receiver |
| CN103368484B (en) * | 2013-07-29 | 2015-09-30 | 周立人 | Motor motion control circuit and control method thereof |
| CN112462140B (en) * | 2021-02-02 | 2021-04-13 | 成都能通科技有限公司 | Frequency tracking method for providing electric energy parameter analysis |
| CN113595956A (en) * | 2021-09-10 | 2021-11-02 | 长光卫星技术有限公司 | Satellite measurement and control communication subcarrier synchronization method |
| CN117591065B (en) * | 2023-11-24 | 2024-06-18 | 北京国科天迅科技股份有限公司 | Signal processing circuit, signal processing method and signal processing chip |
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| US7266465B1 (en) * | 2005-11-09 | 2007-09-04 | Itt Manufacturing Enterprises, Inc. | Wideband digital IFM receiver with frequency confirmation |
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