CN106932794A - The hardware accelerator and method of a kind of satellite navigation baseband signal track algorithm - Google Patents
The hardware accelerator and method of a kind of satellite navigation baseband signal track algorithm Download PDFInfo
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- CN106932794A CN106932794A CN201710154587.5A CN201710154587A CN106932794A CN 106932794 A CN106932794 A CN 106932794A CN 201710154587 A CN201710154587 A CN 201710154587A CN 106932794 A CN106932794 A CN 106932794A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S19/00—Satellite radio beacon positioning systems; Determining position, velocity or attitude using signals transmitted by such systems
- G01S19/01—Satellite radio beacon positioning systems transmitting time-stamped messages, e.g. GPS [Global Positioning System], GLONASS [Global Orbiting Navigation Satellite System] or GALILEO
- G01S19/13—Receivers
- G01S19/24—Acquisition or tracking or demodulation of signals transmitted by the system
- G01S19/29—Acquisition or tracking or demodulation of signals transmitted by the system carrier including Doppler, related
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
- G06F15/7817—Specially adapted for signal processing, e.g. Harvard architectures
Abstract
The present invention relates to the hardware accelerator and method of a kind of satellite navigation baseband signal track algorithm, including data transmission module, data cache module, access control module, computing accumulator module and statistical module, computing accumulator module includes multiple computing summing elements.The step of hardware-accelerated method, is as follows：Hardware accelerator writes the NCS data of DFT data and last time computing before computing；Start DFT computings after the completion of data write-in；Hardware accelerator produces twiddle factor, carries out DFT computings parallel, then by DFT operation results it is cumulative updated after NCS data；Statistics is obtained according to the NCS data after DFT operation results and renewal, and by the NCS data transfers after renewal to base band SoC systems；Hardware accelerator stops computing and counts and produce hardware interrupts, and subsequent algorithm treatment is carried out after base band SoC systems response hardware interrupts.This programme can improve GNSS signal carrier track frequency domain frequency discrimination calculating speed, so as to improve system processing power.
Description
Technical field
The present invention relates to satellite navigation receiver digital signal processing chip technical field, more particularly to it is applied to satellite and leads
Boat receiver frequency domain carriers carry out the hardware accelerator and method of frequency domain frequency discrimination.
Background technology
GLONASS (Global Navigation Satellite System, GNSS) receiver it is main
Task is capture and tracking satellite signal, after signal transforms to baseband signal from radiofrequency signal, is completed by base band signal process
Navigator fix is resolved.
The capture of GNSS signal is searched for from signal is received, captures each visible gps satellite signal, and is therefrom defended
The carrier frequency and C/A code phase rough estimate values of star signal.In the tracking phase of GNSS signal, from defending that acquisition phase is obtained
Star signal(-) carrier frequency and code phase rough estimate value are set out, and multiple correlators are set centered on the code phase of initial estimation,
And carrier frequency is set to the carrier frequency of initial estimation, progressively finely two signal parameters are estimated by track loop
Meter, while output is to the various measured values of signal, then demodulates the navigation message bit in signal in passing.Track loop is general by phase
Close device, discriminator, loop filter composition.Wherein correlator is realized often through hardware, by the integral accumulation of integer number of milliseconds
Export and give loop discriminator, and loop discriminator is often realized with loop filter by software.Track loop is functionally divided into
Code tracking and carrier track, are respectively completed the accurate lock of range finding code phase and carrier frequency.
Carrying out carrier track need to be estimated frequency deviation using frequency discriminator, typically there is two methods：Using arc tangent
Function asks the phase difference that the correlator of adjacent time exports integrated value to obtain frequency divided by time interval, and another method is to utilize
Fast Fourier Transform (FFT) (Fast Fourier Transform, FFT) or discrete Fourier transform (Discrete Fourier
Transform, DFT) frequency domain is carried out to the integrated value of correlator continuous time point output it is converted to frequency spectrum and then frequency discrimination, it is latter
The method of kind differentiates that scope is obtained a wide range of applications because of bigger frequency.
Needed when frequency domain differentiates finding frequency spectrum maximum in the range of the frequency and correlator of regulation, then in maximum
Frequency discrimination obtains the fine values of offset estimation near value；Loop circuit state is monitored in addition is also required in certain pre-determined frequency
Rate and correlator scope are counted to the maximum Distribution value of frequency spectrum, that is, need to carry out multiple different frequencies and correlator scope
Maximum Data-Statistics.Due to being modulated with navigation message in GNSS signal, its coherent integration time is often limited, to improve signal to noise ratio,
Often carry out noncoherent accumulation；Additionally, the monitoring to loop also needs to calculate the average of frequency spectrum.Due to the meeting when DFT is calculated
Frequency spectrum is traveled through, maximum and average can be conveniently asked for, be calculated noncoherent accumulation value.
Amount of calculation can be saved relative to DFT using FFT, the amount of calculation of saving increases and increases with frequency number, but frequency
Number can not be chosen at random, and frequency interval is determined by frequency number, and to increase frequency domain resolution, fft algorithm requirement is to input time domain
Data padding, this can increase amount of calculation again, and when frequency number is less, the advantage that amount of calculation is saved is not obvious.During using DFT, can
Flexibly to select frequency interval and frequency number.Typical scene is tracked in view of GNSS signal, required frequency number is simultaneously little, now adopts
DFT schemes are used, zero padding is can be avoided, amount of calculation during practical application is suitable with FFT schemes, and can flexible configuration frequency interval
With frequency number.The present invention carries out frequency domain decomposition using DFT to the integrated value that correlator is exported.
It is current when carrying out frequency domain frequency discrimination and frequency discrimination using DFT, statistics and search for frequency spectrum maximum by Receiver Software or
Firmware realizes that DFT computings can be calculated using software or realized using DSP devices.It is low that software calculating realizes that DFT computings have speed
Defect；DSP devices realize that DFT computings can improve arithmetic speed, but cannot be realized in large scale integrated circuit, not enough spirit
It is living.Industry needs a kind of scheme of raising badly, to improve GNSS signal carrier track calculating speed, so as to improve system processing power.
The content of the invention
In order to overcome the above-mentioned deficiencies of the prior art, the invention provides a kind of satellite navigation baseband signal track algorithm
Hardware accelerator and method, it is possible to increase GNSS signal carrier track calculating speed, so as to improve system processing power, this hair
The bright technical scheme for solving above-mentioned technical problem is as follows：A kind of hardware accelerator of satellite navigation baseband signal track algorithm,
Including data transmission module, data cache module, access control module, computing accumulator module and statistical module, the computing is tired out
Plus module includes multiple computing summing elements, the data cache module is connected by data transmission module with base band SoC systems,
The computing accumulator module is connected with data cache module, the access control module respectively with base band SoC systems, data transfer
Module, data cache module, computing accumulator module are connected with statistical module, by the data transmission module by DFT data and
In the NCS data write-in data cache module of last time computing, access control module is produced and starts DFT computings after the completion of data write-in
Indication signal, computing accumulator module produces twiddle factor and carries out DFT fortune to DFT data parallels by multiple computing summing elements
Calculate, then new NCS data are obtained and NCS data to last time computing are updated by the cumulative of DFT operation results, count
Module obtains statistics according to the NCS data after DFT operation results and renewal, and data transmission module is again by the NCS after renewal
Data transfer returns base band SoC systems.
Further, also including data arbitration modules, the data cache module is passed by data arbitration modules with data
Defeated module, access control module, computing accumulator module are connected with statistical module, and data arbitration modules are used for before computing and statistics
The interface of data transmission module and data cache module carries out arbitration selection afterwards.
Further, also including interface configuration module, the access control module is by interface configuration module and base band SoC
System is connected.
Further, the data transmission module is connected by AHB host device interfaces with base band SoC systems.
Further, the data cache module includes DFT data cells and NCS data cells, and DFT data cells are used for
The DFT operation results are deposited, NCS data cells are used to deposit the NCS data.
A kind of hardware-accelerated method of satellite navigation baseband signal track algorithm, comprises the following steps：
1) DFT data and the NCS data of last time computing are stored in base band SoC systems in advance, and hardware accelerator is in fortune
The write-in of the NCS data of DFT data and last time computing is performed before calculating；
2) after the completion of DFT data and the NCS data of last time computing write, hardware accelerator refers to according to DFT computings are started
Show that signal starts DFT computings；
3) hardware accelerator reads DFT data, and produces twiddle factor by the parameter of software merit rating, by multiple computings
Summing elements carry out DFT computings parallel, then by DFT operation results it is cumulative updated after NCS data；
4) the NCS data after hardware accelerator counts DFT operation results and updates, according to DFT operation results and renewal
NCS data afterwards obtain statistics, and by the NCS data transfers after renewal to base band SoC systems；
5) after completing operation result statistics and NCS data transfers, hardware accelerator stops computing and counts and produce hard
Part is interrupted, and is read the NCS data after updating after base band SoC systems response hardware interrupts and is carried out subsequent algorithm treatment.
Further, the step 1) in, hardware accelerator writes DFT numbers by AHB host device interfaces with dma mode
According to the NCS data with last time computing.
Further, the step 3) in, the parameter of software merit rating specifically include correlator number, DFT computing frequencies number,
DFT computings sampling number and whether add up.
Further, the step 4) in, it is equal that statistics specifically includes energy peak, energy peak location and energy
Value.
Further, the step 4) in, statistics is present in hardware accelerator after obtaining statistics.
Beneficial effect using above-mentioned further scheme is：The present invention proposes a kind of frequency domain realized in on-chip system chip
The hardware accelerator and method of carrier track algorithm, specially carry out track algorithm time-frequency domain frequency discrimination in frequency domain to GNSS signal
DFT computings, while DFT operation results are counted, such as to searching for frequency spectrum maximum in the range of specified frequency and correlator,
And the circuit and performance for the hardware accelerator carry out height optimization, improve GNSS signal carrier track calculating speed, from
And improve system processing power.
Brief description of the drawings
Fig. 1 is the schematic diagram of hardware accelerator of the present invention；
Fig. 2 is the flow chart of hardware-accelerated method of the invention.
Specific embodiment
Principle of the invention and feature are described below in conjunction with accompanying drawing, example is served only for explaining the present invention, and
It is non-for limiting the scope of the present invention.
The hardware accelerator and method of a kind of satellite navigation baseband signal track algorithm, are applied to base band SoC systems, i.e.,
Baseband signal on-chip system chip System on Chip.Base band SoC systems mainly include microcontroller, baseband processing module with
And system RAM module, the base band SoC system special disposal GNSS intermediate-freuqncy signals of this hardware accelerator are integrated with, it is hardware-accelerated
Device is integrated in base band SoC systems with AMBA AHB interfaces.This hardware accelerator external interface uses AMBA AHB interfaces
And hardware interrupts indication signal, i.e. Advanced Microprocessor Bus Architecture Advanced Microcontroller Bus
Structure and Advanced High-performance Bus Advanced High-Performance Bus, interface are simple, can be straight in the form of IP modules
Connect and be integrated in base band SoC systems.AMBA AHB interfaces include AHB host device interfaces and AHB slave unit interfaces, add in this hardware
In speed variator, data transmission module 1 is connected by AHB host device interfaces with base band SoC systems, and interface configuration module 7 passes through AHB
Slave unit interface is connected with base band SoC systems.Data transfer is carried out by AHB host device interfaces, the software of hardware accelerator
Configuration is carried out by AHB slave units interface.The course of work and principle of hardware-accelerated method are as follows：
After the GNSS intermediate-freuqncy signals of input are through Signal Pretreatment, respectively by the trapping module of base band SoC systems and tracking mould
Each correlator coherent integration results that tracking module is exported can be write system by block treatment, the firmware program for running on microcontroller
In RAM module；
Firmware program will need the source data for carrying out DFT computings to pass through AHB slave units in the initial address of system RAM module
Interface configuration hardware accelerator inside related register, and configure other parameters such as correlator number, DFT computing frequencies
Number, DFT computing sampling numbers etc., last configuration register start DFT computings；
Hardware accelerator copies DFT computing source datas with dma mode by AHB host device interfaces from system RAM module
And DFT computing cumulative datas, after starting DFT computings and adding up, statistics is stored in data and delayed by programming count result of calculation
In storing module 2, and the NCS data of cumulative gained are copied back into system RAM module by AHB host device interfaces with dma mode, most
Interruption is produced afterwards；
After firmware program receives interruption, the NCS data of cumulative gained are directly read from system RAM module, and it is slow from data
Storing module 2 reads statistics, then carries out frequency domain tracking carrier wave ring algorithm, realizes the quick tracking of stabilization.
As shown in figure 1, a kind of hardware accelerator of satellite navigation baseband signal track algorithm, including data transmission module
1st, data cache module 2, access control module 3, computing accumulator module 4, statistical module 5, data arbitration modules 6 and interface configuration
Module 7.
Data transmission module 1 realizes the bursting data transfer between this hardware accelerator and base band SoC systems, reduces number
According to the time of moving, and realize that dma mode transmission data, the i.e. mode of Direct Memory Access directly access base band SoC
The system RAM module of system, without microcontroller intervention, improves performance.Specifically, realize carrying DFT fortune from base band SoC systems
Data cache module 2 inside the evidence that counts and NCS data to hardware accelerator, and the data from inside hardware accelerator
Cache module 2 reads the operation of the NCS data writing systems RAM modules after updating.Wherein, NCS data are the energy after DFT computings
Value accumulation result, i.e. non-coherent integration values.
Data cache module 2 include DFT data cells and NCS data cells, be respectively used to deposit DFT computings source data and
NCS data.
Access control module 3 realizes the SECO of this hardware accelerator and starts control, including single DFT computings
Or energy value after DFT computings it is cumulative when to the access control of data cache module 2.
Computing accumulator module 4 includes multiple computing summing elements；Specifically, computing accumulator module 4 includes that four computings are tired out
Plus unit, four DFT concurrent operations are realized, and by operation result Serial output, energy value is converted to, realize the energy that DFT is calculated
Value is cumulative and the NCS data of cumulative gained are write into data cache module 2.
Statistical module 5 realizes the statistics to the NCS data after DFT operation results and renewal, such as to specified frequency and phase
Close and frequency spectrum maximum is searched in the range of device.
Data arbitration modules 6 are realized carrying out arbitration selection to the interface of data transmission module 1 and data cache module 2.Firmly
When part accelerator needs write-in DFT data and the NCS data of last time computing, data arbitration modules 6 pass through data transmission module 1
DFT data and the NCS data of last time computing are write data cache module 2 from base band SoC systems；After the completion of write-in, work as hardware
When accelerator needs to carry out DFT computings, data arbitration modules 6 are DFT data and the NCS data of last time computing from data buffer storage
The write-in computing of module 2 accumulator module 4, the computing of computing accumulator module 4 obtains NCS data and handle after DFT operation results and renewal
The above results are stored to data cache module 2, and data arbitration modules 6 are passed the NCS data after renewal by data transmission module 1 again
Return base band SoC systems.
Interface configuration module 7 realizes configuration interface function, realize software to the register configuration of this hardware accelerator and
Query function.
As shown in Fig. 2 a kind of hardware-accelerated method of satellite navigation baseband signal track algorithm, is mainly summarised as following step
Suddenly：
1. before hardware accelerator work, the phase after the correlator computing of the various code phases of base band tracking module output
Dry integrated value is that NCS data have been stored in base band as the energy value accumulation result after DFT data, and the computing of last time DFT
DFT data and NCS data are stored in SoC systems, software the initial address of base band SoC systems, are write by AHB slave unit interfaces
Enter the interface configuration module 7 of this hardware accelerator, be reconfigured at other DFT operational parameters such as correlator number, DFT computing frequencies
Whether number, DFT computings sampling number and cumulative etc., finally configuration starts DFT computings；
2. the decoding of access control module 3 configuration register, produces DFT operation time sequence indication signals, DFT computings to be launched
When, control signal is sent to data transmission module 1, data transmission module 1 is automatically by AHB host device interfaces from base band SoC systems
System passes sequentially through burst transfer modes and copies DFT data and NCS data with dma mode, and is write firmly by data arbitration modules 6
Data cache module 2 inside part accelerator.After pending data has been copied, access control module 3 sends to computing accumulator module 4
Start the indication signal of DFT computings；
3. after computing accumulator module 4 receives startup DFT computing indication signals, the data buffer storage from inside hardware accelerator
Module 2 reads DFT data, produces twiddle factor by the parameter of software merit rating, and carry out DFT computings.It is interior to accelerate DFT computings
Portion realizes 4 frequency parallel DFT arithmetic elements, can simultaneously carry out the DFT operation results output of most 4 frequencies；Computing adds up mould
Block 4 one by one correlator one by one frequency complete DFT computings, and by DFT operation results it is cumulative updated after NCS numbers
According to；
4. after computing accumulator module 4 completes DFT computings and the NCS cumulative of all correlators all frequency point datas, statistics
Module 5 is to start the NCS data after counting DFT operation results respectively and updating, and obtains statistics.Statistics includes energy
Peak value, energy peak location and average energy value, wherein energy peak are the maximum of all frequency energy values of all correlators, energy
Amount peak is that correlator is numbered and value of frequency point, and average energy value is the average value of all frequency energy values of all correlators.
Simultaneously according to software merit rating, be automatically copied to the NCS data after renewal in base band SoC systems by data transmission module 1；
5. after statistical module 5 completes operation result statistics and NCS data are copied into base band SoC systems, that is, produce
Hardware interrupts, software directly reads operation result and carries out subsequent algorithm treatment.Operation result includes base band SoC internal systems
Access control module 3 is preserved in NCS data and this hardware accelerator statistics and peakvalue's checking result.
This hardware accelerator and method realize the DFT computings of signal trace algorithm by hardware accelerator form, use
AMBA AHB interfaces, can be directly integrated in base band SoC systems with IP modular forms, easily transplanting multiplexing, and be adapted to extensive collection
Into circuit realiration；AHB host device interfaces take out operational data so that dma mode is automatic from specified memory initial address, and by sudden
Hairdo transmission mode copies data cache module 2 to dma mode, reduces data-moving time and microprocessor intervention, improves
Performance；During single DFT computings, each correlator can parallel carry out the DFT computings of N number of frequency number, greatly improve technical performance, together
When take into account performance and Area Balanced, wherein N is natural number and N is more than 2；Energy value after single DFT computings is counted, is united
Meter result includes energy peak, energy peak location and average energy value；According to software merit rating, can be to the energy value after DFT computings
Carry out cumulative and the energy value accumulation result after DFT computings is counted, such as count cumulative average energy value, find out 3 squares
The Peak values position of the accumulated energies value of shape window；After each DFT computings and NCS energy accumulations, when statistics is calculated,
Hardware logic sends and interrupts, and software directly reads operation result and carries out subsequent algorithm treatment.
Generally speaking, operation time is reduced by measure following aspects：
Energy value computing after the DFT computings and DFT computings that hardware accelerator form realizes signal trace algorithm,
DFT operation results are automatically obtained simultaneously to add up, and DFT operation results and DFT computings accumulation result are carried out into peakvalue's checking
And statistics, same operand is calculated time about software and calculate the 1/200 of the time, realize DFT computing knots additionally by hardware
The statistics and peakvalue's checking of fruit more reduce the plenty of time；
DFT computings are carried out parallel, single DFT computings can parallel carry out the DFT computings of N number of frequency number, make DFT operation times
To be the 1/N of usual serial computing time；
In the data cache module 2 by DFT data from base band SoC system copies to this hardware accelerator, or will deposit
When the DFT operation results for being placed on this hardware accelerator data cache module 2 copy base band SoC systems to, by AHB main equipments
Interface is carried out data transmission with dma mode, and data copy average time is by be reduced to the 1/5 of I/O access modes.
The foregoing is only presently preferred embodiments of the present invention, be not intended to limit the invention, it is all it is of the invention spirit and
Within principle, any modification, equivalent substitution and improvements made etc. should be included within the scope of the present invention.
Claims (10)
1. a kind of hardware accelerator of satellite navigation baseband signal track algorithm, it is characterised in that：Including data transmission module
(1), data cache module (2), access control module (3), computing accumulator module (4) and statistical module (5), the computing add up
Module (4) includes multiple computing summing elements, and the data cache module (2) is by data transmission module (1) and base band SoC systems
System be connected, the computing accumulator module (4) is connected with data cache module (2), the access control module (3) respectively with base band
SoC systems, data transmission module (1), data cache module (2), computing accumulator module (4) are connected with statistical module (5), pass through
The data transmission module (1) writes DFT data and the NCS data of last time computing in data cache module (2), data write-in
After the completion of access control module (3) produce start DFT computing indication signals, computing accumulator module (4) produce twiddle factor simultaneously lead to
Crossing multiple computing summing elements carries out DFT computings to DFT data parallels, then obtains new by the cumulative of DFT operation results
The NCS data and NCS data to last time computing are updated, NCS of the statistical module (5) according to DFT operation results and after updating
Data obtain statistics, and the NCS data transfers after renewal are returned base band SoC systems by data transmission module (1) again.
2. a kind of hardware accelerator of satellite navigation baseband signal track algorithm according to claim 1, its feature exists
In：Also include data arbitration modules (6), the data cache module (2) is by data arbitration modules (6) and data transmission module
(1), access control module (3), computing accumulator module (4) are connected with statistical module (5), and data arbitration modules (6) are for fortune
Calculate and the interface of the front and rear data transmission module (1) of statistics and data cache module (2) carries out arbitration selection.
3. a kind of hardware accelerator of satellite navigation baseband signal track algorithm according to claim 1 and 2, its feature
It is：Also include interface configuration module (7), the access control module (3) is by interface configuration module (7) and base band SoC systems
System is connected.
4. a kind of hardware accelerator of satellite navigation baseband signal track algorithm according to claim 1, its feature exists
In：The data transmission module (1) is connected by AHB host device interfaces with base band SoC systems.
5. a kind of hardware accelerator of satellite navigation baseband signal track algorithm according to claim 1, its feature exists
In：The data cache module (2) includes DFT data cells and NCS data cells, and DFT data cells are used to deposit the DFT
Operation result, NCS data cells are used to deposit the NCS data.
6. a kind of hardware-accelerated method of satellite navigation baseband signal track algorithm, it is characterised in that comprise the following steps：
1) DFT data and the NCS data of last time computing are stored in base band SoC systems in advance, and hardware accelerator is before computing
Perform the write-in of the NCS data of DFT data and last time computing；
2) after the completion of DFT data and the NCS data of last time computing write, hardware accelerator indicates letter according to DFT computings are started
Number start DFT computings；
3) hardware accelerator reads DFT data, and produces twiddle factor by the parameter of software merit rating, cumulative by multiple computings
Unit carries out DFT computings parallel, then by DFT operation results it is cumulative updated after NCS data；
4) the NCS data after hardware accelerator counts DFT operation results and updates, after DFT operation results and renewal
NCS data obtain statistics, and by the NCS data transfers after renewal to base band SoC systems；
5) after completing operation result statistics and NCS data transfers, during hardware accelerator stops computing and counts and produce hardware
It is disconnected, read the NCS data after updating after base band SoC systems response hardware interrupts and carry out subsequent algorithm treatment.
7. a kind of hardware-accelerated method of satellite navigation baseband signal track algorithm according to claim 6, its feature exists
In：The step 1) in, hardware accelerator writes DFT data and last time computing by AHB host device interfaces with dma mode
NCS data.
8. a kind of hardware-accelerated method of satellite navigation baseband signal track algorithm according to claim 6, its feature exists
In：The step 3) in, the parameter of software merit rating specifically includes correlator number, DFT computing frequencies number, DFT computing sampled points
Count and whether add up.
9. a kind of hardware-accelerated method of satellite navigation baseband signal track algorithm according to claim 6, its feature exists
In：The step 4) in, statistics specifically includes energy peak, energy peak location and average energy value.
10. a kind of hardware-accelerated method of satellite navigation baseband signal track algorithm according to claim 6, its feature exists
In：The step 4) in, statistics is present in hardware accelerator after obtaining statistics.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109709582A (en) * | 2017-10-25 | 2019-05-03 | 三星电子株式会社 | Hypothesis related to tracking is obtained by combination to improve the device and method of GNSS sensitivity |
| CN110556841A (en) * | 2019-08-29 | 2019-12-10 | 天津大学 | island microgrid frequency controller design method considering wireless communication time delay |
| CN115630537A (en) * | 2022-12-21 | 2023-01-20 | 长沙北斗产业安全技术研究院股份有限公司 | Navigation signal simulation method and system based on-chip simulation |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1258900A (en) * | 1996-10-31 | 2000-07-05 | 传感电子公司 | Video information intelligent management system |
| CN101132191A (en) * | 2007-10-15 | 2008-02-27 | 北京航空航天大学 | Baseband signal processing method for GNSS receiver |
| CN103492904A (en) * | 2011-03-16 | 2014-01-01 | 萨热姆防务安全公司 | Detection and correction of carrier phase inconsistency during the tracking of a radio navigation signal |
| CN103499823A (en) * | 2013-09-29 | 2014-01-08 | 北京星地恒通信息科技有限公司 | Two-dimensional parallel acquisition system in spread spectrum communication |
| CN103499824A (en) * | 2013-10-22 | 2014-01-08 | 武汉大学 | Open-loop GNSS (Global Navigation Satellite System) signal carrier tracking method and system |
-
2017
- 2017-03-15 CN CN201710154587.5A patent/CN106932794B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1258900A (en) * | 1996-10-31 | 2000-07-05 | 传感电子公司 | Video information intelligent management system |
| CN101132191A (en) * | 2007-10-15 | 2008-02-27 | 北京航空航天大学 | Baseband signal processing method for GNSS receiver |
| CN103492904A (en) * | 2011-03-16 | 2014-01-01 | 萨热姆防务安全公司 | Detection and correction of carrier phase inconsistency during the tracking of a radio navigation signal |
| CN103499823A (en) * | 2013-09-29 | 2014-01-08 | 北京星地恒通信息科技有限公司 | Two-dimensional parallel acquisition system in spread spectrum communication |
| CN103499824A (en) * | 2013-10-22 | 2014-01-08 | 武汉大学 | Open-loop GNSS (Global Navigation Satellite System) signal carrier tracking method and system |
Cited By (5)
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