Two-dimentional system for parallel capture in spread spectrum communication
Technical field
The present invention relates to the two-dimentional system for parallel capture in a kind of spread spectrum communication, specifically refer to the two-dimentional system for parallel capture of pseudo-code phase and Doppler frequency deviation in a kind of satellite navigation system.
Background technology
Current satellite navigation system all adopts spread spectrum, comprises " No. one, the Big Dipper " and " No. two, the Big Dipper " satellite navigation system of China.Directly determining the critical natures such as the sensitivity of receiver and primary positioning time due to the acquisition performance of satellite-signal, so the fast Acquisition problem of the spread-spectrum signal hot issue of research both at home and abroad always.Relatively ripe for the catching method of traditional short pseudo-code, and that the P code long for the cycle, that speed is high carries out the Direct Acquisition calculated amount is very big, as still adopted traditional short method for acquiring pseudo code, will expend very long capture time.Maturation gradually along with the FPGA technology, adopt digital two-dimentional parallel capture to become possibility.
Summary of the invention
The object of the invention is to propose two-dimentional system for parallel capture in a kind of spread spectrum communication, realize the two-dimentional parallel capture of pseudo-code phase and Doppler frequency deviation in satellite navigation system, thereby solve the low efficiency problem of traditional short method for acquiring pseudo code.
Two-dimentional system for parallel capture in the spread spectrum communication that the present invention proposes: comprise and detecting and verification two parts, described test section comprises the data pretreatment unit, buffer memory I, the part matched filter, buffer memory II, FFT, the noncoherent accumulation unit, buffer memory III and peak search element, down-sampled after the reception signal down coversion that described data pretreatment unit will be inputted, local code is down-sampled simultaneously, after processing, data deposit described buffer memory I in, deposit after enough single treatment data and send into described part matched filter relevant calculating that walk abreast, then the result that will be concerned with deposits described buffer memory II in, send into the frequency spectrum after described FFT calculating is concerned with after depositing enough single treatment data, then send into described noncoherent accumulation unit spectrum value is carried out to noncoherent accumulation, the noncoherent accumulation value deposits described buffer memory III in for the next round noncoherent accumulation, send into corresponding code phase and the Doppler frequency deviation of described peak search element search maximal value after completing noncoherent accumulation, send into described check part after search and carry out verification, described check part comprises a yard delay unit, frequency offset compensation element, cumulative unit and control module, the code phase that described code delay unit and described frequency offset compensation element detect according to described detecting unit respectively and Doppler frequency deviation carry out yard time delay and receiving signal frequency offset compensation, code after processing and signal are inputted described cumulative unit simultaneously and are carried out coherent accumulation and noncoherent accumulation, accumulation result is sent into described control module and threshold judgement, surpass acquisition success of thresholding, catch otherwise carry out next section, as travel through all code phases and catch unsuccessfully.
Described data pretreatment unit will receive signal and multiply each other with the local carrier that adopts NCO and CORDIC to produce, and generate component I and quadrature component Q in the same way, then carry out respectively down-sampled, sampling rate is reduced to bit rate 2 times; Local code is carried out simultaneously down-sampled, sampling rate is reduced to bit rate 2 times.
Described buffer memory I, buffer memory II, buffer memory III are the known random access memory of insider (RAM).
Described part matched filter refers at each phase place place, and after receiving signal and local code and multiplying each other, the data of every L sampled point are done cumulative, and the reception data of an original M sampled point are become to present P sampling number certificate, wherein P=M/L.
Described FFT realizes the known Fast Fourier Transform (FFT) of insider, and gets the real part of frequency-domain result and the quadratic sum output of imaginary part.
Described noncoherent accumulation unit is by the frequency domain value of described FFT gained and the corresponding addition of frequency domain value of reading in buffer memory III, realize noncoherent accumulation, data after cumulative write buffer memory III again, and for the noncoherent accumulation of the relevant result of next round, last noncoherent accumulation result of taking turns is directly exported.
Described peak search element is searched for maximal value in the result of described noncoherent accumulation unit output, and the corresponding code phase of maximal value and Doppler frequency deviation are the Search Results of this section, export it to described check part and carry out verification.
Described code delay unit is by RAM and read-write controlling composition, the input local code writes in RAM when effective successively, the RAM write address adds 1 successively, reads address for write address subtracts the code phase in described testing result, thereby realizes exporting after the code phase in the described testing result of code time delay.
Carrier frequency after described frequency offset compensation element deducts predefined carrier frequency Doppler frequency deviation and is compensated, then according to the carrier frequency after compensation, adopt NCO and CORDIC to produce local carrier, by local carrier and reception signal multiplication, the I of component in the same way after being compensated and quadrature component Q.
Cumulative initial time and the finish time that described cumulative unit is set according to described control module, after the compensation that code after the time delay of described code delay unit output and described frequency offset compensation element are exported, signal carries out coherent accumulation and noncoherent accumulation.
Required cumulative initial time and the finish time of the detection end mark described cumulative unit of generation that described control module provides according to described test section, and in the cumulative finish time, the verification thresholding of the accumulation result of described cumulative unit and setting is compared, surpass acquisition success of thresholding, catch otherwise carry out next section, as travel through all code phases and catch unsuccessfully.
The accompanying drawing explanation
Fig. 1 is two-dimentional system for parallel capture of the present invention.
Fig. 2 is data pretreatment unit of the present invention.
Fig. 3 is part matched filter of the present invention.
Fig. 4 is FFT of the present invention.
Embodiment
Below in conjunction with embodiment, the present invention is described in further detail, but embodiments of the present invention are not limited to this.
The two-dimentional system for parallel capture that the present invention realizes in FPGA as shown in Figure 1.Comprise and detect S1 and verification S2 two parts: be down-sampled after the reception signal down coversion that test section data pretreatment unit S11 will input, local code is down-sampled simultaneously, after processing, data deposit buffer memory IS12 in, deposit after enough single treatment data and send into part matched filter S13 relevant calculating that walk abreast, then the result that will be concerned with deposits buffer memory IIS14 in, send into the frequency spectrum after FFT S15 calculating is concerned with after depositing enough single treatment data, then send into 16 pairs of spectrum values of noncoherent accumulation cell S and carry out noncoherent accumulation, the noncoherent accumulation value deposits buffer memory IIIS17 in for the next round noncoherent accumulation, send into corresponding code phase and the Doppler frequency deviation of peak search element S18 search maximal value after completing noncoherent accumulation, send into check part S2 after search and carry out verification, the code phase that check portion demal delay unit S21 and frequency offset compensation element S22 detect according to detecting unit S1 respectively and Doppler frequency deviation carry out yard time delay and receiving signal frequency offset compensation, code after processing and signal are inputted cumulative cell S 24 simultaneously and are carried out coherent accumulation and noncoherent accumulation, accumulation result is sent into control module S23 and threshold judgement, surpass acquisition success of thresholding, catch otherwise carry out next section, as travel through all code phases and catch unsuccessfully.
Data pretreatment unit S11 as shown in Figure 2.Carry out to received signal down coversion, the signal after down coversion and local code are carried out simultaneously down-sampled, sampling rate is down to bit rate 2 times.Wherein low-converter produces corresponding homophase carrier wave and quadrature carrier as frequency control word by NCO according to the IF-FRE of setting, the signal that receives and local carrier are multiplied each other and obtain the I of component in the same way and the quadrature component Q after down coversion, its basic composition unit is 1 NCO, 1 CORDIC, 2 multipliers.
Part matched filter S13 as shown in Figure 3.The chief component of basic structure is shift register group, multiplier group and totalizer group, they will expend ample resources, thereby should keep on the one hand matched filter to reach fast synchronous advantage, on the one hand by improving project organization, to reduce to greatest extent hardware size.Although be similar to the structure of Finite Impulse Response filter, different from the FIR wave filter, the coefficient in the spreading code register is only ± 1, does not need multiplication truly.Coefficient and sampled signal in pseudo-Code memory multiply each other respectively, then by result transmission backward step by step, and carry out addition one by one and finally obtain an Output rusults, the absolute value of this Output rusults, the synchronous situation of reflected input signal and local spreading code.
FFT S15 as shown in Figure 4.In input, enable when effective, the input data are write to current write (being the inverted order storage) in the address of counting by bit-reversed, when the FFT conversion that is counted as configuration to be written is counted, mean that a FFT conversion desired data is full, call over and enter first order butterfly group and carry out base-2 conversion, first order output is inputted as the second level, by that analogy, until afterbody output.The data of the first half of afterbody output are directly exported, and the latter half data first deposit in RAM, after this FFT converts, more successively data are exported from RAM.So far, this FFT converts.Then get the real part of frequency-domain result and the quadratic sum output of imaginary part.
In noncoherent accumulation cell S 16 summand be before noncoherent accumulation and (result of (n-1) inferior coherence in frequency domain cumulative sum addition), addend is the n time coherence in frequency domain cumulative sum, escape character position while carrying out additive operation (because the coherence in frequency domain cumulative sum is inevitable non-negative therefore in high position benefit ' 0 '), obtain judging whether to overflow after addition results.Have and overflow in this noncoherent accumulation process, after this noncoherent accumulation completes, finish this detection.Otherwise, when accumulative frequency reaches the noncoherent accumulation number of times of setting, this noncoherent accumulation result is directly exported.
Peak search element S18 current maximal value of first initialization before each search is 0, when the data of then exporting in the noncoherent accumulation unit are effective, adjudicate the relation of current maximal value and current noncoherent accumulation result, if the former is large, abandon current noncoherent accumulation result; Otherwise current noncoherent accumulation result is replaced current maximal value, and record code phase corresponding to current maximal value and Doppler frequency deviation.Adjudicate to last noncoherent accumulation end value, then by the maximal value of record, corresponding code phase and Doppler frequency deviation exported always.
Code delay unit S21 chief component is RAM and RAM read-write control unit.When the input data are effective, data are write in RAM, write address increases progressively automatically, after overflowing, returns to 0.Calculate according to the code phase values in testing result the clock number that code needs time delay, then current write address is deducted to this value as reading address ram, the code after time delay is read from RAM.
Down coversion in frequency offset compensation element S22 and data pretreatment unit S11 is basically identical, but the Doppler frequency deviation that the frequency control word of NCO is deducted in testing result by the IF-FRE of setting obtains.
Cumulative cell S 24 comprises coherent accumulation and noncoherent accumulation.Cumulative initial time and the finish time according to control module, set, in section flip-flop transition, the rear signal of the code after time delay and compensation is not carried out to coherent accumulation at bit, between the section that may overturn at bit, the coherent accumulation result is carried out to noncoherent accumulation.
Required cumulative initial time and the finish time of the cumulative unit of detection end mark generation that control module S23 provides according to test section S1, and the cumulative finish time will the add up accumulation result of unit and the verification thresholding of setting compare, surpass acquisition success of thresholding, catch otherwise carry out next section, as travel through all code phases and catch unsuccessfully.