CN102053250A - Two-directional pseudo code parallel search system and realization method thereof - Google Patents
Two-directional pseudo code parallel search system and realization method thereof Download PDFInfo
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Abstract
The invention discloses a two-directional pseudo code parallel search system which comprises a signal receiving device, a local PN (pseudo-noise) code generator, a signal acquiring module and a single processor; the local PN code generator and the signal acquiring module are connected with the signal processor respectively; and the local PN code generator is connected with the signal acquiring module. The two-directional pseudo code parallel search system further comprises a signal input device connected with the signal acquiring module, and enables the searches in phase direction and Doppler direction to be finished simultaneously within the related integral time, thereby shortening the search time, and improving the search efficiency. As all digital signal processing is realized on hardware in an assembly line manner, and the concurrency of the hardware is fully utilized for completing the whole search process, the speed of data processing on the hardware is greatly improved compared with the data processing on software, and the chip realization is benefited.
Description
Technical field
The present invention relates to a kind of pseudo-code search system, specifically be meant a kind of pseudo-code two dimension parallel search system and its implementation that is used for satellite navigation system.
Background technology
In present satellite navigation system, the acquisition performance of satellite-signal is determining important performances such as the sensitivity of receiver and primary positioning time, and especially aspect the P sign indicating number caught, because code word is very long, the calculated amount that search needs was very big.The acquiring pseudo code unit is determining the important indicator of subscriber computers such as acquisition sensitivity and primary positioning time as the essential elements of No. two subscriber computer base band signal process of the Big Dipper.Generally, the search to pseudo-code is divided into independently two processes, i.e. the search of the search of distance dimension and Doppler's dimension.Search procedure is such, at first estimate Doppler's value, under this doppler values situation, whole code phase is searched for then, if do not search useful signal, then Doppler's lattice of conversion continues search, up to complete Doppler's possible range of search, the sign indicating number cycle of satellite navigation signals P sign indicating number is usually greater than 1 week, bit rate is up to 10.23MHz, when the P sign indicating number is caught, if use the method for searching for each Doppler's lattice successively, its inefficiency, capture time is long, is difficult to reach the index request that the P sign indicating number is caught.
Summary of the invention
The object of the present invention is to provide a kind of pseudo-code two dimension parallel search system, cooperate its implementation to finish the search of pseudo-code, search when adjusting the distance peacekeeping Doppler dimension is shortened pseudo-code search time, to improve search efficiency.
Purpose of the present invention is achieved through the following technical solutions:
The two-dimentional parallel search of pseudo-code of the present invention system, comprise signal receiving device, local PN sign indicating number generator, signal capture module and signal processor, described signal receiving device is connected with the signal capture module, local PN sign indicating number generator, signal capture module are connected with signal processor respectively, and local PN sign indicating number generator is connected with the signal capture module.The signal that signal receiving device produces the satellite-signal that receives and local PN sign indicating number generator is connected with signal processor by data bus after by the signal capture resume module.
Described signal capture module comprises signal sampling module and high speed processing module, described signal sampling module comprises the digital down converter DDC that is connected with signal input device, the wave filter that is connected with digital down converter DDC and the buffer storage that is connected with wave filter, buffer storage is connected with the high speed processing module, and the high speed processing module is connected with signal processor by data bus.After the intermediate-freuqncy signal process A/D conversion of signal sampling module with signal receiving device output, to carry out down coversion according to pairing IF-FRE, in-phase component I after the down coversion and quadrature component Q two paths of data are carried out FIR filtering, deposit buffer storage in clock sampling then.
Described high speed processing module comprises parallel correlator, buffer, FFT mod circuit, signal incoherent accumulation circuit, the correlation peak search circuit that connects successively, described parallel correlator is connected with the signal sampling module, the correlation peak search circuit is connected with signal processor by data bus, also comprises the shift register that is connected with parallel correlator; Local PN sign indicating number generator is connected with shift register by described buffer storage.
Between described wave filter and buffer storage, also be provided with sampling switch, between local PN sign indicating number generator and buffer storage, also be provided with sampling switch.
Described sampling switch is 2 times of sign indicating number clock sampling switchs.Adopt 2 times of sign indicating number clock samplings, the data that obtain deposit buffer storage in.
Described digital down converter DDC has in-phase component I and two output ports of quadrature component Q, and is connected with buffer storage respectively.
The implementation method of pseudo-code two dimension parallel search system may further comprise the steps:
(a) set up signal receiving device;
(b) with the signal input signal sampling module of accepting, store buffer storage after treatment into; Simultaneously, local PN sign indicating number generator produces the PN sign indicating number, after the PN sign indicating number that produces is sampled by sampling switch, is sent to buffer storage;
(c) treated satellite data in the buffer storage and local PN sign indicating number are sent to the high speed processing module; Carry out data processing;
(d) data with the high speed processing module are connected with signal processor by data bus simultaneously with local PN sign indicating number generator, the signal that obtains by signal processor processes.
Say that further described step (b) may further comprise the steps:
(b1) the satellite-signal input digit low-converter DDC that signal receiving device is received obtains in-phase component I and quadrature component Q;
(b2) with in-phase component I and quadrature component Q respectively input filter carry out filter action;
(b3) will sample through sampling switch through filtered I and Q, and sampled signal will be stored in buffer storage.
Say that further described step (c) may further comprise the steps:
(c1) data-signal in the buffer storage is sent to parallel correlator; Simultaneously, local PN sign indicating number in the buffer storage is sent to shift register, then the signal in each correlator of signal in the shift register and parallel correlator is carried out matching treatment, under the effect of controller, successively be stored in buffer in by ranks the matching result data by selector switch;
(c2) each column signal in the buffer is carried out Fourier transform successively and asks modular arithmetic;
(c3) carry out incoherent accumulation for operation result;
(c4) accumulated result is carried out the correlation peak search,, then determine peak information according to peak value if there is peak value.
Further, described step (c1) may further comprise the steps:
(c11) each correlator carries out integration output in Doppler's time (integral time), and then with M Doppler in the time integration output data of correlator be arranged in following complex matrix:
In the formula
Represent the output (output of the i time relevant integration of j/2 code phase under the current search phase place) of j correlator in i Doppler's time;
(c12) to matrix
Each row carry out the FFT(Fourier transform respectively) obtain matrix
,
Be similarly the complex matrix of M*N;
(c13) to matrix
In element ask modular arithmetic (
) obtain the real number matrix of M*N
(c14) repeat (c11) to (c13) k time, obtain
Be total to k matrix;
(c15) calculate noncoherent accumulation
(c16) exist
Maximizing in the entry of a matrix element
With the position at its place (
,
).
According to what obtain
Whether can judge whether to exist relevant peaks greater than detection threshold.If relevant peaks exists, then basis
Can determine the signal doppler information, according to
Can determine to exist the code phase of relevant peaks.At first data and the index to input latchs, and compares with latched value with the current maximal value that latchs, if input value just replaces the current maximal value that latchs with the data of importing than the current maximal value that latchs is big.After the whole search of the data that needs are handled finish, FPGA will send look-at-me to processor, and processor reads maximal value by bus, phase place and doppler information.
In the receiver signal trapping module, above implementation method can realize by the scheme of a FPGA circuit and a microprocessor combination, the FPGA circuit is used for the hardware of total data Processing Algorithm to be realized, microprocessor is used for obtaining doppler information and code phase offset information and carries out the control corresponding operation.
The present invention compared with prior art has following advantage and beneficial effect:
1 pseudo-code two dimension parallel search system of the present invention and its implementation makes the two-dimensional search of phase place peacekeeping Doppler dimension finish simultaneously in the time a correlation integral, shortened search time, improved search efficiency;
2 pseudo-code two dimension parallel search system of the present invention and its implementation, because digital signal processing all realizes with pipeline system on hardware, the concurrency that makes full use of hardware is finished whole search procedure, therefore its processing speed is handled than the enterprising line data of software and is improved a lot, and is more conducive to the realization of chipization.
Description of drawings
Fig. 1 is a circuit diagram of the present invention;
Fig. 2 is a parallel correlator circuit diagram of the present invention;
Fig. 3 is FFT mod circuit figure of the present invention;
Fig. 4 is the incoherent accumulation circuit figure of the present invention;
Fig. 5 is correlation peak search circuit figure of the present invention.
Embodiment
The present invention is described in further detail below in conjunction with embodiment, but embodiments of the present invention are not limited thereto.
Embodiment one
Shown in Fig. 1 to 5, on FPGA, set up circuit, comprise that signal receiving device, signal receiving device are connected with digital down converter DDC, two output ports of the in-phase component I of digital down converter DDC and quadrature component Q are connected with buffer storage by 2 times of sign indicating number clock sampling switchs respectively, and buffer storage is connected with parallel correlator; Local PN sign indicating number generator is connected with buffer storage by 2 times of sign indicating number clock sampling switchs, and buffer storage is connected with shift register, and shift register connects in a plurality of correlator couplings; After parallel correlator connects buffer, be connected to Fourier transform mod circuit FFT, fft circuit is connected with the correlation peak search circuit by the signal incoherent accumulation circuit, the correlation peak search circuit is connected with signal processor by data bus, simultaneously, local PN sign indicating number generator also is connected with signal processor by data bus.
(a) set up signal receiving device;
(b1) the satellite-signal input digit low-converter DDC that signal receiving device is received obtains in-phase component I and quadrature component Q;
(b2) with in-phase component I and quadrature component Q respectively input filter carry out filter action;
(b3) will sample through sampling switch through filtered I and Q, and sampled signal will be stored in buffer storage;
(c11) each correlator carries out integration output in Doppler's time (integral time), and then with M Doppler in the time integration output data of correlator be arranged in following complex matrix:
In the formula
Represent the output (output of the i time relevant integration of j/2 code phase under the current search phase place) of j correlator in i Doppler's time;
(c12) to matrix
Each row carry out the FFT(Fourier transform respectively) obtain matrix
,
Be similarly the complex matrix of M*N;
(c13) to matrix
In element ask modular arithmetic (
) obtain the real number matrix of M*N
(c14) repeat (c11) to (c13) k time, obtain
Be total to k matrix;
(c15) calculate noncoherent accumulation
(c16) exist
Maximizing in the entry of a matrix element
With the position at its place (
,
);
(c2) signal in the buffer is carried out Fourier transform and it is asked modular arithmetic;
(c3) operation result is carried out incoherent accumulation;
(c4) accumulated result is carried out the correlation peak search,, then determine peak information according to peak value if there is peak value;
(d) data with the high speed processing module are connected with signal processor by data bus simultaneously with local PN sign indicating number generator, the signal message that obtains by signal processor processes.
According to what obtain
Whether can judge whether to exist relevant peaks greater than detection threshold.If relevant peaks exists, then basis
Can determine the signal doppler information, according to
Can determine to exist the code phase of relevant peaks.At first data and the index to input latchs, and compares with latched value with the current maximal value that latchs, if input value just replaces the current maximal value that latchs with the data of importing than the current maximal value that latchs is big.After the whole search of the data that needs are handled finish, FPGA will send look-at-me to processor, and processor reads maximal value by bus, phase place and doppler information.
In the receiver signal trapping module, above implementation method can realize by the scheme of a FPGA circuit and a microprocessor combination, the FPGA circuit is used for the hardware of total data Processing Algorithm to be realized, microprocessor is used for obtaining doppler information and code phase offset information and carries out the control corresponding operation.
As mentioned above, just can realize the present invention well.
Claims (10)
1. pseudo-code two dimension parallel search system, it is characterized in that: comprise signal receiving device, local PN sign indicating number generator, signal capture module and signal processor, described signal receiving device is connected with the signal capture module, local PN sign indicating number generator, signal capture module are connected with signal processor respectively, and local PN sign indicating number generator is connected with the signal capture module.
2. the two-dimentional parallel search of pseudo-code according to claim 1 system, it is characterized in that: described signal capture module comprises signal sampling module and high speed processing module, described signal sampling module comprises the digital down converter DDC that is connected with signal input device, the wave filter that is connected with digital down converter DDC and the buffer storage that is connected with wave filter, buffer storage is connected with the high speed processing module, and the high speed processing module is connected with signal processor by data bus.
3. the two-dimentional parallel search of pseudo-code according to claim 2 system, it is characterized in that: described high speed processing module comprises parallel correlator, buffer, FFT mod circuit, signal incoherent accumulation circuit, the correlation peak search circuit that connects successively, described parallel correlator is connected with the signal sampling module, the correlation peak search circuit is connected with signal processor by data bus, also comprises the shift register that is connected with parallel correlator; Local PN sign indicating number generator is connected with shift register by described buffer storage.
4. the two-dimentional parallel search of pseudo-code according to claim 2 system is characterized in that: also be provided with sampling switch between described wave filter and buffer storage, also be provided with sampling switch between local PN sign indicating number generator and buffer storage.
5. the two-dimentional parallel search of pseudo-code according to claim 4 system, it is characterized in that: described sampling switch is 2 times of sign indicating number clock sampling switchs.
6. the two-dimentional parallel search of pseudo-code according to claim 2 system, it is characterized in that: described digital down converter DDC has in-phase component I and two output ports of quadrature component Q, and is connected with buffer storage respectively.
7. the implementation method of pseudo-code two dimension parallel search system is characterized in that: may further comprise the steps:
(a) set up signal receiving device;
(b) with the signal input signal sampling module of accepting, store buffer storage after treatment into; Simultaneously, local PN sign indicating number generator produces the PN sign indicating number, after the PN sign indicating number that produces is sampled by sampling switch, is sent to buffer storage;
(c) treated satellite data in the buffer storage and local PN sign indicating number are sent to the high speed processing module, carry out data processing;
(d) data with the high speed processing module are connected with signal processor by data bus simultaneously with local PN sign indicating number generator, the signal that obtains by signal processor processes.
8. the implementation method of the two-dimentional parallel search of pseudo-code according to claim 7 system, it is characterized in that: described step (b) may further comprise the steps:
(b1) the satellite-signal input digit low-converter DDC that signal receiving device is received obtains in-phase component I and quadrature component Q;
(b2) with in-phase component I and quadrature component Q respectively input filter carry out filter action;
(b3) will sample through sampling switch through filtered I and Q, and sampled signal will be stored in buffer storage.
9. the implementation method of the two-dimentional parallel search of pseudo-code according to claim 7 system, it is characterized in that: described step (c) may further comprise the steps:
(c1) data-signal in the buffer storage is sent to parallel correlator; Simultaneously, local PN sign indicating number in the buffer storage is sent to shift register, then the signal in each correlator of signal in the shift register and parallel correlator is carried out matching treatment, under the effect of controller, successively be stored in buffer in by ranks the matching result data by selector switch;
(c2) each column signal in the buffer is carried out Fourier transform successively and asks modular arithmetic;
(c3) carry out incoherent accumulation for operation result;
(c4) accumulated result is carried out the correlation peak search,, then determine peak information according to peak value if there is peak value.
10. the implementation method of the two-dimentional parallel search of pseudo-code according to claim 9 system, it is characterized in that: described step (c1) may further comprise the steps:
(c11) each correlator carries out integration output in Doppler's time (integral time), and then with M Doppler in the time integration output data of correlator be arranged in following complex matrix:
In the formula
Represent the output (output of the i time relevant integration of j/2 code phase under the current search phase place) of j correlator in i Doppler's time;
(c12) to matrix
Each row carry out the FFT(Fourier transform respectively) obtain matrix
,
Be similarly the complex matrix of M*N;
(c13) to matrix
In element ask modular arithmetic (
) obtain the real number matrix of M*N
(c14) repeat (c11) to (c13) k time, obtain
Be total to k matrix;
(c15) calculate noncoherent accumulation
(c16) exist
Maximizing in the entry of a matrix element
With the position at its place (
,
).
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Cited By (11)
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| CN102340324A (en) * | 2011-09-26 | 2012-02-01 | 北京邮电大学 | Code phase capturing method and device for broadcast positioning signals |
| CN102520423A (en) * | 2011-12-06 | 2012-06-27 | 成都金本华科技有限公司 | Circuit for rapidly capturing long period pseudo random spread spectrum code of satellite navigation receiver and capturing method thereof |
| CN103034619A (en) * | 2012-12-13 | 2013-04-10 | 中国航天科工信息技术研究院 | Method and device for implementing FFT (Fast Fourier Transform) noncoherent integration |
| CN103472469A (en) * | 2012-06-06 | 2013-12-25 | 东莞市泰斗微电子科技有限公司 | Pseudo code phase pipeline searching method in GNSS satellite signal capture |
| CN103499823A (en) * | 2013-09-29 | 2014-01-08 | 北京星地恒通信息科技有限公司 | Two-dimensional parallel acquisition system in spread spectrum communication |
| CN104360359A (en) * | 2014-11-07 | 2015-02-18 | 中国电子科技集团公司第二十研究所 | Satellite navigation long code direct acquisition circuit structure |
| CN105204040A (en) * | 2015-09-18 | 2015-12-30 | 广州北航新兴产业技术研究院 | Satellite signal capturing system |
| CN107907893A (en) * | 2017-11-16 | 2018-04-13 | 北京卫星信息工程研究所 | Segmented based on parallel frequencies and the search of parallel code can configure the straight method for catching of army's code |
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| CN115097500A (en) * | 2022-08-24 | 2022-09-23 | 中国人民解放军国防科技大学 | Variable step length satellite navigation receiver signal correlation peak acquisition method |
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| CN102340324A (en) * | 2011-09-26 | 2012-02-01 | 北京邮电大学 | Code phase capturing method and device for broadcast positioning signals |
| CN102340324B (en) * | 2011-09-26 | 2013-12-25 | 北京邮电大学 | Code phase capturing method and device for broadcast positioning signals |
| CN102520423A (en) * | 2011-12-06 | 2012-06-27 | 成都金本华科技有限公司 | Circuit for rapidly capturing long period pseudo random spread spectrum code of satellite navigation receiver and capturing method thereof |
| CN103472469B (en) * | 2012-06-06 | 2015-09-23 | 泰斗微电子科技有限公司 | Pseudo code phase pipeline searching method in a kind of GNSS satellite signal capture |
| CN103472469A (en) * | 2012-06-06 | 2013-12-25 | 东莞市泰斗微电子科技有限公司 | Pseudo code phase pipeline searching method in GNSS satellite signal capture |
| CN103034619B (en) * | 2012-12-13 | 2015-11-18 | 中国航天科工信息技术研究院 | A kind of implementation method of FFT no-coherence cumulating and device |
| CN103034619A (en) * | 2012-12-13 | 2013-04-10 | 中国航天科工信息技术研究院 | Method and device for implementing FFT (Fast Fourier Transform) noncoherent integration |
| CN103499823A (en) * | 2013-09-29 | 2014-01-08 | 北京星地恒通信息科技有限公司 | Two-dimensional parallel acquisition system in spread spectrum communication |
| CN103499823B (en) * | 2013-09-29 | 2016-05-04 | 北京星地恒通信息科技有限公司 | Two-dimentional system for parallel capture in spread spectrum communication |
| CN104360359A (en) * | 2014-11-07 | 2015-02-18 | 中国电子科技集团公司第二十研究所 | Satellite navigation long code direct acquisition circuit structure |
| CN105204040A (en) * | 2015-09-18 | 2015-12-30 | 广州北航新兴产业技术研究院 | Satellite signal capturing system |
| CN107907893B (en) * | 2017-11-16 | 2021-07-02 | 北京卫星信息工程研究所 | Sectional configurable military code direct capturing method based on parallel frequency and parallel code search |
| CN107907893A (en) * | 2017-11-16 | 2018-04-13 | 北京卫星信息工程研究所 | Segmented based on parallel frequencies and the search of parallel code can configure the straight method for catching of army's code |
| CN108169772A (en) * | 2017-12-11 | 2018-06-15 | 成都华力创通科技有限公司 | A kind of satellite signal tracking method of windowing FFT |
| CN108169772B (en) * | 2017-12-11 | 2022-01-21 | 成都华力创通科技有限公司 | Satellite signal capturing method of windowed FFT (fast Fourier transform) |
| CN110346820A (en) * | 2019-05-07 | 2019-10-18 | 和芯星通科技(北京)有限公司 | The dispatching method and device of resource in Global Navigation Satellite System |
| CN110346820B (en) * | 2019-05-07 | 2021-05-18 | 和芯星通科技(北京)有限公司 | Method and device for scheduling resources in global navigation satellite system |
| CN115097500A (en) * | 2022-08-24 | 2022-09-23 | 中国人民解放军国防科技大学 | Variable step length satellite navigation receiver signal correlation peak acquisition method |
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Application publication date: 20110511 |