WO2015087497A1 - 高速フーリエ変換装置、高速フーリエ変換方法、及び高速フーリエ変換プログラムが記憶された記憶媒体 - Google Patents
高速フーリエ変換装置、高速フーリエ変換方法、及び高速フーリエ変換プログラムが記憶された記憶媒体 Download PDFInfo
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- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
- G06F17/14—Fourier, Walsh or analogous domain transformations, e.g. Laplace, Hilbert, Karhunen-Loeve, transforms
- G06F17/141—Discrete Fourier transforms
- G06F17/142—Fast Fourier transforms, e.g. using a Cooley-Tukey type algorithm
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- the present invention relates to arithmetic processing in digital signal processing, and more particularly to a fast Fourier transform device, a fast Fourier transform method, and a storage medium storing a fast Fourier transform program.
- FFT Fast Fourier Transform
- FDE frequency domain equalization
- IFFT inverse fast Fourier transform
- Patent Document 1 describes “twist multiplication” described later, that is, multiplication using a twist coefficient.
- Non-Patent Document 1 As an efficient FFT / IFFT processing method, for example, the Cooley-Tukey butterfly operation described in Non-Patent Document 1 is famous. However, since the FFT / IFFT processing method by Cooley-Tukey has a large number of points, a circuit for realizing the processing method becomes complicated. For this reason, for example, the Prime / Factor method described in Non-Patent Document 2 is used to perform decomposition into two small FFT / IFFT, and FFT / IFFT processing is performed.
- FIG. 14 shows a 64-point FFT data flow 500 that has been decomposed into a two-stage butterfly process with a base 8 using, for example, the Prime-Factor method.
- the data flow 500 includes a total of 16 radix-8 butterfly computation processing and twist multiplication processing 504 including data rearrangement processing 501 and butterfly computation processing 502 and 503.
- FFT processing 1, ..., 63
- some data flows are not shown.
- the basic configuration of the data flow shown in FIG. 14 is the same when IFFT processing is performed.
- 8 data parallel when FFT devices that perform FFT processing in parallel on 8 data (hereinafter simply referred to as “8 data parallel”) are created as physical circuits, a total of 8 A 64-point FFT process can be realized by repeating the process once.
- the eight repeated processes are processes in which partial data flows 505a to 505h performed on eight pieces of data are performed in order, and are specifically performed as follows. That is, the process corresponding to the partial data flow 505a is performed first time, the process corresponding to the partial data flow 505b is performed second time, and the process corresponding to the partial data flow 505c (not shown) is performed third time. Is done. Thereafter, similarly, processing up to the eighth partial data flow 505h is sequentially performed. With the above processing, 64-point FFT processing is realized.
- Patent Document 2 discloses an FFT apparatus that rearranges data using RAM in butterfly computation.
- Patent Document 3 discloses a high-speed technology based on parallel processing of butterfly operations.
- JP-A-8-137832 (page 3-5, FIG. 25) Japanese Patent Laid-Open No. 2001-56806 (5th page, FIG. 1) JP 2012-22500 A (page 5, FIG. 1)
- the frequency offset compensation process can be realized by moving the frequency spectrum on the frequency axis. Therefore, the frequency offset compensation processing can be more efficiently implemented in the frequency domain filter, and is used for FDE processing and the like.
- Non-Patent Documents 1 and 2 do not output the FFT processing result signal X (k) in the order in which higher-speed computation is performed in the subsequent stage.
- the result X (k) is output.
- FIG. 15 shows a configuration example of the FFT apparatus 600 in which the data rearrangement processing circuit 602 is connected to the subsequent stage of the FFT circuit 601.
- the data rearrangement circuit 602 needs to include a storage unit that can hold data of at least one FFT block. Furthermore, it is desirable that the output timing or output order of the plurality of processing results to the subsequent stage for each processing result is optimal for the subsequent processing.
- Non-Patent Documents 1 and 2 do not include a data rearrangement circuit, neither the output timing nor the output order of the processing results can be controlled. Therefore, there is a problem that the delay time (latency) of the entire process including the FFT process increases.
- the output timing of a plurality of results obtained by FFT processing is not taken into consideration.
- the input data to the butterfly calculation unit is rearranged.
- the FFT arithmetic unit disclosed in Patent Document 3 achieves high speed by parallelizing butterfly arithmetic.
- the output order of signals resulting from the FFT processing is not particularly taken into consideration. For this reason, signals are output in the order in which the computation of the FFT processing is completed, and the order is not necessarily suitable for speeding up the subsequent processing. Therefore, the FFT devices disclosed in Patent Documents 2 and 3 also have the same problem as described above in that the delay time of the entire process increases.
- the optimization of the timing of the processing result or the output order is effective when the processing using the result of the IFFT processing is performed in the subsequent stage of the IFFT processing.
- the present invention relates to a fast Fourier transform circuit, a fast Fourier transform processing method, and a fast Fourier transform capable of inputting data to be processed and outputting a processing result in an arbitrary order in FFT / IFFT processing in digital signal processing. It is an object to provide a storage medium in which a program is stored.
- the fast Fourier transform device performs a fast Fourier transform or an inverse fast Fourier transform to generate a plurality of first output data, and outputs the first output data in a first order; And a first data rearrangement processing unit that rearranges the plurality of first output data output in step 2 in the second order according to the output order setting based on the first movement amount.
- the fast Fourier transform device of the present invention rearranges a plurality of second input data input in the third order into a fourth order according to an input order setting based on the second movement amount.
- the fast Fourier transform method of the present invention includes rearranging a plurality of output data generated by fast Fourier transform or inverse fast Fourier transform according to output order setting based on the first movement amount setting, or fast Fourier transform or The plurality of input data of the inverse fast Fourier transform is rearranged according to the input order setting based on the second movement amount setting.
- the fast Fourier transform program stored in the storage medium of the present invention includes a computer provided in the fast Fourier transform device, means for performing fast Fourier transform or inverse fast Fourier transform, and a plurality of programs generated by fast Fourier transform or inverse fast Fourier transform.
- processing target data can be input and processing results can be output in any order.
- FIG. 1 It is a block diagram which shows the structure of the FFT apparatus 10 in the 1st Embodiment of this invention. It is a figure which shows the arrangement
- FIG. 1st data rearrangement circuit 11 In the 1st Embodiment of this invention, and the 2nd data rearrangement circuit 12.
- FIG. 1 is a block diagram showing a configuration example of an FFT apparatus 10 according to the first embodiment of the present invention.
- the FFT apparatus 10 processes the 64-point FFT decomposed into two-stage radix-8 butterfly processing according to the data flow 500 shown in FIG. 14 by a pipeline circuit method.
- N is a positive integer representing the FFT block size.
- the FFT apparatus 10 performs 64-point FFT processing in parallel with 8 data.
- the FFT circuit 10 receives time-domain data x (n), generates and outputs a frequency-domain signal X (k) subjected to Fourier transform by FFT processing.
- a total of 64 pieces of data are input as input data x (n) in the order shown in FIG.
- the numbers from 0 to 63 shown as the contents of the table in FIG. 2 mean the subscript n of x (n).
- 8 data of X (0), X (1),..., X (7) constituting the data set P1 are output in the first cycle.
- 8 data of X (8), X (9),..., X (15) constituting the data set P2 are output.
- data constituting the data sets P3 to P8 are output from the third cycle to the eighth cycle.
- the FFT apparatus 10 includes a first data rearrangement processing unit 11, a first butterfly calculation processing unit 21, a second data rearrangement processing unit 12, a twist multiplication processing unit 31, a second butterfly calculation processing unit 22, 3 data rearrangement processing unit 13 and read address generation unit 41.
- the FFT apparatus 10 performs a first data rearrangement process, a first butterfly operation process, a second data rearrangement process, a twist multiplication process, a second butterfly operation process, and a third data rearrangement process. Line processing.
- the first data rearrangement processing unit 11 and the second data rearrangement processing unit 12 are buffer circuits for data rearrangement.
- the first data rearrangement processing unit 11 and the second data rearrangement processing unit 12 respectively have data dependence on the FFT processing algorithm before and after the first butterfly computation processing unit 21. Based on the data sequence rearrangement.
- the third data rearrangement processing unit 13 is a buffer circuit for data rearrangement. That is, the third data rearrangement processing unit 13 rearranges the data sequence after the second butterfly calculation processing unit 22 based on the data dependency on the FFT processing algorithm. Further, the third data rearrangement processing unit 13 performs the rearrangement process of the output X (k) of the FFT apparatus 10 in addition to the above rearrangement. By this rearrangement, for example, it is possible to shift the processing cycle of the output X (k) to realize the shift of the frequency spectrum described above.
- the first data rearrangement processing unit 11 inputs the input data x (n) from the “sequential order” shown in FIG. 2 as the input order to the first butterfly computation processing unit 21. These are rearranged in the “bit reverse order” shown in FIG.
- the bit reverse order shown in FIG. 3 corresponds to the input data set to the radix-8 butterfly processing 502 in the first stage in the data flow diagram shown in FIG. Specifically, in the first cycle, 8 data of x (0), x (8),..., X (56) constituting the data set P1 are input. Then, in the second cycle, 8 data of x (1), x (9),..., X (57) constituting the data set P2 are input. Thereafter, data constituting the data sets P3 to P8 is input in the same manner from the third cycle to the eighth cycle.
- “sequential order” and “bit reverse order” will be specifically described.
- “Sequential order” refers to the order of the eight data sets P1, P2, P3, P4, P5, P6, P7, and P8 shown in FIG.
- (i) ps (i) 8 (s-1) + i It is.
- Each data set is arranged in the order of P1, P2, P3, P4, P5, P6, P7, and P8 corresponding to the progress of the processing cycle.
- the sequential order is a sequence in which s data sets are created by arranging i ⁇ s pieces of data i in order from the top data in the order of data, and the data sets are arranged in the order of cycles.
- bit reverse order refers to the order of the eight data sets Q1, Q2, Q3, Q4, Q5, Q6, Q7, and Q8 shown in FIG.
- Each data set is arranged in the order of Q1, Q2, Q3, Q4, Q5, Q6, Q7, and Q8 corresponding to the progress of the processing cycle.
- the bit reverse order is a sequence in which i ⁇ s pieces of data input in sequential order are arranged in s order from the top data in order of cycles, and i pieces of data in the same cycle are arranged in order of data as one set. It is.
- Each row ps (i) in FIG. 2 and eight rows qs (i) in FIG. 3 indicate data input to the i-th data in the next stage.
- Eight numbers included in each data set are identification information for specifying one of the points of the FFT, specifically, the value of the subscript n of x (n).
- the rearrangement between the data set Ps in FIG. 2 and the data set Qs in FIG. 3, that is, the correspondence between each data set and the identification information included in the data set is replaced with other data shown in the second and subsequent embodiments. It may also be performed in the rearrangement circuit.
- each sequential data set may be created by arranging data in order according to the number of FFT points, the number of cycles, and the number of data processed in parallel. Then, as described above, each data set in the bit reverse order may be created by switching the order of the data input in the sequential order with respect to the progress of the cycle and the order of the data position.
- the first butterfly calculation processing unit 21 is a butterfly circuit that processes the first butterfly calculation process 502 (first butterfly calculation process) of the radix-8 butterfly calculation process performed twice in the data flow 500 of FIG. is there.
- the second data rearrangement processing unit 12 inputs the data y (n) output from the first butterfly calculation processing unit 21 in sequential order to the second butterfly calculation processing unit 22 in order to input the data y (n) shown in FIG. Rearrange in reverse order.
- the twist multiplication processing unit 31 is a circuit that processes complex rotation on the complex plane in the FFT calculation after the first butterfly calculation process, and corresponds to the twist multiplication process 504 in the data flow 500 of FIG. In the twist multiplication process, data is not rearranged.
- the second butterfly operation processing unit 22 is a butterfly circuit that processes the second radix-8 butterfly process 503 in the data flow diagram of FIG.
- the third data rearrangement processing unit 13 sets the data X (k) output in the bit reverse order by the second butterfly computation processing unit 22 in the order shown in FIG. 4 (hereinafter referred to as “arbitrary data set sequential order”). Sort by.
- the “arbitrary data set sequential order” is an order in which the FFT apparatus 10 outputs the final result of the FFT processing.
- the arbitrary data set sequential order is an order in which s data sets Ps created in the sequential order are output in accordance with the progress of the cycle, and can be specified by the frequency offset setting 52. In this embodiment, the arbitrary data set sequential order is specified in the order of P8, P1, P2, P3, P4, P5, P6, and P7.
- Each row ps (i) in FIG. 4 indicates data input to the i-th data in the next stage.
- Eight numbers included in each data set are identification information for specifying one of the points of the FFT, specifically, the value of the subscript k of X (k).
- the third data rearrangement processing unit 13 determines the output order of the data X (k) based on the read address 51 output from the read address generation unit 41.
- the read address generation unit 41 generates a read address 51 with reference to a frequency offset setting 52 given from an upper circuit (not shown) such as a CPU (Central Processing Unit) and outputs the read address 51 to the data rearrangement processing unit 13.
- an upper circuit not shown
- CPU Central Processing Unit
- the data rearrangement processing unit temporarily stores the input data, and controls the selection and output of the stored data, so that the sequential order shown in FIG. 2, the bit reverse order shown in FIG. 3, and the arbitrary order shown in FIG. Data rearrangement processing according to each sequential order of data sets is realized. Below, the specific example of a data rearrangement process part is shown.
- the first data rearrangement processing unit 11 and the second data rearrangement processing unit 12 can be realized by, for example, the data rearrangement processing unit 100 shown in FIG.
- the data rearrangement processing unit 100 inputs data sets D1 to D8 consisting of eight data input as the input information 103 in the first-in first-out first-in first-out buffer (FIFO buffer). Write and store in storage locations 101a-101h. Specifically, data sets D1 to D8 are stored in the data storage positions 101a to 101h, respectively.
- FIFO buffer first-in first-out first-in first-out buffer
- the data rearrangement processing unit 100 outputs the stored data in the first-out order in the FIFO buffer. Specifically, the data rearrangement processing unit 100 outputs eight data read from each of the data reading positions 102a to 102h as one data set, and outputs the eight data sets D1 ′ to D8 ′ as output information 104. To do. As described above, the data sets D1 'to D8' are obtained by rearranging the data included in the data sets D1 to D8 arranged in the cycle order in the order of the data positions.
- FIG. 6 is a configuration diagram of the data rearrangement processing unit 200 showing an implementation example of the third data rearrangement processing unit 13.
- the data rearrangement processing unit 200 inputs eight data sets P1 to P8 input as the input information 203 in a first-in order in the FIFO buffer, and writes and stores them in the data storage positions 201a to 201h. . That is, the data sets D1 to D8 are sequentially stored in the data storage positions 201a to 201h corresponding to the cycle order.
- the data sets D1 'to D8' are stored in the data storage positions 202a to 202h, respectively.
- the data rearrangement processing unit 200 reads the stored data by the reading circuit 205 and outputs it as output information 204.
- the read circuit 205 refers to the read address 51 and selects any one of the data storage locations 202a to 202h to store the eight data stored in the data storage locations 202a to 202h. Any one is read by one read operation.
- the read addresses are given in the desired order which can be arbitrarily designated to the read address 51, so that the data can be read out in any order.
- the first data rearrangement processing unit 11, the second data rearrangement processing unit 12, and the third data rearrangement processing unit 13 perform the sequential order shown in FIG.
- the rearrangement process is performed three times according to each of the 3 bit reverse order and the arbitrary data set sequential order of FIG.
- the output data X (k) a total of 64 pieces of data are output in the period shown in FIG. In FIG. 4, only the subscript k of X (k) is shown. Specifically, the following data is output in each cycle. First cycle: Eight data of X (56), X (57),..., X (63) constituting the data set D8 are output. Second cycle: Eight data of X (0), X (1),..., X (7) constituting the data set D1 are output. 3rd cycle: Eight data of X (8), X (9),..., X (15) constituting the data set D2 are output. 4th cycle: Eight data of X (16), X (17),..., X (23) constituting the data set D3 are output.
- 5th cycle Eight data of X (24), X (25),..., X (31) constituting the data set D4 are output.
- 6th cycle Eight data of X (32), X (33),..., X (39) constituting the data set D5 are output.
- 7th cycle Eight data of X (40), X (41),..., X (47) constituting the data set D6 are output.
- 8th cycle Eight data of X (48), X (49),..., X (55) constituting the data set D7 are output.
- the signal X ′ (k) after the frequency spectrum shift is output in the following cycle according to the value of k.
- X ′ (k) X (k ⁇ 8 + 64) (when 0 ⁇ k ⁇ 8) X (k-8) (when 8 ⁇ k ⁇ 64)
- the frequency domain signal X ′ (k) obtained by adding a frequency offset of 8 with respect to the value of the frequency number k in the high frequency direction to the frequency domain signal X (k) is as follows.
- the output order of the FFT circuit for realizing the movement of the processing cycle can be controlled according to the frequency offset setting 52.
- the FFT apparatus 10 can output data in an arbitrary order by specifying the order using the frequency offset setting 52.
- the output order of the FFT circuit can be output according to the frequency offset amount. As a result, it is not necessary to add a circuit for performing a new rearrangement on the output.
- the circuit to be added is only the read address generator 41, and the circuit scale is very small.
- the FFT process has been described as an example, but the same applies to IFFT. That is, if the control method of the present embodiment is applied to the IFFT processing apparatus and the output order of the processing results is optimized in consideration of the processing content at the latter stage of the IFFT processing, the processing at the latter stage of the IFFT processing is accelerated. Can do.
- the output order of IFFT processing results is specified by “time offset amount” which is a temporal movement amount, not “frequency offset amount” in this embodiment. To do.
- the output order of the results of the FFT processing and IFFT processing is changed according to the “movement amount” of frequency or time, respectively.
- the processing result of the previous stage of the FFT / IFFT processing can be input to the FFT / IFFT processing device in an arbitrary order.
- the processing result of the previous stage of the FFT / IFFT processing can be input to a processing apparatus that performs processing that requires processing cycle movement, such as frequency spectrum movement, in the order desired for the processing.
- processing cycle movement such as frequency spectrum movement
- rearranging the input previous processing results in an order suitable for the FFT / IFFT processing is effective for speeding up the FFT / IFFT processing and suppressing increase in circuit scale and power consumption. is there.
- an IFFT apparatus that operates in accordance with an arbitrary data set sequential order (for example, the order shown in FIG. 4), which is a desirable order for realizing movement of a processing cycle, will be described.
- FIG. 7 is a block diagram showing a configuration example of the IFFT apparatus 20 in the second embodiment of the present invention.
- the IFFT device 20 processes the 64-point IFFT decomposed into two-stage radix-8 butterfly processing by a pipeline circuit system in a data flow similar to the FFT data flow 500 shown in FIG.
- N is a positive integer representing the IFFT block size.
- the IFFT device 20 performs 64-point IFFT processing in parallel with 8 data.
- the IFFT device 20 inputs the input X (k) in the arbitrary data set sequential order shown in FIG. 4, similar to the output of the FFT device 10.
- the IFFT device 20 outputs the output y (n) in the sequential order shown in FIG.
- the IFFT device 20 includes a first data rearrangement processing unit 14, a first butterfly calculation processing unit 21, a second data rearrangement processing unit 12, a twist multiplication processing unit 31, a second butterfly calculation processing unit 22, 3 data rearrangement processing unit 15 and write address generation unit 42.
- the IFFT device 20 performs a first data rearrangement process, a first butterfly operation process, a second data rearrangement process, a twist multiplication process, a second butterfly operation process, and a third data rearrangement process. Line processing.
- the first data rearrangement processing unit 14 is a buffer circuit for data rearrangement. That is, the first data rearrangement processing unit 14 rearranges the data sequence based on the data dependency on the IFFT processing algorithm before the first butterfly circuit 21. Furthermore, in addition to the above-described rearrangement, the first data rearrangement processing unit 14 also performs a rearrangement process for inputting data in an arbitrary data set sequential order.
- the first data rearrangement processing unit 14 inputs the arbitrary data set sequential order shown in FIG. 4 that is the input order of the input data X (k) to the first butterfly computation processing unit 21. These are rearranged in the bit reverse order shown in FIG.
- the first butterfly calculation processing unit 21 is a butterfly circuit that processes the first butterfly calculation process 502 (first butterfly calculation process) of the radix-8 butterfly calculation process performed twice in the data flow 500 of FIG. is there.
- the second data rearrangement processing unit 12 uses the bit reverse order of FIG. 3 in order to input the data y (n) output from the first butterfly calculation processing unit 21 in the sequential order to the twist multiplication processing unit 31. Rearrange.
- the twist multiplication processing unit 31 is a circuit that processes complex rotation on the complex plane in the IFFT computation after the first butterfly computation processing, and corresponds to the twist multiplication processing 504 in the data flow 500 of FIG. In the twist multiplication process, data is not rearranged.
- the second butterfly calculation processing unit 22 is a butterfly circuit that processes the second radix-8 butterfly process 503 in the data flow 500 of FIG.
- the third data rearrangement processing unit 15 rearranges the data X (k) output by the second butterfly computation processing unit 22 in the bit reverse order in the sequential order of FIG. That is, the IFFT apparatus 20 outputs the final result of the IFFT process in sequential order.
- the first data rearrangement processing unit 14 determines the input order of the data X (k) based on the write address 53 output from the write address generation unit 42.
- the second data rearrangement processing unit 12 and the third data rearrangement processing unit 15 can be realized by, for example, the data rearrangement processing unit 100 shown in FIG.
- FIG. 8 is a configuration diagram of the data rearrangement processing unit 300 showing an implementation example of the first data rearrangement processing unit 14.
- the data rearrangement processing unit 300 writes the data sets D1 to D8 composed of 8 data input as the input information 303 in the arbitrary data set sequential order to the write positions 301a to 301h by the write circuit 305.
- the write circuit 305 refers to the write address 53, selects one of the write positions 301a to 301h, and performs one write operation. That is, the data can be written in a desired order by giving the write addresses in a predetermined order designated by the write address 53.
- the data rearrangement processing unit 300 reads out and stores the stored data in the first-out order in the FIFO buffer. Specifically, the data rearrangement processing unit 300 converts the data sets D1 ′ to D8 ′ stored in the data storage positions 302a to 302h into D1 ′, D2 ′, D3 ′, D4 ′, and D5 ′. , D6 ′, D7 ′, D8 ′, and output them in the order.
- the data rearrangement processing unit 300 corresponding to the first data rearrangement processing unit 14 gives the write addresses in a desired order that can be arbitrarily specified to the write address 53, so that it is in the order desirable for movement of the processing cycle. Data can be entered. For example, when the write addresses are given in the order of addresses 8, 1, 2, 3, 4, 5, 6, 7, to the write address 53, the data rearrangement processing unit 300 includes the data sets D1, D2, D3, Data input in the order of D4, D5, D6, D7, D8 is processed as input in the order of D2, D3, D4, D5, D6, D7, D8, D1.
- X ′ (k) X (k + 8) (when 0 ⁇ k ⁇ 56) X (k + 8 ⁇ 64) (when 56 ⁇ k ⁇ 64)
- a frequency domain signal X ′ (k) obtained by adding a frequency offset of 8 with respect to the value of the frequency number k in the low frequency direction to the frequency domain signal X (k) is as follows.
- the data rearrangement processing unit 100 corresponding to the second data rearrangement processing unit 12 and the third data rearrangement processing unit 15 converts the stored data into D1, D2, D3, D4, D5, D6. , D7, D8, that is, the sequential order of FIG. (Effect of 2nd Embodiment)
- the IFFT apparatus 20 specifies the order by using the frequency offset setting 54, and thereby the data is transferred in the order desirable for realizing the movement of the processing cycle for the movement of the frequency spectrum or the like. Can be entered. Therefore, no new rearrangement means for the input is required corresponding to the output order of the FFT apparatus 10.
- the circuit to be added is only the write address generation unit 42, and the circuit scale is very small.
- the IFFT process has been described as an example, but the same applies to the FFT. That is, if the control method of this embodiment is applied to the FFT processing apparatus and the input order of the input signals is optimized in consideration of the processing content of the previous stage of the FFT processing, the FFT processing can be speeded up.
- the third data rearrangement processing unit 13 can be omitted by modifying the second data rearrangement processing unit 12. The configuration of the FFT apparatus 30 excluding the third data rearrangement processing unit 13 from the FFT apparatus 10 will be described with reference to FIG.
- FIG. 9 is a block diagram showing a configuration example of the FFT apparatus 30 according to the third embodiment of the present invention.
- the FFT apparatus 30 processes the 64-point FFT decomposed into two-stage radix-8 butterfly processing by a pipeline circuit system in a data flow similar to the FFT data flow shown in FIG.
- the FFT apparatus 30 performs Fourier transform on x (n) by FFT processing to generate a frequency-domain signal.
- N is a positive integer representing the FFT block size.
- Input data x (n) is input in the order shown in FIG. 2 in a period of 8 cycles of 8 data, for a total of 64 data x (n).
- Each row qs (i) in FIG. 10 indicates data input to the i-th data in the next stage.
- Eight numbers included in each data set are identification information for specifying one of the FFT points, specifically, the value of the subscript k of x (k).
- the signal X ′ (k) after the frequency spectrum shift is output as follows according to the value of k.
- X ′ (k) X (k ⁇ 1 + 64) (when 0 ⁇ k ⁇ 1) X (k ⁇ 1) (when 1 ⁇ k ⁇ 64)
- the frequency domain signal X ′ (k) obtained by adding a frequency offset of 1 to the value of the frequency number k in the high frequency direction to the frequency domain signal X (k) is as follows.
- the FFT device 30 includes a first data rearrangement processing unit 11, a first butterfly calculation processing unit 21, a second data rearrangement processing unit 16, a twist multiplication processing unit 31, a second butterfly calculation processing unit 22, and A read address generation unit 43 is provided.
- the same components as those in the FFT apparatus 10 are denoted by the same reference numerals, and detailed description thereof is omitted.
- the FFT device 30 pipelines the first data rearrangement process, the first butterfly operation process, the second data rearrangement process, the twist multiplication process, and the second butterfly operation process.
- the FFT device 30 has a configuration obtained by removing the third data rearrangement processing unit 13 from the configuration of the FFT device 10.
- the second data rearrangement processing unit 16 performs the rearrangement process performed by the third data rearrangement processing unit 13 in the FFT apparatus 10 with reference to the read address 51. That is, the second data rearrangement processing unit 16 rearranges the data sequence based on the data dependency on the FFT processing algorithm based on the read address 55. Further, the second data rearrangement processing unit 16 performs a rearrangement process on the output X (k) of the FFT apparatus 30 in addition to the above rearrangement.
- this rearrangement for example, it is possible to shift the processing cycle of the output X (k) to realize the shift of the frequency spectrum described above.
- the second data rearrangement processing unit 16 is the order in which the data output from the first butterfly computation processing unit 21 in the sequential order of FIG. 2 is input to the twist multiplication processing unit 31 in FIG. Arbitrary data set shown is rearranged in bit reverse order.
- the second data rearrangement processing unit 16 can be realized with the same configuration as the data rearrangement processing unit 200 shown in FIG.
- the FFT circuit can be output in accordance with the frequency offset amount. As a result, it is not necessary to add a circuit for performing a new rearrangement on the output.
- the third data rearrangement processing unit 13 can be omitted. As a result, the circuit scale and power consumption can be further reduced.
- the FFT process has been described as an example, but the same applies to IFFT. That is, if the control method of the present embodiment is applied to the IFFT processing apparatus and the output order of the processing results is optimized in consideration of the processing content at the latter stage of the IFFT processing, the processing at the latter stage of the IFFT processing is accelerated. Can do.
- the output order of IFFT processing results is specified by “time offset amount” which is a temporal movement amount, not “frequency offset amount” in this embodiment. To do.
- the output order of the results of the FFT processing and IFFT processing is changed according to the “movement amount” of frequency or time, respectively.
- the processing result of the previous stage of the FFT / IFFT processing can be input to the FFT / IFFT processing device in an arbitrary order.
- the processing result of the previous stage of the FFT / IFFT processing can be input to a processing apparatus that performs processing that requires processing cycle movement, such as frequency spectrum movement, in the order desired for the processing.
- processing cycle movement such as frequency spectrum movement
- rearranging the input previous processing results in an order suitable for the FFT / IFFT processing is effective for speeding up the FFT / IFFT processing and suppressing increase in circuit scale and power consumption. is there.
- FIG. 11 is a block diagram showing a configuration example of the IFFT apparatus 40 according to the fourth embodiment of the present invention.
- the IFFT device 40 processes the 64-point IFFT decomposed into two-stage radix-8 butterfly processing by a pipeline circuit method in a data flow similar to the FFT data flow shown in FIG.
- N is a positive integer representing the IFFT block size.
- the IFFT device 40 performs 64-point IFFT processing in parallel with 8 data.
- the IFFT apparatus 40 receives the input X (k) in the arbitrary data set bit reverse order shown in FIG. 10, similar to the output of the FFT apparatus 30. Then, the IFFT device 40 outputs the output y (n) in the sequential order shown in FIG.
- the IFFT device 40 includes a first butterfly computation processing unit 21, a first data rearrangement processing unit 17, a twist multiplication processing unit 31, a second butterfly computation processing unit 22, a second data rearrangement processing unit 15, and A write address generation unit 44 is provided.
- the same components as those in the IFFT device 20 are denoted by the same reference numerals, and detailed description thereof is omitted.
- the IFFT device 40 pipelines the first butterfly calculation process, the first data rearrangement process, the twist multiplication process, the second butterfly calculation process, and the second data rearrangement process.
- the IFFT device 40 has a configuration obtained by removing the first data rearrangement processing unit 14 from the configuration of the IFFT device 20.
- the rearrangement processing that the first data rearrangement processing unit 14 in the IFFT device 20 performs with reference to the write address 53 is performed by the second data rearrangement processing unit 17 in the IFFT device 40. That is, the second data rearrangement processing unit 17 rearranges the data sequence based on the data dependency on the IFFT processing algorithm based on the write address 57. Furthermore, in addition to the above-described rearrangement, the second data rearrangement processing unit 17 performs a rearrangement process for inputting data in an arbitrary data set sequential order.
- the second data rearrangement processing unit 17 inputs the data output by the first butterfly calculation processing unit 21 in the arbitrary data set sequential order of FIG. 4 to the second butterfly calculation processing unit 22.
- the bits are rearranged in the bit reverse order shown in FIG.
- the second data rearrangement processing unit 17 can be realized by the same configuration as the data rearrangement processing unit 300 shown in FIG. (Effect of the fourth embodiment)
- the IFFT device 40 inputs data in an order desirable for realizing the movement of the processing cycle for moving the frequency spectrum, etc., by specifying the order using the frequency offset setting 58. can do. Therefore, a new rearrangement unit for the input is not required corresponding to the output order of the FFT device 30.
- the circuit to be added is only the write address generation unit 44, and the circuit scale is very small.
- the first data rearrangement processing unit 14 can be omitted. As a result, the circuit scale and power consumption can be further reduced.
- the IFFT process has been described as an example, but the same applies to the FFT. That is, if the control method of this embodiment is applied to the FFT processing apparatus and the input order of the input signals is optimized in consideration of the processing content of the previous stage of the FFT processing, the FFT processing can be speeded up.
- the order of data input to the FFT processing is designated not by the “frequency offset amount” in the present embodiment but by the “time offset amount” that is a temporal movement amount.
- the data input order to the IFFT process and the FFT process is changed according to the “movement amount” of the frequency or time.
- the fast Fourier transform device of the present invention is characterized by rearranging data in an arbitrary order desirable for realizing movement of the processing cycle before or after the FFT / IFFT conversion.
- the processing after data rearrangement can be speeded up.
- the data rearrangement may be performed between a process at a certain stage and a process at the next stage.
- FIG. 12A, FIG. 12B, and FIG. 12C are block diagrams showing the essential configuration of the fast Fourier transform device of the present invention.
- the fast Fourier transform device 60 includes a Fourier transform unit 61 and a data rearrangement processing unit 62.
- the Fourier transform unit 61 performs a fast Fourier transform or an inverse fast Fourier transform, generates a plurality of output data, and outputs them in the first order.
- the data rearrangement processing unit 62 rearranges the plurality of first output data output in the first order in the second order based on the movement amount setting.
- the fast Fourier transform device 60 performs data rearrangement after Fourier transform.
- the “movement amount” is “frequency offset” when the Fourier transform unit 61 performs fast Fourier transform, and “time offset” when the inverse fast Fourier transform is performed.
- the fast Fourier transform device 70 includes a Fourier transform unit 72 and a data rearrangement processing unit 71.
- the data rearrangement processing unit 71 rearranges the plurality of input data input in the third order in the fourth order based on the movement amount setting.
- the Fourier transform unit 72 performs fast Fourier transform or inverse fast Fourier transform on the plurality of input data rearranged in the fourth order. As described above, the fast Fourier transform device 70 rearranges data before Fourier transform.
- the fast Fourier transform apparatus 80 includes processing units 81 and 82 and a data rearrangement processing unit 831.
- the fast Fourier transform device 80 performs fast Fourier transform or inverse fast Fourier transform in two stages using the processing units 81 and 82.
- the processing unit 81 generates a plurality of intermediate data and outputs them in the fifth order.
- the data rearrangement processing unit 83 rearranges the plurality of intermediate data input in the fifth order in the sixth order based on the order setting.
- the processing unit 82 performs a predetermined process on the plurality of intermediate data rearranged in the sixth order, and generates output data as a result of the fast Fourier transform or the inverse fast Fourier transform.
- FIG. 13 is a block diagram illustrating a configuration example of the digital filter circuit 400 according to the fifth embodiment of the present invention.
- the digital filter circuit 400 includes an FFT circuit 413, an IFFT circuit 414, a data shift circuit 415, and a filter circuit 421.
- the FFT circuit 413 converts the input complex signal x (n) into a frequency domain complex signal 431 by FFT.
- X (k) A (k) + jB (k) (2) Convert to
- n is an integer of 0 ⁇ n ⁇ N ⁇ 1 indicating a signal sample number in the time domain
- N is an integer of 0 ⁇ N indicating the number of FFT conversion samples
- k is a frequency number in the frequency domain 0 ⁇ k ⁇ N ⁇ 1.
- the data shift circuit 415 moves the output cycle of the input complex signal 431 based on the cycle shift amount signal 444 and outputs it as a complex signal 432. Further, the data shift circuit 415 replaces a part of the input complex signal 431 with the value “0” based on the cycle movement amount signal 444 and outputs it as a complex signal 432.
- the data shift circuit 415 moves the output cycle and replaces it with the value “0” so that the signal X ′ (k) becomes as follows according to the sign of D.
- the IFFT circuit 414 generates a time-domain complex signal x ′′ (n) by IFFT for the input complex signal 433 for each frequency number k of 0 ⁇ k ⁇ N ⁇ 1 and outputs it. To do.
- the FFT circuit 10 As an implementation method of the FFT circuit 413, the FFT circuit 10 according to the first embodiment of the present invention can be used. Similarly, the IFFT circuit 20 according to the second embodiment of the present invention can be used as a method for realizing the IFFT circuit 414.
- the FFT circuit 20 in the third embodiment of the present invention can be used as a method for realizing the FFT circuit 413.
- the IFFT circuit 40 according to the fourth embodiment of the present invention can be used as a method for realizing the IFFT circuit 414.
- the digital filter circuit 400 performs FFT conversion on the time domain input signal to generate a frequency domain complex signal. Then, the digital filter circuit 400 shifts the output cycle of the signal data of the complex number signal in the frequency domain by the data shift circuit 415 based on the cycle shift amount signal 444.
- the filter circuit 421 performs predetermined filter processing, and the IFFT circuit 414 converts the result into a time domain signal.
- the shift of the processing cycle is realized by performing the shift processing of the signal data based on the set value of the cycle shift amount by using the data shift circuit for the complex signal in the frequency domain. As a result, speeding up of processing that requires movement of the processing cycle, such as addition of a frequency offset, is realized.
- the FFT circuit 10 according to the first embodiment of the present invention and the IFFT circuit 20 according to the second embodiment of the present invention can be used for realizing the FFT circuit and the IFFT circuit, respectively.
- the FFT circuit 30 according to the third embodiment of the present invention and the IFFT circuit 40 according to the fourth embodiment of the present invention can be used for realizing the FFT circuit and the IFFT circuit, respectively.
- the FFT circuit and the IFFT circuit according to the embodiment of the present invention can reduce the circuit scale and power consumption for performing the FFT process and the IFFT process, respectively.
- the data shift circuit 415 does not need to rearrange the signal data between different cycles. Therefore, the data shift circuit 415 performs the filter process by using the FFT circuit or the IFFT circuit according to the embodiment of the present invention for the filter process. Therefore, the circuit scale and power consumption can be reduced.
- data rearrangement processing may be performed using a program.
- data rearrangement processing may be performed by using a DSP and a memory to control writing of data to the memory and reading of data from the memory by a program.
- FFT processing may be performed using a program in the first and third embodiments, and IFFT processing may be performed in the second and fourth embodiments.
- FFT processing, data shift processing, filter processing, and IFFT processing may be performed using a program.
- the program may be stored in a non-transitory medium such as a ROM (Read Only Memory), a RAM (Random Access Memory), a semiconductor memory device such as a flash memory, an optical disk, a magnetic disk, or a magneto-optical disk.
- a non-transitory medium such as a ROM (Read Only Memory), a RAM (Random Access Memory), a semiconductor memory device such as a flash memory, an optical disk, a magnetic disk, or a magneto-optical disk.
- First Fourier transform or inverse fast Fourier transform is performed to generate a plurality of first output data and output in a first order; and the plurality of second output data output in the first order.
- a fast Fourier transform device comprising: first data rearrangement processing means for rearranging one output data in a second order according to an output order setting based on a first movement amount.
- the first moving amount is a moving amount of frequency when the first converting unit performs fast Fourier transform, and is a moving amount of time when the first converting unit performs inverse fast Fourier transform.
- the fast Fourier transform device includes butterfly calculation processing means for performing butterfly calculation processing and outputting the plurality of first output data in the first order
- the first data rearrangement processing means includes: The fast Fourier transform device according to appendix 1 or 2, wherein the plurality of first data after the butterfly computation process is rearranged in the second order.
- the first data rearrangement processing means includes a first storage means for storing the plurality of first output data, and the plurality of first data from the first storage means based on the output order setting. And a read address generation means for generating a read address for the output data, wherein the plurality of first output data is stored in the first order and read in the second order. 4.
- the fast Fourier transform device according to any one of 3. (Appendix 5) When the plurality of first output data is X (k) (k is an integer of 0 ⁇ k ⁇ N ⁇ 1, N is the number of points of fast Fourier transform or inverse fast Fourier where N> 0), 5.
- the fast Fourier transform device according to any one of appendices 1 to 4, wherein the data rearrangement processing means outputs the data in the order specified by the output setting.
- a fast Fourier transform device comprising: a second transform unit that performs a fast Fourier transform or an inverse fast Fourier transform on the plurality of second input data rearranged in the above.
- the second moving amount is a moving amount of time when the second converting unit performs fast Fourier transform, and is a moving amount of frequency when the second converting unit performs inverse fast Fourier transform.
- the second conversion means includes butterfly calculation processing means for performing butterfly calculation processing, and the second data rearrangement processing means is configured to input the plurality of second inputs to the butterfly calculation processing means in the fourth order.
- the fast Fourier transform device according to appendix 6 or 7, wherein data is input.
- the second data rearrangement processing means includes: a second storage means for storing the plurality of second input data; and the plurality of second data to the second storage means based on the input order setting. And a write address generation means for generating a write address of the input data, wherein the plurality of second input data are stored in the third order and read out in the fourth order.
- the fast Fourier transform device according to any one of 8.
- (Appendix 12) Rearranging a plurality of output data generated by the fast Fourier transform or the inverse fast Fourier transform according to the output order setting based on the first movement amount setting, or the plurality of inputs of the fast Fourier transform or the inverse fast Fourier transform A fast Fourier transform method for rearranging data according to an input order setting based on a second movement amount setting. (Appendix 13) Based on a first moving amount setting of a plurality of output data generated by means of fast Fourier transform or inverse fast Fourier transform, and a plurality of output data generated by the fast Fourier transform or inverse fast Fourier transform.
- Sorting means for rearranging according to output order setting, or functioning as sorting means for rearranging a plurality of input data of the fast Fourier transform or the inverse fast Fourier transform according to an input order setting based on a second movement amount setting Fast Fourier transform program.
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Abstract
Description
1)D>0の場合(高周波数方向へシフトさせるためのオフセット付加)
X'(k)=X(k-D+N) (0≦k<D のとき)
X(k-D) (D≦k<N/2 のとき)
0 (N/2≦k<N/2+D のとき)
X(k-D) (N/2+D≦k<N のとき)
2)D<0の場合(低周波数方向へシフトさせるためのオフセット付加)
X'(k)=X(k-D) (0≦k<N/2+D のとき)
0 (N/2+D≦k<N/2 のとき)
X(k-D) (N/2≦k<N+D のとき)
X(k-D-N) (N+D≦k<N のとき)
3)D=0の場合(シフトなし)
X'(k)=X(k) (0≦k<N)
このように、周波数オフセット補償後の信号の周波数番号には、補償前の信号の周波数番号に対して、周波数番号の値に応じた所定のずれが生じる。通常、周波数領域における信号処理は、ある周波数番号の処理を1サイクルとして、周波数番号の順に行われる。そのため、周波数オフセット補償後の信号X'(k)の処理と、補償前の信号X(k)の処理とは、同じサイクルで実行することができない。従って、周波数オフセット補償を実現するためには、周波数領域の信号X(k)(k=0,1,・・・,N-1)の処理サイクルを、信号X(k)が入力されたサイクルとは異なるサイクルへ移動させる必要がある。この場合、信号X(k)の処理サイクルの移動先サイクルに極力近いサイクルに、信号X(k)が入力されることが望ましい。なぜなら、異なるサイクルへ信号X(k)の処理サイクルを移動させるためには、信号X(k)が入力されたサイクルから移動先サイクルまで、信号X(k)を保持する必要があり、信号X(k)の保持が全体としての処理速度の低下の原因になるためである。
(発明の目的)
本発明は、デジタル信号処理におけるFFT/IFFT処理において、処理対象のデータの入力や処理結果の出力を任意の順序で行うことが可能な高速フーリエ変換回路、高速フーリエ変換処理方法、及び高速フーリエ変換プログラムが記憶された記憶媒体を提供することを目的とする。
図1は、本発明の第1の実施形態に係るFFT装置10の構成例を示すブロック図である。FFT装置10は、図14に示されたデータフロー500に従って、2段階の基数8のバタフライ処理に分解された64ポイントFFTを、パイプライン回路方式によって処理する。FFT装置10は、時間領域のデータx(n)(n=0,1,・・・ ,N-1)が入力されると、x(n)をFFT処理によりフーリエ変換して周波数領域の信号X(k)(k=0,1,・・・,N-1)を生成し、出力する。ここで、NはFFTブロックサイズを表す正整数である。
ps(i)=8(s-1)+i
である。そして、各データ組は、処理のサイクルの進行に対応して、P1、P2、P3、P4、P5、P6、P7、P8の順に並べられている。つまり、逐次順序とは、i×s個のデータを、先頭のデータからi個ずつデータ順に並べてデータ組をs個作成し、そのデータ組をサイクル順に並べたものである。
qs(i)=(s-1)+8i
である。そして、各データ組は、処理のサイクルの進行に対応して、Q1、Q2、Q3、Q4、Q5、Q6、Q7、Q8の順に並べられている。つまり、ビットリバース順序とは、逐次順序で入力されたi×s個のデータを、先頭のデータからs個ずつサイクル順に並べ、同じサイクルのi個のデータを1つの組としてデータ順に並べたものである。
Qs(i)=Pi(s)
である。このように、Qs(i)とPi(s)とは、各データ組を構成するデータについての、サイクルの進行に対する順序とデータ位置に対する順序とが入れ替えられた関係にある。従って、ビットリバース順序で入力されたデータを、ビットリバース順序に従って並べ替えると、逐次順序になる。
1サイクル目:
データ組D8を構成するX(56),X(57),・・・,X(63)の8データが出力される。
2サイクル目:
データ組D1を構成するX(0),X(1),・・・,X(7)の8データが出力される。
3サイクル目:
データ組D2を構成するX(8),X(9),・・・,X(15)の8データが出力される。
4サイクル目:
データ組D3を構成するX(16),X(17),・・・,X(23)の8データが出力される。
5サイクル目:
データ組D4を構成するX(24),X(25),・・・,X(31)の8データが出力される。
6サイクル目:
データ組D5を構成するX(32),X(33),・・・,X(39)の8データが出力される。
7サイクル目:
データ組D6を構成するX(40),X(41),・・・,X(47)の8データが出力される。
8サイクル目:
データ組D7を構成するX(48),X(49),・・・,X(55)の8データが出力される。
X'(k) (k=8~15): 2サイクル目
X'(k) (k=16~23):3サイクル目
X'(k) (k=24~31):4サイクル目
X'(k) (k=32~39):5サイクル目
X'(k) (k=40~47):6サイクル目
X'(k) (k=48~55):7サイクル目
X'(k) (k=56~63):8サイクル目
このとき、以下の関係が成り立つ。
X(k-8) (8≦k<64 の場合)
周波数領域の信号X(k)に、高周波数の方向に周波数番号kの値について8だけ周波数オフセットが付加された周波数領域の信号X'(k)は、以下の通りである。
X(k-8) (8≦k<32 の場合)
0 (32≦k<40 の場合)
X(k-8) (40≦k<64 の場合)
従って、周波数領域の信号X'(k)を生成するために、新たに異なるサイクル間での信号の移動が必要ではなく、新たにデータの並べ替えのための回路を必要としない。すなわち、周波数領域の信号X(k)(k=0,1,・・・,63)の周波数スペクトルを、周波数番号kの値について8だけ高周波数の方向に移動させるため、望ましい信号の出力順序が実現される。
(第1の実施形態の効果)
以上のように、本実施形態では、FFT装置10は、周波数オフセット設定52を用いて順序を指定することによって、任意の順序でデータを出力することができる。
(第2の実施形態)
第1の実施形態とは逆に、FFT/IFFT処理の前段の処理結果を、任意の順序で、FFT/IFFT処理装置に入力することもできる。そのため、例えば、周波数スペクトルの移動等、処理サイクルの移動が必要な処理を行う処理装置に、その処理にとって望ましい順序で、FFT/IFFT処理の前段の処理結果を入力することができる。この場合は、入力された前段の処理結果を、FFT/IFFT処理に適した順序に並べ替えることが、FFT/IFFT処理の高速化や、回路規模及び消費電力の増加の抑制のために有効である。
X(k+8-64) (56≦k<64 の場合)
周波数領域の信号X(k)に、低周波数の方向に周波数番号kの値について8だけ周波数オフセットが付加された周波数領域の信号X'(k)は、以下の通りである。
0 (24≦k<32 の場合)
X(k+8) (32≦k<56 の場合)
X(k+8-64) (56≦k<64 の場合)
従って、周波数領域の信号X'(k)を生成するために、新たに異なるサイクル間での信号の移動が必要なく、新たにデータの並べ替えのための回路を必要としない。すなわち、周波数領域の信号X(k)(k=0,1,・・・,63)の周波数スペクトルを、周波数番号kの値について8だけ低周波数の方向に移動させるため、望ましい信号の出力順序が実現される。
(第2の実施形態の効果)
以上のように、本実施形態では、IFFT装置20は、周波数オフセット設定54を用いて順序を指定することによって、周波数スペクトルの移動等のための、処理サイクルの移動の実現に望ましい順序でデータを入力することができる。従って、FFT装置10の出力順序に対応して、入力に対する新たな並べ替え手段を必要としない。
(第3の実施形態)
FFT装置10において、第2のデータ並べ替え処理部12に改造を加えることによって、第3のデータ並べ替え処理部13は省略することができる。FFT装置10から第3のデータ並べ替え処理部13を除いたFFT装置30の構成を、図9を参照して説明する。
1サイクル目:
データ組Q8を構成するX(7),X(15),・・・,X(63)の8データを出力される。
2サイクル目:
データ組Q1を構成するX(0),X(8),・・・,X(56)の8データを出力される。
3サイクル目:
データ組Q2を構成するX(1),X(9),・・・,X(57)の8データを出力される。
4サイクル目:
データ組Q3を構成するX(2),X(10),・・・,X(58)の8データを出力される。
5サイクル目:
データ組Q4を構成するX(3),X(11),・・・,X(59)の8データを出力される。
6サイクル目:
データ組Q5を構成するX(4),X(12),・・・,X(60)の8データを出力される。
7サイクル目:
データ組Q6を構成するX(5),X(13),・・・,X(61)の8データを出力される。
8サイクル目:
データ組Q7を構成するX(6),X(14),・・・,X(62)の8データを出力される。
X'(1),X'(9),・・・,X'(57): 2サイクル目
X'(2),X'(10),・・・,X'(58):3サイクル目
X'(3),X'(11),・・・,X'(59):4サイクル目
X'(4),X'(12),・・・,X'(60):5サイクル目
X'(5),X'(13),・・・,X'(61):6サイクル目
X'(6),X'(14),・・・,X'(62):7サイクル目
X'(7),X'(15),・・・,X'(63):8サイクル目
このとき、以下の関係が成り立つ。
X(k-1) (1≦k<64 の場合)
周波数領域の信号X(k)に、高周波数の方向に周波数番号kの値について1だけ周波数オフセットが付加された周波数領域の信号X'(k)は、以下の通りである。
X(k-1) (1≦k<32 の場合)
0 (32≦k<33 の場合)
X(k-1) (33≦k<64 の場合)
従って、周波数領域の信号X'(k)を生成するために、新たに異なるサイクル間での信号の移動が必要なく、新たにデータの並べ替えのための回路を必要としない。すなわち、周波数領域の信号X(k)(k=0,1,・・・,63)の周波数スペクトルを、周波数番号kの値について1だけ高周波数の方向に移動させるため、望ましい信号の出力順序が実現される。
(第3の実施の形態の効果)
以上のように、本実施形態では、FFT装置30は、周波数オフセット設定56を用いて順序を指定することによって、任意の順序でデータを出力することができる。
(第4の実施形態)
第3の実施形態とは逆に、FFT/IFFT処理の前段の処理結果を、任意の順序で、FFT/IFFT処理装置に入力することもできる。そのため、例えば、周波数スペクトルの移動等、処理サイクルの移動が必要な処理を行う処理装置に、その処理にとって望ましい順序で、FFT/IFFT処理の前段の処理結果を入力することができる。この場合は、入力された前段の処理結果を、FFT/IFFT処理に適した順序に並べ替えることが、FFT/IFFT処理の高速化や、回路規模及び消費電力の増加の抑制のために有効である。
(第4の実施形態の効果)
以上のように、本実施形態では、IFFT装置40は、周波数オフセット設定58を用いて順序を指定することによって、周波数スペクトルの移動等のための処理サイクルの移動の実現に望ましい順序でデータを入力することができる。従って、FFT装置30の出力順序に対応して、入力に対する新たな並べ替え手段を必要としない。
(第5の実施形態)
図13は、本発明の第5の実施形態におけるデジタルフィルタ回路400の構成例を示すブロック図である。デジタルフィルタ回路400は、FFT回路413、IFFT回路414、データシフト回路415、及びフィルタ回路421、を備える。
x(n)=r(n)+js(n) ・・・(1)
を入力する。
X(k)=A(k)+jB(k) ・・・(2)
に変換する。
1)D>0の場合(高周波数方向へサイクルをシフト)
X'(k)=X(k-D+N) (0≦k<D のとき)
X(k-D) (D≦k<N/2 のとき)
0 (N/2≦k<N/2+D のとき)
X(k-D) (N/2+D≦k<N のとき)
2)D<0の場合(低周波数方向へサイクルをシフト)
X'(k)=X(k-D) (0≦k<N/2+D のとき)
0 (N/2+D≦k<N/2 のとき)
X(k-D) (N/2≦k<N+D のとき)
X(k-D-N) (N+D≦k<N のとき)
3)D=0の場合(シフトなし)
X'(k)=X(k) (0≦k<N)
次に、フィルタ回路421は、データシフト回路415が複素数信号432として出力したX(k)に対して、フィルタ係数信号445によって入力されるフィルタ係数C1(k)を用いて、複素数乗算による複素数フィルタ処理を行う。具体的には、フィルタ回路421は、0≦k≦N-1の周波数番号kのそれぞれについて、複素数信号
X'(k)=X(k)×C1(k) ・・・(3)
を計算して、複素数信号433として出力する。
(第5の実施形態の効果)
以上のように、本実施形態によれば、周波数領域の複素数信号をデータシフト回路により、サイクル移動量の設定値に基づいて信号データのシフト処理を行うことで、処理サイクルの移動を実現する。これにより、周波数オフセットの付加等、処理サイクルの移動が必要な処理の高速化が実現される。
(付記1)
高速フーリエ変換又は逆高速フーリエ変換を行って、複数の第1の出力データを生成し、第1の順序で出力する第1の変換手段と、前記第1の順序で出力された前記複数の第1の出力データを、第1の移動量に基づく出力順序設定に従って第2の順序に並べ替える第1のデータ並べ替え処理手段と、を備える高速フーリエ変換装置。
(付記2)
前記第1の移動量は、前記第1の変換手段が高速フーリエ変換を行うときは周波数の移動量であり、前記第1の変換手段が逆高速フーリエ変換を行うときは時間の移動量であることを特徴とする付記1に記載の高速フーリエ変換装置。
(付記3)
前記第1の変換処理手段は、バタフライ演算処理を行い、前記第1の順序で前記複数の第1の出力データを出力するバタフライ演算処理手段を含み、前記第1のデータ並べ替え処理手段は、前記バタフライ演算処理後の前記複数の第1のデータを前記第2の順序に並べ替えることを特徴とする付記1又は2に記載の高速フーリエ変換装置。
(付記4)
前記第1のデータ並べ替え処理手段は、前記複数の第1の出力データを記憶する第1の記憶手段と、前記出力順序設定に基づいて、前記第1の記憶手段からの前記複数の第1の出力データの読み出しアドレスを生成する読み出しアドレス生成手段とを備え、前記複数の第1の出力データを前記第1の順序で記憶し、前記第2の順序で読み出すことを特徴とする付記1乃至3のいずれかに記載の高速フーリエ変換装置。
(付記5)
前記複数の第1の出力データをX(k)(kは0≦k≦N-1の整数、NはN>0の高速フーリエ変換又は逆高速フーリエのポイント数)とするとき、前記第1のデータ並べ替え処理手段は、前記出力設定が指定する順序で出力することを特徴とする付記1乃至4のいずれかに記載の高速フーリエ変換装置。
(付記6)
第3の順序で入力される複数の第2の入力データを、第2の移動量に基づく入力順序設定に従って第4の順序に並べ替える第2のデータ並べ替え処理手段と、前記第4の順序に並べ替えられた前記複数の第2の入力データに対して、高速フーリエ変換又は逆高速フーリエ変換を行う第2の変換手段と、を備える高速フーリエ変換装置。
(付記7)
前記第2の移動量は、前記第2の変換手段が高速フーリエ変換を行うときは時間の移動量であり、前記第2の変換手段が逆高速フーリエ変換を行うときは周波数の移動量であることを特徴とする付記6に記載の高速フーリエ変換装置。
前記第2の変換手段は、バタフライ演算処理を行うバタフライ演算処理手段を含み、前記第2のデータ並べ替え処理手段は、前記第4の順序で前記バタフライ演算処理手段に前記複数の第2の入力データを入力することを特徴とする付記6又は7に記載の高速フーリエ変換装置。
前記第2のデータ並べ替え処理手段は、前記複数の第2の入力データを記憶する第2の記憶手段と、前記入力順序設定に基づいて、前記第2の記憶手段への前記複数の第2の入力データの書き込みアドレスを生成する書き込みアドレス生成手段とを備え、前記複数の第2の入力データを前記第3の順序で記憶し、前記第4の順序で読み出すことを特徴とする付記6乃至8のいずれかに記載の高速フーリエ変換装置。
前記複数の第1の入力データをX(k)(kは0≦k≦N-1の整数、NはN>0の高速フーリエ変換又は逆高速フーリエのポイント数)とするとき、前記第2のデータ並べ替え処理手段は、前記入力設定が指定する順序で前記バタフライ演算処理手段に入力することを特徴とする付記6乃至9のいずれかに記載の高速フーリエ変換装置。
(付記11)
付記1又は6に記載の高速フーリエ変換装置を含むフィルタ装置。
(付記12)
高速フーリエ変換若しくは逆高速フーリエ変換により生成された複数の出力データの、第1の移動量設定に基づく出力順序設定に従った並べ替え、又は前記高速フーリエ変換若しくは前記逆高速フーリエ変換の複数の入力データの、第2の移動量設定に基づく入力順序設定に従った並べ替えを行う高速フーリエ変換方法。
(付記13)
高速フーリエ変換装置が備えるコンピュータを、高速フーリエ変換又は逆高速フーリエ変換を行う手段、及び前記高速フーリエ変換若しくは前記逆高速フーリエ変換により生成された複数の出力データの、第1の移動量設定に基づく出力順序設定に従って並べ替える並べ替え手段、又は前記高速フーリエ変換若しくは前記逆高速フーリエ変換の複数の入力データの、第2の移動量設定に基づく入力順序設定に従って並べ替える並べ替え手段として機能させるための高速フーリエ変換プログラム。
20、40 IFFT装置
11、12、13、14、15、16、17 データ並べ替え処理部
21、22 バタフライ演算処理部
31 ひねり乗算処理部
41、43 読み出しアドレス生成部
42、44 書き込みアドレス生成部
51、55 読み出しアドレス
52、56 周波数オフセット設定
53、57 書き込みアドレス
54、58 周波数オフセット設定
60、70、80 高速フーリエ変換装置
61、72 フーリエ変換部
62、71、83 データ並べ替え処理部
81、82 処理部
100、200、300 データ並べ替え処理部
101a~101h データ記憶位置
102a~102h データ読み出し位置
201a~201h データ記憶位置
301a~301h データ記憶位置
400 デジタルフィルタ回路
413 FFT回路
414 IFFT回路
415 データシフト回路
421 フィルタ回路
431~433 複素数信号
444 サイクル移動量信号
445 フィルタ係数信号
500 データフロー
501 データ並べ替え処理
502、503 バタフライ演算処理
504 ひねり演算処理
505 部分データフロー
600 FFT装置
601 FFT部
602 データ並べ替え処理部
Claims (10)
- 高速フーリエ変換又は逆高速フーリエ変換を行って、複数の第1の出力データを生成し、第1の順序で出力する第1の変換手段と、
前記第1の順序で出力された前記複数の第1の出力データを、第1の移動量に基づく出力順序設定に従って第2の順序に並べ替える第1のデータ並べ替え処理手段と、
を備える高速フーリエ変換装置。 - 前記第1の変換処理手段は、バタフライ演算処理を行い、前記第1の順序で前記複数の第1の出力データを出力するバタフライ演算処理手段を含み、
前記第1のデータ並べ替え処理手段は、前記バタフライ演算処理後の前記複数の第1のデータを前記第2の順序に並べ替える
ことを特徴とする請求項1に記載の高速フーリエ変換装置。 - 前記第1のデータ並べ替え処理手段は、
前記複数の第1の出力データを記憶する第1の記憶手段と、前記移動量設定に基づいて、前記第1の記憶手段からの前記複数の第1の出力データの読み出しアドレスを生成する読み出しアドレス生成手段とを備え、
前記複数の第1の出力データを前記第1の順序で記憶し、前記第2の順序で読み出すこと
を特徴とする請求項1又は2に記載の高速フーリエ変換装置。 - 前記複数の第1の出力データをX(k)(kは0≦k≦N-1の整数、NはN>0の高速フーリエ変換又は逆高速フーリエのポイント数)とするとき、前記第1のデータ並べ替え処理手段は、前記出力設定が指定する順序で出力すること
を特徴とする請求項1乃至3のいずれかに記載の高速フーリエ変換装置。 - 第3の順序で入力される複数の第2の入力データを、第2の移動量に基づく入力順序設定に従って第4の順序に並べ替える第2のデータ並べ替え処理手段と、
前記第4の順序に並べ替えられた前記複数の第2の入力データに対して、高速フーリエ変換又は逆高速フーリエ変換を行う第2の変換手段と、
を備える高速フーリエ変換装置。 - 前記第2の変換手段は、バタフライ演算処理を行うバタフライ演算処理手段を含み、前記第2のデータ並べ替え処理手段は、前記第4の順序で前記バタフライ演算処理手段に前記複数の第2の入力データを入力することを特徴とする請求項5に記載の高速フーリエ変換装置。
- 前記第2のデータ並べ替え処理手段は、前記複数の第2の入力データを記憶する第2の記憶手段と、前記入力順序設定に基づいて、前記第2の記憶手段への前記複数の第2の入力データの書き込みアドレスを生成する書き込みアドレス生成手段とを備え、前記複数の第2の入力データを前記第3の順序で記憶し、前記第4の順序で読み出すことを特徴とする請求項5又は6に記載の高速フーリエ変換装置。
- 請求項1又は5に記載の高速フーリエ変換装置を含むデジタルフィルタ装置。
- 高速フーリエ変換若しくは逆高速フーリエ変換により生成された複数の出力データの、第1の移動量設定に基づく出力順序設定に従った並べ替え、又は
前記高速フーリエ変換若しくは前記逆高速フーリエ変換の複数の入力データの、第2の移動量設定に基づく入力順序設定に従った並べ替えを行う
高速フーリエ変換方法。 - 高速フーリエ変換装置が備えるコンピュータを、
高速フーリエ変換又は逆高速フーリエ変換を行う手段、及び
前記高速フーリエ変換若しくは前記逆高速フーリエ変換により生成された複数の出力データの、第1の移動量設定に基づく出力順序設定に従って並べ替える並べ替え手段、又は 前記高速フーリエ変換若しくは前記逆高速フーリエ変換の複数の入力データの、第2の移動量設定に基づく入力順序設定に従って並べ替える並べ替え手段
として機能させるための高速フーリエ変換プログラムが記憶された記憶媒体。
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