Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L7/00—Arrangements for synchronising receiver with transmitter
  • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
  • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L7/00—Arrangements for synchronising receiver with transmitter
  • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
  • H04L7/0033—Correction by delay
  • H04L7/0037—Delay of clock signal
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L7/00—Arrangements for synchronising receiver with transmitter
  • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L7/00—Arrangements for synchronising receiver with transmitter
  • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
  • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
  • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Definitions

• the present invention relates to adjustment of timing signals.
• Information carried in data signals can be lost if clock signals that are associated with the data signals are not properly timed relative to the data signals.
• Certain equipment such as electronic test equipment can provide synchronous clock signals that can be aligned with data signals of a device such as a device under test. Since these synchronous clock signals are provided by equipment external to the device, sometimes the clock signals can be misaligned with the data signals provided by the device. Misalignment of synchronous clock signals can become particularly problematic when very high speed data signals and clock signals are being used.
• Source-synchronous clock signals generally may not become misaligned with the data signals that are associated with them.
• communicating source-synchronous clock signals to each of a plurality of channels on certain equipment where the clock signals may be needed for comparison with associated data signals can be inefficient and burdensome.
• Illustrative embodiments of the present invention provide a method and apparatus for aligning a synchronous clock signal with a data signal which comes from a different source than the synchronous clock signal.
• Embodiments of the present invention can be used, for example, in equipment such as test equipment to generate well timed synchronous clock signals internally for association with data signals that are received from an external source.
• An illustrative embodiment of the invention provides a method for calibrating a synchronous clock signal by advancing the synchronous clock signal, by decreasing a delay in the synchronous clock signal, for example, if a transition of a data signal occurs before a pulse of an offset synchronous clock signal.
• the offset synchronous clock signal is delayed by one half cycle relative to the synchronous clock signal.
• the delay in the synchronous clock signal can be increased if the transition of the data signal occurs after the pulse of the offset synchronous clock signal.
• the synchronous clock signal can be offset by a half cycle to provide an offset clock signal.
• a data signal can be latched with a pulse of the synchronous clock signal to provide a first state.
• the data signal can be latched with another pulse, such as a next pulse of the synchronous clock signal, for example to provide a second state.
• the data signal can be latched with a pulse of the offset clock signal to provide a third data state.
• a delay in the synchronous clock signal can be decreased if the first state is different from the second state and the first state is equal to the third state.
• a delay in the synchronous clock signal can be increased if the first state is different from the second state and the first state is different from the third state.
• the illustrative apparatus includes latching circuitry which receives a data signal, a synchronous clock signal and an offset synchronous clock signal.
• the illustrative apparatus further includes compare circuitry in communication with the latching circuitry.
• the compare circuitry receives a latched data state corresponding to a first state, another latched data state, such as a previous latched data state, for example, corresponding to a second state and an offset latched data state corresponding to a third state from the latching circuitry.
• the illustrative apparatus further includes controllable delay circuitry in communication with the compare circuitry.
• the controllable delay circuitry receives the synchronous clock signal and changes the delay in the synchronous clock signal depending on whether the second state is equal to or different from the third state if the first state is different from the second data state.
• the controllable delay circuitry may change the delay in the synchronous clock signal depending on whether the third state is equal to or different from the first state if the first state is different from the second state.
• FIGs. 1 - 3 are timing diagrams of a data signal, a synchronous clock signal and an offset clock signal according to illustrative embodiments of the present invention
• FIG. 4 is a process flow diagram of a method for adjusting the timing of a synchronous clock signal according to an illustrative embodiment of the present invention
• FIG. 5 is a schematic block diagram of an apparatus for providing a synchronous clock signal according to an illustrative embodiment of the present invention
• Fig. 6 is a schematic circuit diagram of an apparatus for providing a synchronous clock signal according to an illustrative embodiment of the present invention
• Fig. 7 is a schematic circuit diagram of an apparatus for providing a high speed synchronous clock signal according to an alternative embodiment of the present invention.
• a synchronous clock signal 10 includes a train of synchronous clock pulses 12 that can have a period 14 corresponding to a data cycle 16 of a data signal 18.
• An offset clock signal 20 includes a train of offset clock pulses 22 that have the same period 14 as the synchronous clock signal but are offset from the synchronous clock pulses 12 by one half period (e.g., one half of data cycle 16).
• Fig. 2 is a timing diagram illustrating the relationship between a data signal, synchronous clock signal and offset clock signal in a system wherein the synchronous clock pulses 12 do not occur at the center of each data cycle. Rather, synchronous clock pulses 12 in Fig. 2 occur earlier than the center of each data cycle. In this case of a synchronous clock signal 10 which runs early, the offset clock signal 20 runs early and the offset pulse 22 does not occur simultaneously with a transition of the data signal 18.
• a transition occurred in the data signal 18 an early synchronous clock signal can be identified by determining that a state of the data signal 18 at the time of an offset clock pulse 22 is the same as the state of the data signal at the time of the previous synchronous clock pulse 12.
• Fig. 3 is a timing diagram illustrating the relationship between a data signal, synchronous clock signal and offset clock signal in another system wherein the synchronous clock pulses 12 do not occur at the center of each data cycle. Rather, synchronous clock pulses 12 in Fig. 3, occur later than the center of each data cycle. In this case of a synchronous clock signal 10 which runs late, the offset clock signal 20 runs late and the offset pulse 22 does not occur simultaneously with a transition of the data signal 18.
• a late synchronous clock signal can be identified if a transition occurred in the data signal 18 by determining that a state of the data signal 18 at the time of an offset clock pulse 22 is the different from the state of the data signal at the time of the previous synchronous clock pulse 12.
• a method for adjusting the timing of a synchronous clock signal relative to a data signal is described with reference to Fig. 4.
• a storage step 24 a state of a data signal 18 at the time of a first synchronous clock pulse 12 is stored.
• a state of the data signal 18 is stored at the time of a second synchronous clock pulse 15. It should be understood that the terms "first,” “second” and “third,” etc. used herein are not used to identify an initial, second and third pulse or state in a signal, but rather are used to identify pulses or states anywhere in a signal or signals relative to each other.
• an offset latching step 28 a state of the data signal 18 is stored at the time of an offset clock pulse 22 that occurs between the first synchronous clock pulse 12 and the second synchronous clock pulse 15.
• a first comparison step 30 can be performed to determine whether a transition of the data signal 18 has occurred between the first synchronous clock pulse 12 and the second synchronous clock pulse 15.
• a state of the data signal 18 at the time of the first synchronous clock pulse 12 that had been stored in the storage step 24 can be compared with a state of the data signal 18 at the time of the second synchronous clock pulse 15 that had been stored in the latching step 26. If these states are different, then a transition has occurred and a second comparison step 32 can be performed to determine whether the synchronous clock signal 10 is running early or late. If these states are the same, then no transition has occurred. If no transition has occurred, the state of the data signal 18 at the time of the second synchronous clock pulse 15 can be stored in a storage step 24 for a next iteration of the method of this illustrative embodiment.
• the state of the data signal 18 at the time of the first synchronous clock pulse 12 that had been stored in the storage step 24 can be compared with the state of the data signal 18 at the time of the offset clock pulse 22 that had been stored in the offset latching step 28. If the states compared in the second comparison step 32 are the same, then the synchronous clock signal 10 is running early so a delaying step 34 can be performed to more closely align pulses of the synchronous clock signal 10 with the center of cycles of the data signal 18. If the states compared in the second comparison step 32 are different, then the synchronous clock signal 10 is running late so an advancing step 36 can be performed to more closely align pulses of the synchronous clock signal 10 with the center of cycles of the data signal 18. In either case, the state of the data signal 18 at the time of the second synchronous clock pulse 15 can then be stored in a storage step for use in a next iteration of the method of this illustrative embodiment.
• a data signal 18, a synchronous clock signal 10 and an offset clock signal 20 are provided to latching circuitry 38.
• the synchronous clock signal 10 is also provided to offset circuitry 40 which provides the offset clock signal 20.
• the latching circuitry 38 stores states of the data signal 18 at the time of each pulse of the synchronous clock signal 10 and offset clock signal 20.
• the latching circuitry 38 is in communication with compare circuitry 48 and provides to the compare circuitry 48: a first state 42 of the data signal 18 that had been stored at the time of a first synchronous clock pulse (item 12, Figs. 1 - 3); a second state 44 of the data signal 18 that had been stored at the time of a second synchronous clock pulse (item 15, Figs. 1 - 3); and a third state 46 of the data signal 18 that had been stored at the time of an offset clock pulse (item 22, Figs. 1 - 3) which occurred between the first synchronous clock pulse (item 12, Figs. 1 - 3) and the second synchronous clock pulse (item 15, Figs. 1 - 3).
• the compare circuitry 48 is in communication with controllable delay circuitry 50.
• the compare circuitry 48 sends an advance signal (i.e., a decrease delay signal) to the controllable delay circuitry 50 if the first state 42 is different from the second state 44 and the first state 42 is different from the third state 46.
• the compare circuitry 48 sends a retard signal (i.e., an increase delay signal) to the controllable delay circuitry 50 if the first state 42 is different from the second state 44 and the first state 42 is the same as the third state 46.
• delay circuitry 52 is provided between the compare circuitry 48 and the controllable delay circuitry 50 to delay the advance and retard signals long enough for signals in the apparatus to settle following previous advance and retard signals.
• a data signal 18 is provided to data inputs of a first latch 54 and a second latch 56.
• a synchronous clock signal 10 is provided to clock inputs of the first latch 54, a third latch 58, a fourth latch 68, a fifth latch 70, a sixth latch 72 and a seventh latch 74.
• the synchronous clock signal 10 is also provided to offset circuitry 75 which offsets the synchronous clock signal 10 by half of a cycle to provide an offset synchronous clock signal 20 to the clock input of the second latch 56.
• the output of the first latch 54 is provided as input of the third latch 58 so that the third latch 58 stores the state that had been stored in the first latch 54 on the previous cycle of the synchronous clock signal 10.
• the output of the third latch 58 provides a first state to one input of a first exclusive-OR-gate 60 (hereinafter referred to as "XOR gate”) and to one input of a second XOR gate 62.
• the second latch 56 provides a third state to the other input of the second XOR gate 62.
• the first latch 54 provides a second state to the other input of the first XOR gate 60.
• the output of the first XOR gate 60 is asserted if the first state is different from the second state, i.e., if a data signal transition occurred between the first synchronous clock pulse 12 and the second synchronous clock pulse 15 (Figs. 1 - 3). Accordingly, in this illustrative embodiment, the first XOR gate 60 provides a transition indicator signal. The output of the first XOR gate 60 is provided to one input of a first AND gate 64 and to one input of a second AND gate 66.
• the second XOR gate 62 has a non-inverted output which is asserted if the first state is different from the third state, and an inverted output which is asserted if the first state is the same as the third state.
• an XOR gate such as the second XOR gate 62 having an inverted output and a non-inverted output can be constructed by providing a connection to both sides of an inverter that is connected to the output of a standard single output XOR gate.
• the non-inverted output of the second XOR gate 62 is provided as an input to the first AND gate 64.
• the inverted output of the second XOR gate 62 is provided as an input to the second AND gate 66. Accordingly, the output of the first AND gate 64 is asserted if the first state and the second state are different, i.e., a transition has occurred, and the first state and third state are different, i.e., the synchronous clock signal 10 is running late.
• An asserted output of the first AND gate 64 can therefore be used as a clock advance signal to decrease a delay in the synchronous clock signal 10.
• the output of the second AND gate 66 is asserted if the first state and the second state are different, i.e., a transition has occurred, and the first state and third state are the same, i.e., the synchronous clock signal 10 signal is running early.
• An asserted output of the second AND gate 66 can therefore be used as a clock delay signal to increase the delay in the synchronous clock signal 10.
• the output of the first AND gate 64 is provided as an input to a fourth latch 68.
• the output of the second AND gate 66 is provided as an input to a fifth latch 70.
• the output of the fourth latch 68 is provided as ' an input to a sixth latch 72.
• the output of the fifth latch 70 is provided as an input to a seventh latch 74.
• the fourth, fifth, sixth and seventh latches 68, 70, 72, 74 are all clocked by the synchronous clock signal 10 and thereby provide outputs that are timed to assure that XOR gates 60, 62 and AND gates 64, 66 have settled and that the comparisons performed by the XOR gates 60, 62 and AND gates 64, 66 occur before a next offset pulse arrives so that the proper offset clock pulse (item 22, Figs. 1 - 3) which occurs between the first and second synchronous clock pulses (items 12 and 15, Figs. 1 - 3) is used in the comparison.
• the output of the sixth latch 72 is provided as an advance signal, i.e., a decrease delay signal, to controllable delay circuitry 76 in communication with a clock signal 78 which provides the synchronous clock signal 10 and, when asserted, causes the synchronous clock signal 10 to be advanced.
• the output of the seventh latch 74 is provided as a delay signal to controllable delay circuitry 76 and, when asserted, causes the synchronous clock signal to be delayed.
• a synchronous clock signal such as a 2 GHz clock signal is divided, by clock divider circuitry, for example, into a plurality of shifted synchronous clock signals, such as four 8 GHz clock signals, for example.
• Latching circuitry 38, offset circuitry 40, compare circuitry 42 and delay circuitry 52 are provided for each of the plurality of shifted synchronous clock signals substantially as described herein with reference to Figs. 5 and 6.
• increment and decrement signals are provided by compare circuitry 42 and delay circuitry 52 associated with each of the plurality of synchronous clock signals.
• the increment and decrement signals are , averaged by add and compare circuitries 80 which provide an increment or decrement signal to controllable delay circuitry (not shown) in communication with the 2GHz clock signal depending on whether the number of increment signals received by the add and compare circuitries 80 were greater than or less than the number of decrement signals received by the add and compare circuitries 80.
• This embodiment thereby provides a high frequency synchronous clock signal that is self centering with a high frequency data signal.
• timing pulses are shown and described generally in Figs 1-3 with reference to the center of synchronous clock pulses and the center of offset clock pulses, persons having ordinary skill in the art should understand that various circuitries operate by clocking elements on the rising edge or the falling edge of a clock pulse. It should be understood that the alignment of clock signals and synchronous clock signals can therefore be different from that shown in Figs. 1 - 3 to accommodate devices which respond to rising or falling edges of a clock signal within the scope of the present invention.
• data signals comprise various signal types and can include clock signals for example which can be treated as data by test equipment. It should be understood that virtually any type of binary signal associated with a clock signal can be used in place of the data signals described herein without departing from the scope of the present invention.
• the illustrative embodiments of the present invention are described generally herein in terms of comparing a second state of a data signal at the time of a previous synchronous clock pulse (item 12, Figs. 1 - 3) with a third state of the data signal at the time of an offset clock pulse (item 22, Figs.
• first state of the data signal taken at the time of a synchronous clock pulse (item 15, Figs. 1 - 3) can also be compared with the third state of the data signal taken at the time of the offset clock pulse (item 22, Figs. 1 - 3) to determine whether to retard or advance the synchronous clock signal within the scope of the present invention.
• illustrative embodiments of the present invention provide a method and apparatus that can be used to provide a clock signal that is precisely timed relative to a data signal.
• the methods and apparatus described herein continuously adjust a clock signal relative to an associate data signal so that the clock signal can be used in place of a source-synchronous clock signal in equipment such as electronic test equipment.

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• Engineering & Computer Science (AREA)
• Computer Networks & Wireless Communication (AREA)
• Signal Processing (AREA)
• Synchronisation In Digital Transmission Systems (AREA)
• Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

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• 2005
  • 2005-10-31 US US11/263,397 patent/US7593497B2/en active Active
• 2006
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  • 2006-10-26 DE DE112006003101T patent/DE112006003101T5/de not_active Withdrawn
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