WO2007038033A3 - Procede et dispositif permettant la detection d'une transition de synchronisation tardive - Google Patents

Procede et dispositif permettant la detection d'une transition de synchronisation tardive Download PDF

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Publication number
WO2007038033A3
WO2007038033A3 PCT/US2006/036153 US2006036153W WO2007038033A3 WO 2007038033 A3 WO2007038033 A3 WO 2007038033A3 US 2006036153 W US2006036153 W US 2006036153W WO 2007038033 A3 WO2007038033 A3 WO 2007038033A3
Authority
WO
WIPO (PCT)
Prior art keywords
transition detection
late timing
timing transition
latches
outputs
Prior art date
Application number
PCT/US2006/036153
Other languages
English (en)
Other versions
WO2007038033A2 (fr
Inventor
Edward Grochowski
Chris Wilkerson
Shih-Lien Lu
Murali Annavaram
Original Assignee
Intel Corp
Edward Grochowski
Chris Wilkerson
Shih-Lien Lu
Murali Annavaram
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp, Edward Grochowski, Chris Wilkerson, Shih-Lien Lu, Murali Annavaram filed Critical Intel Corp
Priority to CN2006800346785A priority Critical patent/CN101268615B/zh
Priority to DE112006002337T priority patent/DE112006002337T5/de
Publication of WO2007038033A2 publication Critical patent/WO2007038033A2/fr
Publication of WO2007038033A3 publication Critical patent/WO2007038033A3/fr

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31922—Timing generation or clock distribution
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31725—Timing aspects, e.g. clock distribution, skew, propagation delay
    • G01R31/31726—Synchronization, e.g. of test, clock or strobe signals; Signals in different clock domains; Generation of Vernier signals; Comparison and adjustment of the signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/153—Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time interval after this instant
    • H03K5/1534—Transition or edge detectors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0079—Receiver details
    • H04L7/0083—Receiver details taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Logic Circuits (AREA)
  • Manipulation Of Pulses (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Power Sources (AREA)

Abstract

Le dispositif décrit comprend deux bascules à verrouillage qui enregistrent l'état d'un signal de données lors de la transition d'un signal d'horloge. Une logique de comparaison compare les sorties des deux bascules à verrouillage et produit un signal indiquant si les sorties sont égales ou différentes. L'invention concerne des systèmes utilisant ces bascules à verrouillage et une logique de comparaison.
PCT/US2006/036153 2005-09-23 2006-09-14 Procede et dispositif permettant la detection d'une transition de synchronisation tardive WO2007038033A2 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN2006800346785A CN101268615B (zh) 2005-09-23 2006-09-14 用于迟滞时序转变检测的方法和装置
DE112006002337T DE112006002337T5 (de) 2005-09-23 2006-09-14 Verfahren und Vorrichtung zur Detektion verspäteter Timing-Übergänge

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/234,548 US7622961B2 (en) 2005-09-23 2005-09-23 Method and apparatus for late timing transition detection
US11/234,548 2005-09-23

Publications (2)

Publication Number Publication Date
WO2007038033A2 WO2007038033A2 (fr) 2007-04-05
WO2007038033A3 true WO2007038033A3 (fr) 2007-06-21

Family

ID=37836868

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/036153 WO2007038033A2 (fr) 2005-09-23 2006-09-14 Procede et dispositif permettant la detection d'une transition de synchronisation tardive

Country Status (4)

Country Link
US (2) US7622961B2 (fr)
CN (1) CN101268615B (fr)
DE (1) DE112006002337T5 (fr)
WO (1) WO2007038033A2 (fr)

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US8032804B2 (en) * 2009-01-12 2011-10-04 Micron Technology, Inc. Systems and methods for monitoring a memory system
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US8499265B2 (en) * 2011-02-14 2013-07-30 Nanya Technology Corporation Circuit for detecting and preventing setup fails and the method thereof
WO2013048398A1 (fr) * 2011-09-28 2013-04-04 Intel Corporation Appareil et procédé de surveillance du vieillissement autonome au niveau du chemin
US8762804B2 (en) * 2012-08-06 2014-06-24 Texas Instruments Incorporated Error prediction in logic and memory devices
TWI489245B (zh) * 2012-12-04 2015-06-21 Univ Nat Cheng Kung 具有能預測因製程與環境變異所造成時序錯誤的嵌入式脈衝時序電路系統
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DE102013211372A1 (de) * 2013-06-18 2014-12-18 Aalto University Foundation Steuerungsmechanismus basiert auf zeitverhaltensinformation
WO2015035330A1 (fr) 2013-09-06 2015-03-12 Futurewei Technologies, Inc. Procédé et appareil permettant d'éliminer une métastabilité d'un processeur asynchrone
EP2858244A1 (fr) * 2013-10-02 2015-04-08 Aalto University Foundation Prévention de violations de synchronisation
WO2015094373A1 (fr) * 2013-12-20 2015-06-25 Intel Corporation Appareil et procédé de réduction de bande de garde adaptative
CN104952382A (zh) * 2014-03-24 2015-09-30 昆达电脑科技(昆山)有限公司 液晶电视影像传输前后比对装置
US9755653B2 (en) 2014-11-05 2017-09-05 Mediatek Inc. Phase detector
US9231591B1 (en) * 2014-12-12 2016-01-05 Xilinx, Inc. Dynamic voltage scaling in programmable integrated circuits
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EP3867657B1 (fr) * 2018-10-16 2024-03-27 Minima Processor Oy Applications de circuits micro-électroniques adaptatifs conçus pour une testabilité
WO2020115353A1 (fr) 2018-12-05 2020-06-11 Minima Processor Oy Circuit microélectronique capable d'activer sélectivement des trajets de traitement, et procédé d'activation de trajets de traitement dans un circuit microélectronique
US11074150B2 (en) 2019-04-19 2021-07-27 Nxp B.V. Chip health monitor
EP3923472A1 (fr) 2020-06-08 2021-12-15 Nxp B.V. Circuit de détection et de correction d'erreurs de synchronisation

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Also Published As

Publication number Publication date
CN101268615B (zh) 2012-06-06
US20070164787A1 (en) 2007-07-19
CN101268615A (zh) 2008-09-17
US20100052730A1 (en) 2010-03-04
US8125246B2 (en) 2012-02-28
WO2007038033A2 (fr) 2007-04-05
US7622961B2 (en) 2009-11-24
DE112006002337T5 (de) 2008-06-19

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